Lines Matching +full:1 +full:- +full:sd
1 // SPDX-License-Identifier: GPL-2.0-only
3 * adv7604 - Analog Devices ADV7604 video decoder driver
11 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
13 * REF_02 - Analog devices, Register map documentation, Documentation of
15 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
26 #include <linux/v4l2-dv-timings.h>
34 #include <media/v4l2-ctrls.h>
35 #include <media/v4l2-device.h>
36 #include <media/v4l2-event.h>
37 #include <media/v4l2-dv-timings.h>
38 #include <media/v4l2-fwnode.h>
42 MODULE_PARM_DESC(debug, "debug level (0-2)");
52 #define ADV76XX_RGB_OUT (1 << 1)
55 #define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0)
59 #define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5)
66 #define ADV76XX_OP_CH_SEL_GRB (1 << 5)
72 #define ADV76XX_OP_SWAP_CB_CR (1 << 0)
126 void (*set_termination)(struct v4l2_subdev *sd, bool enable);
127 void (*setup_irqs)(struct v4l2_subdev *sd);
128 unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
129 unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
131 /* 0 = AFE, 1 = HDMI */
167 struct v4l2_subdev sd; member
211 return state->info->has_afe; in adv76xx_has_afe()
318 /* ----------------------------------------------------------------------- */
320 static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd) in to_state() argument
322 return container_of(sd, struct adv76xx_state, sd); in to_state()
335 /* ----------------------------------------------------------------------- */
340 struct i2c_client *client = state->i2c_clients[client_page]; in adv76xx_read_check()
344 err = regmap_read(state->regmap[client_page], reg, &val); in adv76xx_read_check()
348 client->addr, reg); in adv76xx_read_check()
364 struct regmap *regmap = state->regmap[client_page]; in adv76xx_write_block()
372 /* ----------------------------------------------------------------------- */
374 static inline int io_read(struct v4l2_subdev *sd, u8 reg) in io_read() argument
376 struct adv76xx_state *state = to_state(sd); in io_read()
381 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val) in io_write() argument
383 struct adv76xx_state *state = to_state(sd); in io_write()
385 return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val); in io_write()
388 static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, in io_write_clr_set() argument
391 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val); in io_write_clr_set()
394 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg) in avlink_read() argument
396 struct adv76xx_state *state = to_state(sd); in avlink_read()
401 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val) in avlink_write() argument
403 struct adv76xx_state *state = to_state(sd); in avlink_write()
405 return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val); in avlink_write()
408 static inline int cec_read(struct v4l2_subdev *sd, u8 reg) in cec_read() argument
410 struct adv76xx_state *state = to_state(sd); in cec_read()
415 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val) in cec_write() argument
417 struct adv76xx_state *state = to_state(sd); in cec_write()
419 return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val); in cec_write()
422 static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, in cec_write_clr_set() argument
425 return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val); in cec_write_clr_set()
428 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg) in infoframe_read() argument
430 struct adv76xx_state *state = to_state(sd); in infoframe_read()
435 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val) in infoframe_write() argument
437 struct adv76xx_state *state = to_state(sd); in infoframe_write()
439 return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val); in infoframe_write()
442 static inline int afe_read(struct v4l2_subdev *sd, u8 reg) in afe_read() argument
444 struct adv76xx_state *state = to_state(sd); in afe_read()
449 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val) in afe_write() argument
451 struct adv76xx_state *state = to_state(sd); in afe_write()
453 return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val); in afe_write()
456 static inline int rep_read(struct v4l2_subdev *sd, u8 reg) in rep_read() argument
458 struct adv76xx_state *state = to_state(sd); in rep_read()
463 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val) in rep_write() argument
465 struct adv76xx_state *state = to_state(sd); in rep_write()
467 return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val); in rep_write()
470 static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) in rep_write_clr_set() argument
472 return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val); in rep_write_clr_set()
475 static inline int edid_read(struct v4l2_subdev *sd, u8 reg) in edid_read() argument
477 struct adv76xx_state *state = to_state(sd); in edid_read()
482 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val) in edid_write() argument
484 struct adv76xx_state *state = to_state(sd); in edid_write()
486 return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val); in edid_write()
489 static inline int edid_write_block(struct v4l2_subdev *sd, in edid_write_block() argument
492 struct adv76xx_state *state = to_state(sd); in edid_write_block()
497 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", in edid_write_block()
501 len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ? in edid_write_block()
503 (total_len - i); in edid_write_block()
517 for (i = 0; i < state->info->num_dv_ports; ++i) in adv76xx_set_hpd()
518 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i)); in adv76xx_set_hpd()
520 v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd); in adv76xx_set_hpd()
528 struct v4l2_subdev *sd = &state->sd; in adv76xx_delayed_work_enable_hotplug() local
530 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__); in adv76xx_delayed_work_enable_hotplug()
532 adv76xx_set_hpd(state, state->edid.present); in adv76xx_delayed_work_enable_hotplug()
535 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg) in hdmi_read() argument
537 struct adv76xx_state *state = to_state(sd); in hdmi_read()
542 static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) in hdmi_read16() argument
544 return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask; in hdmi_read16()
547 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val) in hdmi_write() argument
549 struct adv76xx_state *state = to_state(sd); in hdmi_write()
551 return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val); in hdmi_write()
554 static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) in hdmi_write_clr_set() argument
556 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val); in hdmi_write_clr_set()
559 static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val) in test_write() argument
561 struct adv76xx_state *state = to_state(sd); in test_write()
563 return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val); in test_write()
566 static inline int cp_read(struct v4l2_subdev *sd, u8 reg) in cp_read() argument
568 struct adv76xx_state *state = to_state(sd); in cp_read()
573 static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask) in cp_read16() argument
575 return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask; in cp_read16()
578 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val) in cp_write() argument
580 struct adv76xx_state *state = to_state(sd); in cp_write()
582 return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val); in cp_write()
585 static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val) in cp_write_clr_set() argument
587 return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val); in cp_write_clr_set()
590 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg) in vdp_read() argument
592 struct adv76xx_state *state = to_state(sd); in vdp_read()
597 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val) in vdp_write() argument
599 struct adv76xx_state *state = to_state(sd); in vdp_write()
601 return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val); in vdp_write()
608 static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg) in adv76xx_read_reg() argument
610 struct adv76xx_state *state = to_state(sd); in adv76xx_read_reg()
615 if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask)) in adv76xx_read_reg()
616 return -EINVAL; in adv76xx_read_reg()
619 err = regmap_read(state->regmap[page], reg, &val); in adv76xx_read_reg()
625 static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val) in adv76xx_write_reg() argument
627 struct adv76xx_state *state = to_state(sd); in adv76xx_write_reg()
630 if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask)) in adv76xx_write_reg()
631 return -EINVAL; in adv76xx_write_reg()
635 return regmap_write(state->regmap[page], reg, val); in adv76xx_write_reg()
638 static void adv76xx_write_reg_seq(struct v4l2_subdev *sd, in adv76xx_write_reg_seq() argument
644 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val); in adv76xx_write_reg_seq()
647 /* -----------------------------------------------------------------------------
743 for (i = 0; i < state->info->nformats; ++i) { in adv76xx_format_info()
744 if (state->info->formats[i].code == code) in adv76xx_format_info()
745 return &state->info->formats[i]; in adv76xx_format_info()
751 /* ----------------------------------------------------------------------- */
753 static inline bool is_analog_input(struct v4l2_subdev *sd) in is_analog_input() argument
755 struct adv76xx_state *state = to_state(sd); in is_analog_input()
757 return state->selected_input == ADV7604_PAD_VGA_RGB || in is_analog_input()
758 state->selected_input == ADV7604_PAD_VGA_COMP; in is_analog_input()
761 static inline bool is_digital_input(struct v4l2_subdev *sd) in is_digital_input() argument
763 struct adv76xx_state *state = to_state(sd); in is_digital_input()
765 return state->selected_input == ADV76XX_PAD_HDMI_PORT_A || in is_digital_input()
766 state->selected_input == ADV7604_PAD_HDMI_PORT_B || in is_digital_input()
767 state->selected_input == ADV7604_PAD_HDMI_PORT_C || in is_digital_input()
768 state->selected_input == ADV7604_PAD_HDMI_PORT_D; in is_digital_input()
795 * case, pad value -1 returns the capabilities for the currently selected input.
798 adv76xx_get_dv_timings_cap(struct v4l2_subdev *sd, int pad) in adv76xx_get_dv_timings_cap() argument
800 if (pad == -1) { in adv76xx_get_dv_timings_cap()
801 struct adv76xx_state *state = to_state(sd); in adv76xx_get_dv_timings_cap()
803 pad = state->selected_input; in adv76xx_get_dv_timings_cap()
821 /* ----------------------------------------------------------------------- */
824 static void adv76xx_inv_register(struct v4l2_subdev *sd) in adv76xx_inv_register() argument
826 v4l2_info(sd, "0x000-0x0ff: IO Map\n"); in adv76xx_inv_register()
827 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n"); in adv76xx_inv_register()
828 v4l2_info(sd, "0x200-0x2ff: CEC Map\n"); in adv76xx_inv_register()
829 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n"); in adv76xx_inv_register()
830 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n"); in adv76xx_inv_register()
831 v4l2_info(sd, "0x500-0x5ff: DPP Map\n"); in adv76xx_inv_register()
832 v4l2_info(sd, "0x600-0x6ff: AFE Map\n"); in adv76xx_inv_register()
833 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n"); in adv76xx_inv_register()
834 v4l2_info(sd, "0x800-0x8ff: EDID Map\n"); in adv76xx_inv_register()
835 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n"); in adv76xx_inv_register()
836 v4l2_info(sd, "0xa00-0xaff: Test Map\n"); in adv76xx_inv_register()
837 v4l2_info(sd, "0xb00-0xbff: CP Map\n"); in adv76xx_inv_register()
838 v4l2_info(sd, "0xc00-0xcff: VDP Map\n"); in adv76xx_inv_register()
841 static int adv76xx_g_register(struct v4l2_subdev *sd, in adv76xx_g_register() argument
846 ret = adv76xx_read_reg(sd, reg->reg); in adv76xx_g_register()
848 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); in adv76xx_g_register()
849 adv76xx_inv_register(sd); in adv76xx_g_register()
853 reg->size = 1; in adv76xx_g_register()
854 reg->val = ret; in adv76xx_g_register()
859 static int adv76xx_s_register(struct v4l2_subdev *sd, in adv76xx_s_register() argument
864 ret = adv76xx_write_reg(sd, reg->reg, reg->val); in adv76xx_s_register()
866 v4l2_info(sd, "Register %03llx not supported\n", reg->reg); in adv76xx_s_register()
867 adv76xx_inv_register(sd); in adv76xx_s_register()
875 static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd) in adv7604_read_cable_det() argument
877 u8 value = io_read(sd, 0x6f); in adv7604_read_cable_det()
885 static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd) in adv7611_read_cable_det() argument
887 u8 value = io_read(sd, 0x6f); in adv7611_read_cable_det()
889 return value & 1; in adv7611_read_cable_det()
892 static unsigned int adv7612_read_cable_det(struct v4l2_subdev *sd) in adv7612_read_cable_det() argument
897 u8 value = io_read(sd, 0x6f); in adv7612_read_cable_det()
899 return value & 1; in adv7612_read_cable_det()
902 static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd) in adv76xx_s_detect_tx_5v_ctrl() argument
904 struct adv76xx_state *state = to_state(sd); in adv76xx_s_detect_tx_5v_ctrl()
905 const struct adv76xx_chip_info *info = state->info; in adv76xx_s_detect_tx_5v_ctrl()
906 u16 cable_det = info->read_cable_det(sd); in adv76xx_s_detect_tx_5v_ctrl()
908 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det); in adv76xx_s_detect_tx_5v_ctrl()
911 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd, in find_and_set_predefined_video_timings() argument
920 is_digital_input(sd) ? 250000 : 1000000, false)) in find_and_set_predefined_video_timings()
922 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */ in find_and_set_predefined_video_timings()
923 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + in find_and_set_predefined_video_timings()
928 return -1; in find_and_set_predefined_video_timings()
931 static int configure_predefined_video_timings(struct v4l2_subdev *sd, in configure_predefined_video_timings() argument
934 struct adv76xx_state *state = to_state(sd); in configure_predefined_video_timings()
937 v4l2_dbg(1, debug, sd, "%s", __func__); in configure_predefined_video_timings()
941 io_write(sd, 0x16, 0x43); in configure_predefined_video_timings()
942 io_write(sd, 0x17, 0x5a); in configure_predefined_video_timings()
945 cp_write_clr_set(sd, 0x81, 0x10, 0x00); in configure_predefined_video_timings()
946 cp_write(sd, 0x8f, 0x00); in configure_predefined_video_timings()
947 cp_write(sd, 0x90, 0x00); in configure_predefined_video_timings()
948 cp_write(sd, 0xa2, 0x00); in configure_predefined_video_timings()
949 cp_write(sd, 0xa3, 0x00); in configure_predefined_video_timings()
950 cp_write(sd, 0xa4, 0x00); in configure_predefined_video_timings()
951 cp_write(sd, 0xa5, 0x00); in configure_predefined_video_timings()
952 cp_write(sd, 0xa6, 0x00); in configure_predefined_video_timings()
953 cp_write(sd, 0xa7, 0x00); in configure_predefined_video_timings()
954 cp_write(sd, 0xab, 0x00); in configure_predefined_video_timings()
955 cp_write(sd, 0xac, 0x00); in configure_predefined_video_timings()
957 if (is_analog_input(sd)) { in configure_predefined_video_timings()
958 err = find_and_set_predefined_video_timings(sd, in configure_predefined_video_timings()
961 err = find_and_set_predefined_video_timings(sd, in configure_predefined_video_timings()
963 } else if (is_digital_input(sd)) { in configure_predefined_video_timings()
964 err = find_and_set_predefined_video_timings(sd, in configure_predefined_video_timings()
967 err = find_and_set_predefined_video_timings(sd, in configure_predefined_video_timings()
970 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", in configure_predefined_video_timings()
971 __func__, state->selected_input); in configure_predefined_video_timings()
972 err = -1; in configure_predefined_video_timings()
979 static void configure_custom_video_timings(struct v4l2_subdev *sd, in configure_custom_video_timings() argument
982 struct adv76xx_state *state = to_state(sd); in configure_custom_video_timings()
985 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4; in configure_custom_video_timings()
986 u16 cp_start_eav = width - bt->hfrontporch; in configure_custom_video_timings()
987 u16 cp_start_vbi = height - bt->vfrontporch; in configure_custom_video_timings()
988 u16 cp_end_vbi = bt->vsync + bt->vbackporch; in configure_custom_video_timings()
989 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ? in configure_custom_video_timings()
990 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0; in configure_custom_video_timings()
996 v4l2_dbg(2, debug, sd, "%s\n", __func__); in configure_custom_video_timings()
998 if (is_analog_input(sd)) { in configure_custom_video_timings()
1000 io_write(sd, 0x00, 0x07); /* video std */ in configure_custom_video_timings()
1001 io_write(sd, 0x01, 0x02); /* prim mode */ in configure_custom_video_timings()
1003 cp_write_clr_set(sd, 0x81, 0x10, 0x10); in configure_custom_video_timings()
1005 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */ in configure_custom_video_timings()
1007 /* IO-map reg. 0x16 and 0x17 should be written in sequence */ in configure_custom_video_timings()
1008 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO], in configure_custom_video_timings()
1010 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n"); in configure_custom_video_timings()
1012 /* active video - horizontal timing */ in configure_custom_video_timings()
1013 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff); in configure_custom_video_timings()
1014 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) | in configure_custom_video_timings()
1016 cp_write(sd, 0xa4, cp_start_eav & 0xff); in configure_custom_video_timings()
1018 /* active video - vertical timing */ in configure_custom_video_timings()
1019 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff); in configure_custom_video_timings()
1020 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) | in configure_custom_video_timings()
1022 cp_write(sd, 0xa7, cp_end_vbi & 0xff); in configure_custom_video_timings()
1023 } else if (is_digital_input(sd)) { in configure_custom_video_timings()
1026 io_write(sd, 0x00, 0x02); /* video std */ in configure_custom_video_timings()
1027 io_write(sd, 0x01, 0x06); /* prim mode */ in configure_custom_video_timings()
1029 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", in configure_custom_video_timings()
1030 __func__, state->selected_input); in configure_custom_video_timings()
1033 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7); in configure_custom_video_timings()
1034 cp_write(sd, 0x90, ch1_fr_ll & 0xff); in configure_custom_video_timings()
1035 cp_write(sd, 0xab, (height >> 4) & 0xff); in configure_custom_video_timings()
1036 cp_write(sd, 0xac, (height & 0x0f) << 4); in configure_custom_video_timings()
1039 static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b… in adv76xx_set_offset() argument
1041 struct adv76xx_state *state = to_state(sd); in adv76xx_set_offset()
1050 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n", in adv76xx_set_offset()
1054 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4); in adv76xx_set_offset()
1055 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6); in adv76xx_set_offset()
1060 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP], in adv76xx_set_offset()
1062 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__); in adv76xx_set_offset()
1065 static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 ga… in adv76xx_set_gain() argument
1067 struct adv76xx_state *state = to_state(sd); in adv76xx_set_gain()
1069 u8 gain_man = 1; in adv76xx_set_gain()
1070 u8 agc_mode_man = 1; in adv76xx_set_gain()
1080 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n", in adv76xx_set_gain()
1085 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6)); in adv76xx_set_gain()
1090 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP], in adv76xx_set_gain()
1092 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__); in adv76xx_set_gain()
1095 static void set_rgb_quantization_range(struct v4l2_subdev *sd) in set_rgb_quantization_range() argument
1097 struct adv76xx_state *state = to_state(sd); in set_rgb_quantization_range()
1098 bool rgb_output = io_read(sd, 0x02) & 0x02; in set_rgb_quantization_range()
1099 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; in set_rgb_quantization_range()
1102 if (hdmi_signal && (io_read(sd, 0x60) & 1)) in set_rgb_quantization_range()
1103 y = infoframe_read(sd, 0x01) >> 5; in set_rgb_quantization_range()
1105 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n", in set_rgb_quantization_range()
1106 __func__, state->rgb_quantization_range, in set_rgb_quantization_range()
1109 adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0); in set_rgb_quantization_range()
1110 adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0); in set_rgb_quantization_range()
1111 io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4); in set_rgb_quantization_range()
1113 switch (state->rgb_quantization_range) { in set_rgb_quantization_range()
1115 if (state->selected_input == ADV7604_PAD_VGA_RGB) { in set_rgb_quantization_range()
1117 * Set RGB full range (0-255) */ in set_rgb_quantization_range()
1118 io_write_clr_set(sd, 0x02, 0xf0, 0x10); in set_rgb_quantization_range()
1122 if (state->selected_input == ADV7604_PAD_VGA_COMP) { in set_rgb_quantization_range()
1125 io_write_clr_set(sd, 0x02, 0xf0, 0xf0); in set_rgb_quantization_range()
1132 io_write_clr_set(sd, 0x02, 0xf0, 0xf0); in set_rgb_quantization_range()
1136 /* Receiving DVI-D signal in set_rgb_quantization_range()
1139 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) { in set_rgb_quantization_range()
1140 /* RGB limited range (16-235) */ in set_rgb_quantization_range()
1141 io_write_clr_set(sd, 0x02, 0xf0, 0x00); in set_rgb_quantization_range()
1143 /* RGB full range (0-255) */ in set_rgb_quantization_range()
1144 io_write_clr_set(sd, 0x02, 0xf0, 0x10); in set_rgb_quantization_range()
1146 if (is_digital_input(sd) && rgb_output) { in set_rgb_quantization_range()
1147 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40); in set_rgb_quantization_range()
1149 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0); in set_rgb_quantization_range()
1150 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70); in set_rgb_quantization_range()
1155 if (state->selected_input == ADV7604_PAD_VGA_COMP) { in set_rgb_quantization_range()
1156 /* YCrCb limited range (16-235) */ in set_rgb_quantization_range()
1157 io_write_clr_set(sd, 0x02, 0xf0, 0x20); in set_rgb_quantization_range()
1164 /* RGB limited range (16-235) */ in set_rgb_quantization_range()
1165 io_write_clr_set(sd, 0x02, 0xf0, 0x00); in set_rgb_quantization_range()
1169 if (state->selected_input == ADV7604_PAD_VGA_COMP) { in set_rgb_quantization_range()
1170 /* YCrCb full range (0-255) */ in set_rgb_quantization_range()
1171 io_write_clr_set(sd, 0x02, 0xf0, 0x60); in set_rgb_quantization_range()
1178 /* RGB full range (0-255) */ in set_rgb_quantization_range()
1179 io_write_clr_set(sd, 0x02, 0xf0, 0x10); in set_rgb_quantization_range()
1181 if (is_analog_input(sd) || hdmi_signal) in set_rgb_quantization_range()
1184 /* Adjust gain/offset for DVI-D signals only */ in set_rgb_quantization_range()
1186 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40); in set_rgb_quantization_range()
1188 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0); in set_rgb_quantization_range()
1189 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70); in set_rgb_quantization_range()
1197 struct v4l2_subdev *sd = in adv76xx_s_ctrl() local
1198 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd; in adv76xx_s_ctrl()
1200 struct adv76xx_state *state = to_state(sd); in adv76xx_s_ctrl()
1202 switch (ctrl->id) { in adv76xx_s_ctrl()
1204 cp_write(sd, 0x3c, ctrl->val); in adv76xx_s_ctrl()
1207 cp_write(sd, 0x3a, ctrl->val); in adv76xx_s_ctrl()
1210 cp_write(sd, 0x3b, ctrl->val); in adv76xx_s_ctrl()
1213 cp_write(sd, 0x3d, ctrl->val); in adv76xx_s_ctrl()
1216 state->rgb_quantization_range = ctrl->val; in adv76xx_s_ctrl()
1217 set_rgb_quantization_range(sd); in adv76xx_s_ctrl()
1221 return -EINVAL; in adv76xx_s_ctrl()
1226 afe_write(sd, 0xc8, ctrl->val); in adv76xx_s_ctrl()
1231 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2); in adv76xx_s_ctrl()
1234 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16); in adv76xx_s_ctrl()
1235 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8); in adv76xx_s_ctrl()
1236 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff)); in adv76xx_s_ctrl()
1239 return -EINVAL; in adv76xx_s_ctrl()
1244 struct v4l2_subdev *sd = in adv76xx_g_volatile_ctrl() local
1245 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd; in adv76xx_g_volatile_ctrl()
1247 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) { in adv76xx_g_volatile_ctrl()
1248 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC; in adv76xx_g_volatile_ctrl()
1249 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80)) in adv76xx_g_volatile_ctrl()
1250 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3; in adv76xx_g_volatile_ctrl()
1253 return -EINVAL; in adv76xx_g_volatile_ctrl()
1256 /* ----------------------------------------------------------------------- */
1258 static inline bool no_power(struct v4l2_subdev *sd) in no_power() argument
1261 return io_read(sd, 0x0c) & 0x24; in no_power()
1264 static inline bool no_signal_tmds(struct v4l2_subdev *sd) in no_signal_tmds() argument
1266 struct adv76xx_state *state = to_state(sd); in no_signal_tmds()
1268 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input)); in no_signal_tmds()
1271 static inline bool no_lock_tmds(struct v4l2_subdev *sd) in no_lock_tmds() argument
1273 struct adv76xx_state *state = to_state(sd); in no_lock_tmds()
1274 const struct adv76xx_chip_info *info = state->info; in no_lock_tmds()
1276 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask; in no_lock_tmds()
1279 static inline bool is_hdmi(struct v4l2_subdev *sd) in is_hdmi() argument
1281 return hdmi_read(sd, 0x05) & 0x80; in is_hdmi()
1284 static inline bool no_lock_sspd(struct v4l2_subdev *sd) in no_lock_sspd() argument
1286 struct adv76xx_state *state = to_state(sd); in no_lock_sspd()
1296 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0); in no_lock_sspd()
1299 static inline bool no_lock_stdi(struct v4l2_subdev *sd) in no_lock_stdi() argument
1302 return !(cp_read(sd, 0xb1) & 0x80); in no_lock_stdi()
1305 static inline bool no_signal(struct v4l2_subdev *sd) in no_signal() argument
1309 ret = no_power(sd); in no_signal()
1311 ret |= no_lock_stdi(sd); in no_signal()
1312 ret |= no_lock_sspd(sd); in no_signal()
1314 if (is_digital_input(sd)) { in no_signal()
1315 ret |= no_lock_tmds(sd); in no_signal()
1316 ret |= no_signal_tmds(sd); in no_signal()
1322 static inline bool no_lock_cp(struct v4l2_subdev *sd) in no_lock_cp() argument
1324 struct adv76xx_state *state = to_state(sd); in no_lock_cp()
1331 return io_read(sd, 0x12) & 0x01; in no_lock_cp()
1334 static inline bool in_free_run(struct v4l2_subdev *sd) in in_free_run() argument
1336 return cp_read(sd, 0xff) & 0x10; in in_free_run()
1339 static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status) in adv76xx_g_input_status() argument
1342 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0; in adv76xx_g_input_status()
1343 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0; in adv76xx_g_input_status()
1344 if (!in_free_run(sd) && no_lock_cp(sd)) in adv76xx_g_input_status()
1345 *status |= is_digital_input(sd) ? in adv76xx_g_input_status()
1348 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status); in adv76xx_g_input_status()
1353 /* ----------------------------------------------------------------------- */
1361 static int stdi2dv_timings(struct v4l2_subdev *sd, in stdi2dv_timings() argument
1365 struct adv76xx_state *state = to_state(sd); in stdi2dv_timings()
1366 u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl; in stdi2dv_timings()
1374 adv76xx_get_dv_timings_cap(sd, -1), in stdi2dv_timings()
1377 if (vtotal(bt) != stdi->lcf + 1) in stdi2dv_timings()
1379 if (bt->vsync != stdi->lcvs) in stdi2dv_timings()
1384 if ((pix_clk < bt->pixelclock + 1000000) && in stdi2dv_timings()
1385 (pix_clk > bt->pixelclock - 1000000)) { in stdi2dv_timings()
1391 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0, in stdi2dv_timings()
1392 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | in stdi2dv_timings()
1393 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), in stdi2dv_timings()
1396 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs, in stdi2dv_timings()
1397 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) | in stdi2dv_timings()
1398 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0), in stdi2dv_timings()
1399 false, state->aspect_ratio, timings)) in stdi2dv_timings()
1402 v4l2_dbg(2, debug, sd, in stdi2dv_timings()
1404 __func__, stdi->lcvs, stdi->lcf, stdi->bl, in stdi2dv_timings()
1405 stdi->hs_pol, stdi->vs_pol); in stdi2dv_timings()
1406 return -1; in stdi2dv_timings()
1410 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi) in read_stdi() argument
1412 struct adv76xx_state *state = to_state(sd); in read_stdi()
1413 const struct adv76xx_chip_info *info = state->info; in read_stdi()
1416 if (no_lock_stdi(sd) || no_lock_sspd(sd)) { in read_stdi()
1417 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__); in read_stdi()
1418 return -1; in read_stdi()
1422 stdi->bl = cp_read16(sd, 0xb1, 0x3fff); in read_stdi()
1423 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff); in read_stdi()
1424 stdi->lcvs = cp_read(sd, 0xb3) >> 3; in read_stdi()
1425 stdi->interlaced = io_read(sd, 0x12) & 0x10; in read_stdi()
1429 polarity = cp_read(sd, 0xb5); in read_stdi()
1431 stdi->hs_pol = polarity & 0x10 in read_stdi()
1432 ? (polarity & 0x08 ? '+' : '-') : 'x'; in read_stdi()
1433 stdi->vs_pol = polarity & 0x40 in read_stdi()
1434 ? (polarity & 0x20 ? '+' : '-') : 'x'; in read_stdi()
1436 stdi->hs_pol = 'x'; in read_stdi()
1437 stdi->vs_pol = 'x'; in read_stdi()
1440 polarity = hdmi_read(sd, 0x05); in read_stdi()
1441 stdi->hs_pol = polarity & 0x20 ? '+' : '-'; in read_stdi()
1442 stdi->vs_pol = polarity & 0x10 ? '+' : '-'; in read_stdi()
1445 if (no_lock_stdi(sd) || no_lock_sspd(sd)) { in read_stdi()
1446 v4l2_dbg(2, debug, sd, in read_stdi()
1448 return -1; in read_stdi()
1451 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) { in read_stdi()
1452 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__); in read_stdi()
1454 return -1; in read_stdi()
1457 v4l2_dbg(2, debug, sd, in read_stdi()
1458 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n", in read_stdi()
1459 __func__, stdi->lcf, stdi->bl, stdi->lcvs, in read_stdi()
1460 stdi->hs_pol, stdi->vs_pol, in read_stdi()
1461 stdi->interlaced ? "interlaced" : "progressive"); in read_stdi()
1466 static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd, in adv76xx_enum_dv_timings() argument
1469 struct adv76xx_state *state = to_state(sd); in adv76xx_enum_dv_timings()
1471 if (timings->pad >= state->source_pad) in adv76xx_enum_dv_timings()
1472 return -EINVAL; in adv76xx_enum_dv_timings()
1475 adv76xx_get_dv_timings_cap(sd, timings->pad), in adv76xx_enum_dv_timings()
1479 static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd, in adv76xx_dv_timings_cap() argument
1482 struct adv76xx_state *state = to_state(sd); in adv76xx_dv_timings_cap()
1483 unsigned int pad = cap->pad; in adv76xx_dv_timings_cap()
1485 if (cap->pad >= state->source_pad) in adv76xx_dv_timings_cap()
1486 return -EINVAL; in adv76xx_dv_timings_cap()
1488 *cap = *adv76xx_get_dv_timings_cap(sd, pad); in adv76xx_dv_timings_cap()
1489 cap->pad = pad; in adv76xx_dv_timings_cap()
1496 static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd, in adv76xx_fill_optional_dv_timings_fields() argument
1499 v4l2_find_dv_timings_cap(timings, adv76xx_get_dv_timings_cap(sd, -1), in adv76xx_fill_optional_dv_timings_fields()
1500 is_digital_input(sd) ? 250000 : 1000000, in adv76xx_fill_optional_dv_timings_fields()
1504 static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd) in adv7604_read_hdmi_pixelclock() argument
1508 a = hdmi_read(sd, 0x06); in adv7604_read_hdmi_pixelclock()
1509 b = hdmi_read(sd, 0x3b); in adv7604_read_hdmi_pixelclock()
1516 static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd) in adv7611_read_hdmi_pixelclock() argument
1520 a = hdmi_read(sd, 0x51); in adv7611_read_hdmi_pixelclock()
1521 b = hdmi_read(sd, 0x52); in adv7611_read_hdmi_pixelclock()
1525 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128; in adv7611_read_hdmi_pixelclock()
1528 static unsigned int adv76xx_read_hdmi_pixelclock(struct v4l2_subdev *sd) in adv76xx_read_hdmi_pixelclock() argument
1530 struct adv76xx_state *state = to_state(sd); in adv76xx_read_hdmi_pixelclock()
1531 const struct adv76xx_chip_info *info = state->info; in adv76xx_read_hdmi_pixelclock()
1534 freq = info->read_hdmi_pixelclock(sd); in adv76xx_read_hdmi_pixelclock()
1535 if (is_hdmi(sd)) { in adv76xx_read_hdmi_pixelclock()
1537 bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8; in adv76xx_read_hdmi_pixelclock()
1538 pixelrepetition = (hdmi_read(sd, 0x05) & 0x0f) + 1; in adv76xx_read_hdmi_pixelclock()
1546 static int adv76xx_query_dv_timings(struct v4l2_subdev *sd, in adv76xx_query_dv_timings() argument
1549 struct adv76xx_state *state = to_state(sd); in adv76xx_query_dv_timings()
1550 const struct adv76xx_chip_info *info = state->info; in adv76xx_query_dv_timings()
1551 struct v4l2_bt_timings *bt = &timings->bt; in adv76xx_query_dv_timings()
1555 return -EINVAL; in adv76xx_query_dv_timings()
1559 if (no_signal(sd)) { in adv76xx_query_dv_timings()
1560 state->restart_stdi_once = true; in adv76xx_query_dv_timings()
1561 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__); in adv76xx_query_dv_timings()
1562 return -ENOLINK; in adv76xx_query_dv_timings()
1566 if (read_stdi(sd, &stdi)) { in adv76xx_query_dv_timings()
1567 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__); in adv76xx_query_dv_timings()
1568 return -ENOLINK; in adv76xx_query_dv_timings()
1570 bt->interlaced = stdi.interlaced ? in adv76xx_query_dv_timings()
1573 if (is_digital_input(sd)) { in adv76xx_query_dv_timings()
1574 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80; in adv76xx_query_dv_timings()
1578 w = hdmi_read16(sd, 0x07, info->linewidth_mask); in adv76xx_query_dv_timings()
1579 h = hdmi_read16(sd, 0x09, info->field0_height_mask); in adv76xx_query_dv_timings()
1581 if (hdmi_signal && (io_read(sd, 0x60) & 1)) in adv76xx_query_dv_timings()
1582 vic = infoframe_read(sd, 0x04); in adv76xx_query_dv_timings()
1585 bt->width == w && bt->height == h) in adv76xx_query_dv_timings()
1588 timings->type = V4L2_DV_BT_656_1120; in adv76xx_query_dv_timings()
1590 bt->width = w; in adv76xx_query_dv_timings()
1591 bt->height = h; in adv76xx_query_dv_timings()
1592 bt->pixelclock = adv76xx_read_hdmi_pixelclock(sd); in adv76xx_query_dv_timings()
1593 bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask); in adv76xx_query_dv_timings()
1594 bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask); in adv76xx_query_dv_timings()
1595 bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask); in adv76xx_query_dv_timings()
1596 bt->vfrontporch = hdmi_read16(sd, 0x2a, in adv76xx_query_dv_timings()
1597 info->field0_vfrontporch_mask) / 2; in adv76xx_query_dv_timings()
1598 bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2; in adv76xx_query_dv_timings()
1599 bt->vbackporch = hdmi_read16(sd, 0x32, in adv76xx_query_dv_timings()
1600 info->field0_vbackporch_mask) / 2; in adv76xx_query_dv_timings()
1601 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) | in adv76xx_query_dv_timings()
1602 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0); in adv76xx_query_dv_timings()
1603 if (bt->interlaced == V4L2_DV_INTERLACED) { in adv76xx_query_dv_timings()
1604 bt->height += hdmi_read16(sd, 0x0b, in adv76xx_query_dv_timings()
1605 info->field1_height_mask); in adv76xx_query_dv_timings()
1606 bt->il_vfrontporch = hdmi_read16(sd, 0x2c, in adv76xx_query_dv_timings()
1607 info->field1_vfrontporch_mask) / 2; in adv76xx_query_dv_timings()
1608 bt->il_vsync = hdmi_read16(sd, 0x30, in adv76xx_query_dv_timings()
1609 info->field1_vsync_mask) / 2; in adv76xx_query_dv_timings()
1610 bt->il_vbackporch = hdmi_read16(sd, 0x34, in adv76xx_query_dv_timings()
1611 info->field1_vbackporch_mask) / 2; in adv76xx_query_dv_timings()
1613 adv76xx_fill_optional_dv_timings_fields(sd, timings); in adv76xx_query_dv_timings()
1616 * Since LCVS values are inaccurate [REF_03, p. 275-276], in adv76xx_query_dv_timings()
1617 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails. in adv76xx_query_dv_timings()
1619 if (!stdi2dv_timings(sd, &stdi, timings)) in adv76xx_query_dv_timings()
1621 stdi.lcvs += 1; in adv76xx_query_dv_timings()
1622 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs); in adv76xx_query_dv_timings()
1623 if (!stdi2dv_timings(sd, &stdi, timings)) in adv76xx_query_dv_timings()
1625 stdi.lcvs -= 2; in adv76xx_query_dv_timings()
1626 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs); in adv76xx_query_dv_timings()
1627 if (stdi2dv_timings(sd, &stdi, timings)) { in adv76xx_query_dv_timings()
1637 if (state->restart_stdi_once) { in adv76xx_query_dv_timings()
1638 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__); in adv76xx_query_dv_timings()
1640 /* enter one-shot mode */ in adv76xx_query_dv_timings()
1641 cp_write_clr_set(sd, 0x86, 0x06, 0x00); in adv76xx_query_dv_timings()
1643 cp_write_clr_set(sd, 0x86, 0x06, 0x04); in adv76xx_query_dv_timings()
1645 cp_write_clr_set(sd, 0x86, 0x06, 0x02); in adv76xx_query_dv_timings()
1646 state->restart_stdi_once = false; in adv76xx_query_dv_timings()
1647 return -ENOLINK; in adv76xx_query_dv_timings()
1649 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__); in adv76xx_query_dv_timings()
1650 return -ERANGE; in adv76xx_query_dv_timings()
1652 state->restart_stdi_once = true; in adv76xx_query_dv_timings()
1656 if (no_signal(sd)) { in adv76xx_query_dv_timings()
1657 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__); in adv76xx_query_dv_timings()
1659 return -ENOLINK; in adv76xx_query_dv_timings()
1662 if ((is_analog_input(sd) && bt->pixelclock > 170000000) || in adv76xx_query_dv_timings()
1663 (is_digital_input(sd) && bt->pixelclock > 225000000)) { in adv76xx_query_dv_timings()
1664 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n", in adv76xx_query_dv_timings()
1665 __func__, (u32)bt->pixelclock); in adv76xx_query_dv_timings()
1666 return -ERANGE; in adv76xx_query_dv_timings()
1669 if (debug > 1) in adv76xx_query_dv_timings()
1670 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ", in adv76xx_query_dv_timings()
1676 static int adv76xx_s_dv_timings(struct v4l2_subdev *sd, in adv76xx_s_dv_timings() argument
1679 struct adv76xx_state *state = to_state(sd); in adv76xx_s_dv_timings()
1684 return -EINVAL; in adv76xx_s_dv_timings()
1686 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) { in adv76xx_s_dv_timings()
1687 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__); in adv76xx_s_dv_timings()
1691 bt = &timings->bt; in adv76xx_s_dv_timings()
1693 if (!v4l2_valid_dv_timings(timings, adv76xx_get_dv_timings_cap(sd, -1), in adv76xx_s_dv_timings()
1695 return -ERANGE; in adv76xx_s_dv_timings()
1697 adv76xx_fill_optional_dv_timings_fields(sd, timings); in adv76xx_s_dv_timings()
1699 state->timings = *timings; in adv76xx_s_dv_timings()
1701 cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00); in adv76xx_s_dv_timings()
1704 err = configure_predefined_video_timings(sd, timings); in adv76xx_s_dv_timings()
1708 configure_custom_video_timings(sd, bt); in adv76xx_s_dv_timings()
1711 set_rgb_quantization_range(sd); in adv76xx_s_dv_timings()
1713 if (debug > 1) in adv76xx_s_dv_timings()
1714 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ", in adv76xx_s_dv_timings()
1719 static int adv76xx_g_dv_timings(struct v4l2_subdev *sd, in adv76xx_g_dv_timings() argument
1722 struct adv76xx_state *state = to_state(sd); in adv76xx_g_dv_timings()
1724 *timings = state->timings; in adv76xx_g_dv_timings()
1728 static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable) in adv7604_set_termination() argument
1730 hdmi_write(sd, 0x01, enable ? 0x00 : 0x78); in adv7604_set_termination()
1733 static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable) in adv7611_set_termination() argument
1735 hdmi_write(sd, 0x83, enable ? 0xfe : 0xff); in adv7611_set_termination()
1738 static void enable_input(struct v4l2_subdev *sd) in enable_input() argument
1740 struct adv76xx_state *state = to_state(sd); in enable_input()
1742 if (is_analog_input(sd)) { in enable_input()
1743 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */ in enable_input()
1744 } else if (is_digital_input(sd)) { in enable_input()
1745 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input); in enable_input()
1746 state->info->set_termination(sd, true); in enable_input()
1747 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */ in enable_input()
1748 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */ in enable_input()
1750 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", in enable_input()
1751 __func__, state->selected_input); in enable_input()
1755 static void disable_input(struct v4l2_subdev *sd) in disable_input() argument
1757 struct adv76xx_state *state = to_state(sd); in disable_input()
1759 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */ in disable_input()
1761 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */ in disable_input()
1762 state->info->set_termination(sd, false); in disable_input()
1765 static void select_input(struct v4l2_subdev *sd) in select_input() argument
1767 struct adv76xx_state *state = to_state(sd); in select_input()
1768 const struct adv76xx_chip_info *info = state->info; in select_input()
1770 if (is_analog_input(sd)) { in select_input()
1771 adv76xx_write_reg_seq(sd, info->recommended_settings[0]); in select_input()
1773 afe_write(sd, 0x00, 0x08); /* power up ADC */ in select_input()
1774 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */ in select_input()
1775 afe_write(sd, 0xc8, 0x00); /* phase control */ in select_input()
1776 } else if (is_digital_input(sd)) { in select_input()
1777 hdmi_write(sd, 0x00, state->selected_input & 0x03); in select_input()
1779 adv76xx_write_reg_seq(sd, info->recommended_settings[1]); in select_input()
1782 afe_write(sd, 0x00, 0xff); /* power down ADC */ in select_input()
1783 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */ in select_input()
1784 afe_write(sd, 0xc8, 0x40); /* phase control */ in select_input()
1787 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */ in select_input()
1788 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */ in select_input()
1789 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */ in select_input()
1791 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n", in select_input()
1792 __func__, state->selected_input); in select_input()
1796 static int adv76xx_s_routing(struct v4l2_subdev *sd, in adv76xx_s_routing() argument
1799 struct adv76xx_state *state = to_state(sd); in adv76xx_s_routing()
1801 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d", in adv76xx_s_routing()
1802 __func__, input, state->selected_input); in adv76xx_s_routing()
1804 if (input == state->selected_input) in adv76xx_s_routing()
1807 if (input > state->info->max_port) in adv76xx_s_routing()
1808 return -EINVAL; in adv76xx_s_routing()
1810 state->selected_input = input; in adv76xx_s_routing()
1812 disable_input(sd); in adv76xx_s_routing()
1813 select_input(sd); in adv76xx_s_routing()
1814 enable_input(sd); in adv76xx_s_routing()
1816 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt); in adv76xx_s_routing()
1821 static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd, in adv76xx_enum_mbus_code() argument
1825 struct adv76xx_state *state = to_state(sd); in adv76xx_enum_mbus_code()
1827 if (code->index >= state->info->nformats) in adv76xx_enum_mbus_code()
1828 return -EINVAL; in adv76xx_enum_mbus_code()
1830 code->code = state->info->formats[code->index].code; in adv76xx_enum_mbus_code()
1840 format->width = state->timings.bt.width; in adv76xx_fill_format()
1841 format->height = state->timings.bt.height; in adv76xx_fill_format()
1842 format->field = V4L2_FIELD_NONE; in adv76xx_fill_format()
1843 format->colorspace = V4L2_COLORSPACE_SRGB; in adv76xx_fill_format()
1845 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) in adv76xx_fill_format()
1846 format->colorspace = (state->timings.bt.height <= 576) ? in adv76xx_fill_format()
1859 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
1860 * ----------+-------------------------------------------------
1862 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
1863 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
1864 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
1877 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG), in adv76xx_op_ch_sel()
1878 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB), in adv76xx_op_ch_sel()
1879 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR), in adv76xx_op_ch_sel()
1884 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5]; in adv76xx_op_ch_sel()
1889 struct v4l2_subdev *sd = &state->sd; in adv76xx_setup_format() local
1891 io_write_clr_set(sd, 0x02, 0x02, in adv76xx_setup_format()
1892 state->format->rgb_out ? ADV76XX_RGB_OUT : 0); in adv76xx_setup_format()
1893 io_write(sd, 0x03, state->format->op_format_sel | in adv76xx_setup_format()
1894 state->pdata.op_format_mode_sel); in adv76xx_setup_format()
1895 io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state)); in adv76xx_setup_format()
1896 io_write_clr_set(sd, 0x05, 0x01, in adv76xx_setup_format()
1897 state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0); in adv76xx_setup_format()
1898 set_rgb_quantization_range(sd); in adv76xx_setup_format()
1901 static int adv76xx_get_format(struct v4l2_subdev *sd, in adv76xx_get_format() argument
1905 struct adv76xx_state *state = to_state(sd); in adv76xx_get_format()
1907 if (format->pad != state->source_pad) in adv76xx_get_format()
1908 return -EINVAL; in adv76xx_get_format()
1910 adv76xx_fill_format(state, &format->format); in adv76xx_get_format()
1912 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { in adv76xx_get_format()
1915 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); in adv76xx_get_format()
1916 format->format.code = fmt->code; in adv76xx_get_format()
1918 format->format.code = state->format->code; in adv76xx_get_format()
1924 static int adv76xx_get_selection(struct v4l2_subdev *sd, in adv76xx_get_selection() argument
1928 struct adv76xx_state *state = to_state(sd); in adv76xx_get_selection()
1930 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) in adv76xx_get_selection()
1931 return -EINVAL; in adv76xx_get_selection()
1933 if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS) in adv76xx_get_selection()
1934 return -EINVAL; in adv76xx_get_selection()
1936 sel->r.left = 0; in adv76xx_get_selection()
1937 sel->r.top = 0; in adv76xx_get_selection()
1938 sel->r.width = state->timings.bt.width; in adv76xx_get_selection()
1939 sel->r.height = state->timings.bt.height; in adv76xx_get_selection()
1944 static int adv76xx_set_format(struct v4l2_subdev *sd, in adv76xx_set_format() argument
1948 struct adv76xx_state *state = to_state(sd); in adv76xx_set_format()
1951 if (format->pad != state->source_pad) in adv76xx_set_format()
1952 return -EINVAL; in adv76xx_set_format()
1954 info = adv76xx_format_info(state, format->format.code); in adv76xx_set_format()
1958 adv76xx_fill_format(state, &format->format); in adv76xx_set_format()
1959 format->format.code = info->code; in adv76xx_set_format()
1961 if (format->which == V4L2_SUBDEV_FORMAT_TRY) { in adv76xx_set_format()
1964 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad); in adv76xx_set_format()
1965 fmt->code = format->format.code; in adv76xx_set_format()
1967 state->format = info; in adv76xx_set_format()
1975 static void adv76xx_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status) in adv76xx_cec_tx_raw_status() argument
1977 struct adv76xx_state *state = to_state(sd); in adv76xx_cec_tx_raw_status()
1979 if ((cec_read(sd, 0x11) & 0x01) == 0) { in adv76xx_cec_tx_raw_status()
1980 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__); in adv76xx_cec_tx_raw_status()
1985 v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n", in adv76xx_cec_tx_raw_status()
1987 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST, in adv76xx_cec_tx_raw_status()
1988 1, 0, 0, 0); in adv76xx_cec_tx_raw_status()
1996 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__); in adv76xx_cec_tx_raw_status()
2002 nack_cnt = cec_read(sd, 0x14) & 0xf; in adv76xx_cec_tx_raw_status()
2005 low_drive_cnt = cec_read(sd, 0x14) >> 4; in adv76xx_cec_tx_raw_status()
2008 cec_transmit_done(state->cec_adap, status, in adv76xx_cec_tx_raw_status()
2013 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__); in adv76xx_cec_tx_raw_status()
2014 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0); in adv76xx_cec_tx_raw_status()
2019 static void adv76xx_cec_isr(struct v4l2_subdev *sd, bool *handled) in adv76xx_cec_isr() argument
2021 struct adv76xx_state *state = to_state(sd); in adv76xx_cec_isr()
2022 const struct adv76xx_chip_info *info = state->info; in adv76xx_cec_isr()
2026 cec_irq = io_read(sd, info->cec_irq_status) & 0x0f; in adv76xx_cec_isr()
2030 v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq); in adv76xx_cec_isr()
2031 adv76xx_cec_tx_raw_status(sd, cec_irq); in adv76xx_cec_isr()
2035 msg.len = cec_read(sd, 0x25) & 0x1f; in adv76xx_cec_isr()
2043 msg.msg[i] = cec_read(sd, i + 0x15); in adv76xx_cec_isr()
2044 cec_write(sd, info->cec_rx_enable, in adv76xx_cec_isr()
2045 info->cec_rx_enable_mask); /* re-enable rx */ in adv76xx_cec_isr()
2046 cec_received_msg(state->cec_adap, &msg); in adv76xx_cec_isr()
2050 if (info->cec_irq_swap) { in adv76xx_cec_isr()
2055 cec_irq = ((cec_irq & 0x08) >> 3) | ((cec_irq & 0x04) >> 1) | in adv76xx_cec_isr()
2056 ((cec_irq & 0x02) << 1) | ((cec_irq & 0x01) << 3); in adv76xx_cec_isr()
2058 io_write(sd, info->cec_irq_status + 1, cec_irq); in adv76xx_cec_isr()
2067 const struct adv76xx_chip_info *info = state->info; in adv76xx_cec_adap_enable()
2068 struct v4l2_subdev *sd = &state->sd; in adv76xx_cec_adap_enable() local
2070 if (!state->cec_enabled_adap && enable) { in adv76xx_cec_adap_enable()
2071 cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */ in adv76xx_cec_adap_enable()
2072 cec_write(sd, 0x2c, 0x01); /* cec soft reset */ in adv76xx_cec_adap_enable()
2073 cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */ in adv76xx_cec_adap_enable()
2079 io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x0f); in adv76xx_cec_adap_enable()
2080 cec_write(sd, info->cec_rx_enable, info->cec_rx_enable_mask); in adv76xx_cec_adap_enable()
2081 } else if (state->cec_enabled_adap && !enable) { in adv76xx_cec_adap_enable()
2083 io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x00); in adv76xx_cec_adap_enable()
2084 /* disable address mask 1-3 */ in adv76xx_cec_adap_enable()
2085 cec_write_clr_set(sd, 0x27, 0x70, 0x00); in adv76xx_cec_adap_enable()
2087 cec_write_clr_set(sd, 0x2a, 0x01, 0x00); in adv76xx_cec_adap_enable()
2088 state->cec_valid_addrs = 0; in adv76xx_cec_adap_enable()
2090 state->cec_enabled_adap = enable; in adv76xx_cec_adap_enable()
2091 adv76xx_s_detect_tx_5v_ctrl(sd); in adv76xx_cec_adap_enable()
2098 struct v4l2_subdev *sd = &state->sd; in adv76xx_cec_adap_log_addr() local
2101 if (!state->cec_enabled_adap) in adv76xx_cec_adap_log_addr()
2102 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO; in adv76xx_cec_adap_log_addr()
2105 cec_write_clr_set(sd, 0x27, 0x70, 0); in adv76xx_cec_adap_log_addr()
2106 state->cec_valid_addrs = 0; in adv76xx_cec_adap_log_addr()
2111 bool is_valid = state->cec_valid_addrs & (1 << i); in adv76xx_cec_adap_log_addr()
2115 if (is_valid && state->cec_addr[i] == addr) in adv76xx_cec_adap_log_addr()
2121 return -ENXIO; in adv76xx_cec_adap_log_addr()
2123 state->cec_addr[i] = addr; in adv76xx_cec_adap_log_addr()
2124 state->cec_valid_addrs |= 1 << i; in adv76xx_cec_adap_log_addr()
2129 cec_write_clr_set(sd, 0x27, 0x10, 0x10); in adv76xx_cec_adap_log_addr()
2131 cec_write_clr_set(sd, 0x28, 0x0f, addr); in adv76xx_cec_adap_log_addr()
2133 case 1: in adv76xx_cec_adap_log_addr()
2134 /* enable address mask 1 */ in adv76xx_cec_adap_log_addr()
2135 cec_write_clr_set(sd, 0x27, 0x20, 0x20); in adv76xx_cec_adap_log_addr()
2136 /* set address for mask 1 */ in adv76xx_cec_adap_log_addr()
2137 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4); in adv76xx_cec_adap_log_addr()
2141 cec_write_clr_set(sd, 0x27, 0x40, 0x40); in adv76xx_cec_adap_log_addr()
2142 /* set address for mask 1 */ in adv76xx_cec_adap_log_addr()
2143 cec_write_clr_set(sd, 0x29, 0x0f, addr); in adv76xx_cec_adap_log_addr()
2153 struct v4l2_subdev *sd = &state->sd; in adv76xx_cec_adap_transmit() local
2154 u8 len = msg->len; in adv76xx_cec_adap_transmit()
2158 * The number of retries is the number of attempts - 1, but retry in adv76xx_cec_adap_transmit()
2162 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4); in adv76xx_cec_adap_transmit()
2165 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len); in adv76xx_cec_adap_transmit()
2166 return -EINVAL; in adv76xx_cec_adap_transmit()
2171 cec_write(sd, i, msg->msg[i]); in adv76xx_cec_adap_transmit()
2174 cec_write(sd, 0x10, len); in adv76xx_cec_adap_transmit()
2176 cec_write(sd, 0x11, 0x01); in adv76xx_cec_adap_transmit()
2187 static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled) in adv76xx_isr() argument
2189 struct adv76xx_state *state = to_state(sd); in adv76xx_isr()
2190 const struct adv76xx_chip_info *info = state->info; in adv76xx_isr()
2191 const u8 irq_reg_0x43 = io_read(sd, 0x43); in adv76xx_isr()
2192 const u8 irq_reg_0x6b = io_read(sd, 0x6b); in adv76xx_isr()
2193 const u8 irq_reg_0x70 = io_read(sd, 0x70); in adv76xx_isr()
2199 io_write(sd, 0x44, irq_reg_0x43); in adv76xx_isr()
2201 io_write(sd, 0x71, irq_reg_0x70); in adv76xx_isr()
2203 io_write(sd, 0x6c, irq_reg_0x6b); in adv76xx_isr()
2205 v4l2_dbg(2, debug, sd, "%s: ", __func__); in adv76xx_isr()
2209 fmt_change_digital = is_digital_input(sd) in adv76xx_isr()
2210 ? irq_reg_0x6b & info->fmt_change_digital_mask in adv76xx_isr()
2214 v4l2_dbg(1, debug, sd, in adv76xx_isr()
2218 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt); in adv76xx_isr()
2225 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__, in adv76xx_isr()
2226 (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI"); in adv76xx_isr()
2227 set_rgb_quantization_range(sd); in adv76xx_isr()
2234 adv76xx_cec_isr(sd, handled); in adv76xx_isr()
2238 tx_5v = irq_reg_0x70 & info->cable_det_mask; in adv76xx_isr()
2240 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v); in adv76xx_isr()
2241 adv76xx_s_detect_tx_5v_ctrl(sd); in adv76xx_isr()
2253 adv76xx_isr(&state->sd, 0, &handled); in adv76xx_irq_handler()
2258 static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) in adv76xx_get_edid() argument
2260 struct adv76xx_state *state = to_state(sd); in adv76xx_get_edid()
2263 memset(edid->reserved, 0, sizeof(edid->reserved)); in adv76xx_get_edid()
2265 switch (edid->pad) { in adv76xx_get_edid()
2270 if (state->edid.present & (1 << edid->pad)) in adv76xx_get_edid()
2271 data = state->edid.edid; in adv76xx_get_edid()
2274 return -EINVAL; in adv76xx_get_edid()
2277 if (edid->start_block == 0 && edid->blocks == 0) { in adv76xx_get_edid()
2278 edid->blocks = data ? state->edid.blocks : 0; in adv76xx_get_edid()
2283 return -ENODATA; in adv76xx_get_edid()
2285 if (edid->start_block >= state->edid.blocks) in adv76xx_get_edid()
2286 return -EINVAL; in adv76xx_get_edid()
2288 if (edid->start_block + edid->blocks > state->edid.blocks) in adv76xx_get_edid()
2289 edid->blocks = state->edid.blocks - edid->start_block; in adv76xx_get_edid()
2291 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128); in adv76xx_get_edid()
2296 static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid) in adv76xx_set_edid() argument
2298 struct adv76xx_state *state = to_state(sd); in adv76xx_set_edid()
2299 const struct adv76xx_chip_info *info = state->info; in adv76xx_set_edid()
2305 memset(edid->reserved, 0, sizeof(edid->reserved)); in adv76xx_set_edid()
2307 if (edid->pad > ADV7604_PAD_HDMI_PORT_D) in adv76xx_set_edid()
2308 return -EINVAL; in adv76xx_set_edid()
2309 if (edid->start_block != 0) in adv76xx_set_edid()
2310 return -EINVAL; in adv76xx_set_edid()
2311 if (edid->blocks == 0) { in adv76xx_set_edid()
2313 state->edid.present &= ~(1 << edid->pad); in adv76xx_set_edid()
2314 adv76xx_set_hpd(state, state->edid.present); in adv76xx_set_edid()
2315 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); in adv76xx_set_edid()
2318 state->aspect_ratio.numerator = 16; in adv76xx_set_edid()
2319 state->aspect_ratio.denominator = 9; in adv76xx_set_edid()
2321 if (!state->edid.present) { in adv76xx_set_edid()
2322 state->edid.blocks = 0; in adv76xx_set_edid()
2323 cec_phys_addr_invalidate(state->cec_adap); in adv76xx_set_edid()
2326 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n", in adv76xx_set_edid()
2327 __func__, edid->pad, state->edid.present); in adv76xx_set_edid()
2330 if (edid->blocks > 2) { in adv76xx_set_edid()
2331 edid->blocks = 2; in adv76xx_set_edid()
2332 return -E2BIG; in adv76xx_set_edid()
2334 pa = v4l2_get_edid_phys_addr(edid->edid, edid->blocks * 128, &spa_loc); in adv76xx_set_edid()
2339 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n", in adv76xx_set_edid()
2340 __func__, edid->pad, state->edid.present); in adv76xx_set_edid()
2343 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug); in adv76xx_set_edid()
2345 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00); in adv76xx_set_edid()
2352 return -EINVAL; in adv76xx_set_edid()
2354 switch (edid->pad) { in adv76xx_set_edid()
2356 state->spa_port_a[0] = edid->edid[spa_loc]; in adv76xx_set_edid()
2357 state->spa_port_a[1] = edid->edid[spa_loc + 1]; in adv76xx_set_edid()
2360 rep_write(sd, 0x70, edid->edid[spa_loc]); in adv76xx_set_edid()
2361 rep_write(sd, 0x71, edid->edid[spa_loc + 1]); in adv76xx_set_edid()
2364 rep_write(sd, 0x72, edid->edid[spa_loc]); in adv76xx_set_edid()
2365 rep_write(sd, 0x73, edid->edid[spa_loc + 1]); in adv76xx_set_edid()
2368 rep_write(sd, 0x74, edid->edid[spa_loc]); in adv76xx_set_edid()
2369 rep_write(sd, 0x75, edid->edid[spa_loc + 1]); in adv76xx_set_edid()
2372 return -EINVAL; in adv76xx_set_edid()
2375 if (info->type == ADV7604) { in adv76xx_set_edid()
2376 rep_write(sd, 0x76, spa_loc & 0xff); in adv76xx_set_edid()
2377 rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2); in adv76xx_set_edid()
2380 rep_write(sd, 0x70, spa_loc & 0xff); in adv76xx_set_edid()
2381 rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8); in adv76xx_set_edid()
2384 edid->edid[spa_loc] = state->spa_port_a[0]; in adv76xx_set_edid()
2385 edid->edid[spa_loc + 1] = state->spa_port_a[1]; in adv76xx_set_edid()
2387 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks); in adv76xx_set_edid()
2388 state->edid.blocks = edid->blocks; in adv76xx_set_edid()
2389 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15], in adv76xx_set_edid()
2390 edid->edid[0x16]); in adv76xx_set_edid()
2391 state->edid.present |= 1 << edid->pad; in adv76xx_set_edid()
2393 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid); in adv76xx_set_edid()
2395 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad); in adv76xx_set_edid()
2401 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present); in adv76xx_set_edid()
2404 if (rep_read(sd, info->edid_status_reg) & state->edid.present) in adv76xx_set_edid()
2406 mdelay(1); in adv76xx_set_edid()
2409 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present); in adv76xx_set_edid()
2410 return -EIO; in adv76xx_set_edid()
2412 cec_s_phys_addr(state->cec_adap, pa, false); in adv76xx_set_edid()
2415 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10); in adv76xx_set_edid()
2419 /*********** avi info frame CEA-861-E **************/
2428 static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index, in adv76xx_read_infoframe() argument
2435 if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) { in adv76xx_read_infoframe()
2436 v4l2_info(sd, "%s infoframe not received\n", in adv76xx_read_infoframe()
2438 return -ENOENT; in adv76xx_read_infoframe()
2442 buffer[i] = infoframe_read(sd, in adv76xx_read_infoframe()
2445 len = buffer[2] + 1; in adv76xx_read_infoframe()
2448 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, in adv76xx_read_infoframe()
2450 return -ENOENT; in adv76xx_read_infoframe()
2454 buffer[i + 3] = infoframe_read(sd, in adv76xx_read_infoframe()
2458 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, in adv76xx_read_infoframe()
2460 return -ENOENT; in adv76xx_read_infoframe()
2465 static void adv76xx_log_infoframes(struct v4l2_subdev *sd) in adv76xx_log_infoframes() argument
2469 if (!is_hdmi(sd)) { in adv76xx_log_infoframes()
2470 v4l2_info(sd, "receive DVI-D signal, no infoframes\n"); in adv76xx_log_infoframes()
2476 struct i2c_client *client = v4l2_get_subdevdata(sd); in adv76xx_log_infoframes()
2478 if (adv76xx_read_infoframe(sd, i, &frame)) in adv76xx_log_infoframes()
2480 hdmi_infoframe_log(KERN_INFO, &client->dev, &frame); in adv76xx_log_infoframes()
2484 static int adv76xx_log_status(struct v4l2_subdev *sd) in adv76xx_log_status() argument
2486 struct adv76xx_state *state = to_state(sd); in adv76xx_log_status()
2487 const struct adv76xx_chip_info *info = state->info; in adv76xx_log_status()
2490 u8 reg_io_0x02 = io_read(sd, 0x02); in adv76xx_log_status()
2495 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB", in adv76xx_log_status()
2496 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709", in adv76xx_log_status()
2497 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709", in adv76xx_log_status()
2501 "RGB limited range (16-235)", "RGB full range (0-255)", in adv76xx_log_status()
2502 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", in adv76xx_log_status()
2504 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", in adv76xx_log_status()
2509 "RGB limited range (16-235)", "RGB full range (0-255)", in adv76xx_log_status()
2510 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)", in adv76xx_log_status()
2512 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)", in adv76xx_log_status()
2518 "RGB limited range (16-235)", in adv76xx_log_status()
2519 "RGB full range (0-255)", in adv76xx_log_status()
2522 "8-bits per channel", in adv76xx_log_status()
2523 "10-bits per channel", in adv76xx_log_status()
2524 "12-bits per channel", in adv76xx_log_status()
2525 "16-bits per channel (not supported)" in adv76xx_log_status()
2528 v4l2_info(sd, "-----Chip status-----\n"); in adv76xx_log_status()
2529 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on"); in adv76xx_log_status()
2530 edid_enabled = rep_read(sd, info->edid_status_reg); in adv76xx_log_status()
2531 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n", in adv76xx_log_status()
2536 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ? in adv76xx_log_status()
2538 if (state->cec_enabled_adap) { in adv76xx_log_status()
2542 bool is_valid = state->cec_valid_addrs & (1 << i); in adv76xx_log_status()
2545 v4l2_info(sd, "CEC Logical Address: 0x%x\n", in adv76xx_log_status()
2546 state->cec_addr[i]); in adv76xx_log_status()
2550 v4l2_info(sd, "-----Signal status-----\n"); in adv76xx_log_status()
2551 cable_det = info->read_cable_det(sd); in adv76xx_log_status()
2552 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n", in adv76xx_log_status()
2557 v4l2_info(sd, "TMDS signal detected: %s\n", in adv76xx_log_status()
2558 no_signal_tmds(sd) ? "false" : "true"); in adv76xx_log_status()
2559 v4l2_info(sd, "TMDS signal locked: %s\n", in adv76xx_log_status()
2560 no_lock_tmds(sd) ? "false" : "true"); in adv76xx_log_status()
2561 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true"); in adv76xx_log_status()
2562 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true"); in adv76xx_log_status()
2563 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true"); in adv76xx_log_status()
2564 v4l2_info(sd, "CP free run: %s\n", in adv76xx_log_status()
2565 (in_free_run(sd)) ? "on" : "off"); in adv76xx_log_status()
2566 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n", in adv76xx_log_status()
2567 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f, in adv76xx_log_status()
2568 (io_read(sd, 0x01) & 0x70) >> 4); in adv76xx_log_status()
2570 v4l2_info(sd, "-----Video Timings-----\n"); in adv76xx_log_status()
2571 if (read_stdi(sd, &stdi)) in adv76xx_log_status()
2572 v4l2_info(sd, "STDI: not locked\n"); in adv76xx_log_status()
2574 …v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync… in adv76xx_log_status()
2578 if (adv76xx_query_dv_timings(sd, &timings)) in adv76xx_log_status()
2579 v4l2_info(sd, "No video detected\n"); in adv76xx_log_status()
2581 v4l2_print_dv_timings(sd->name, "Detected format: ", in adv76xx_log_status()
2583 v4l2_print_dv_timings(sd->name, "Configured format: ", in adv76xx_log_status()
2584 &state->timings, true); in adv76xx_log_status()
2586 if (no_signal(sd)) in adv76xx_log_status()
2589 v4l2_info(sd, "-----Color space-----\n"); in adv76xx_log_status()
2590 v4l2_info(sd, "RGB quantization range ctrl: %s\n", in adv76xx_log_status()
2591 rgb_quantization_range_txt[state->rgb_quantization_range]); in adv76xx_log_status()
2592 v4l2_info(sd, "Input color space: %s\n", in adv76xx_log_status()
2594 v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n", in adv76xx_log_status()
2597 "(16-235)" : "(0-255)", in adv76xx_log_status()
2599 v4l2_info(sd, "Color space conversion: %s\n", in adv76xx_log_status()
2600 csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]); in adv76xx_log_status()
2602 if (!is_digital_input(sd)) in adv76xx_log_status()
2605 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D"); in adv76xx_log_status()
2606 v4l2_info(sd, "Digital video port selected: %c\n", in adv76xx_log_status()
2607 (hdmi_read(sd, 0x00) & 0x03) + 'A'); in adv76xx_log_status()
2608 v4l2_info(sd, "HDCP encrypted content: %s\n", in adv76xx_log_status()
2609 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false"); in adv76xx_log_status()
2610 v4l2_info(sd, "HDCP keys read: %s%s\n", in adv76xx_log_status()
2611 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no", in adv76xx_log_status()
2612 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : ""); in adv76xx_log_status()
2613 if (is_hdmi(sd)) { in adv76xx_log_status()
2614 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01; in adv76xx_log_status()
2615 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01; in adv76xx_log_status()
2616 bool audio_mute = io_read(sd, 0x65) & 0x40; in adv76xx_log_status()
2618 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n", in adv76xx_log_status()
2623 v4l2_info(sd, "Audio format: %s\n", in adv76xx_log_status()
2624 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo"); in adv76xx_log_status()
2626 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) + in adv76xx_log_status()
2627 (hdmi_read(sd, 0x5c) << 8) + in adv76xx_log_status()
2628 (hdmi_read(sd, 0x5d) & 0xf0)); in adv76xx_log_status()
2629 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) + in adv76xx_log_status()
2630 (hdmi_read(sd, 0x5e) << 8) + in adv76xx_log_status()
2631 hdmi_read(sd, 0x5f)); in adv76xx_log_status()
2632 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off"); in adv76xx_log_status()
2634 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]); in adv76xx_log_status()
2635 v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]); in adv76xx_log_status()
2637 adv76xx_log_infoframes(sd); in adv76xx_log_status()
2643 static int adv76xx_subscribe_event(struct v4l2_subdev *sd, in adv76xx_subscribe_event() argument
2647 switch (sub->type) { in adv76xx_subscribe_event()
2649 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub); in adv76xx_subscribe_event()
2651 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub); in adv76xx_subscribe_event()
2653 return -EINVAL; in adv76xx_subscribe_event()
2657 static int adv76xx_registered(struct v4l2_subdev *sd) in adv76xx_registered() argument
2659 struct adv76xx_state *state = to_state(sd); in adv76xx_registered()
2660 struct i2c_client *client = v4l2_get_subdevdata(sd); in adv76xx_registered()
2663 err = cec_register_adapter(state->cec_adap, &client->dev); in adv76xx_registered()
2665 cec_delete_adapter(state->cec_adap); in adv76xx_registered()
2669 static void adv76xx_unregistered(struct v4l2_subdev *sd) in adv76xx_unregistered() argument
2671 struct adv76xx_state *state = to_state(sd); in adv76xx_unregistered()
2673 cec_unregister_adapter(state->cec_adap); in adv76xx_unregistered()
2676 /* ----------------------------------------------------------------------- */
2724 /* -------------------------- custom ctrls ---------------------------------- */
2733 .step = 1,
2744 .step = 1,
2759 /* ----------------------------------------------------------------------- */
2782 static int adv76xx_core_init(struct v4l2_subdev *sd) in adv76xx_core_init() argument
2784 struct adv76xx_state *state = to_state(sd); in adv76xx_core_init()
2785 const struct adv76xx_chip_info *info = state->info; in adv76xx_core_init()
2786 struct adv76xx_platform_data *pdata = &state->pdata; in adv76xx_core_init()
2788 hdmi_write(sd, 0x48, in adv76xx_core_init()
2789 (pdata->disable_pwrdnb ? 0x80 : 0) | in adv76xx_core_init()
2790 (pdata->disable_cable_det_rst ? 0x40 : 0)); in adv76xx_core_init()
2792 disable_input(sd); in adv76xx_core_init()
2794 if (pdata->default_input >= 0 && in adv76xx_core_init()
2795 pdata->default_input < state->source_pad) { in adv76xx_core_init()
2796 state->selected_input = pdata->default_input; in adv76xx_core_init()
2797 select_input(sd); in adv76xx_core_init()
2798 enable_input(sd); in adv76xx_core_init()
2802 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */ in adv76xx_core_init()
2803 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */ in adv76xx_core_init()
2804 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */ in adv76xx_core_init()
2807 io_write_clr_set(sd, 0x02, 0x0f, pdata->alt_gamma << 3); in adv76xx_core_init()
2808 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 | in adv76xx_core_init()
2809 pdata->insert_av_codes << 2 | in adv76xx_core_init()
2810 pdata->replicate_av_codes << 1); in adv76xx_core_init()
2813 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */ in adv76xx_core_init()
2816 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 | in adv76xx_core_init()
2817 pdata->inv_hs_pol << 1 | pdata->inv_llc_pol); in adv76xx_core_init()
2820 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 | in adv76xx_core_init()
2821 pdata->dr_str_clk << 2 | in adv76xx_core_init()
2822 pdata->dr_str_sync); in adv76xx_core_init()
2824 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */ in adv76xx_core_init()
2825 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */ in adv76xx_core_init()
2826 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold - in adv76xx_core_init()
2828 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold - in adv76xx_core_init()
2830 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution in adv76xx_core_init()
2834 hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */ in adv76xx_core_init()
2835 hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */ in adv76xx_core_init()
2836 hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */ in adv76xx_core_init()
2839 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */ in adv76xx_core_init()
2842 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */ in adv76xx_core_init()
2843 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4); in adv76xx_core_init()
2847 io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */ in adv76xx_core_init()
2848 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */ in adv76xx_core_init()
2849 …io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts … in adv76xx_core_init()
2850 io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */ in adv76xx_core_init()
2851 info->setup_irqs(sd); in adv76xx_core_init()
2853 return v4l2_ctrl_handler_setup(sd->ctrl_handler); in adv76xx_core_init()
2856 static void adv7604_setup_irqs(struct v4l2_subdev *sd) in adv7604_setup_irqs() argument
2858 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */ in adv7604_setup_irqs()
2861 static void adv7611_setup_irqs(struct v4l2_subdev *sd) in adv7611_setup_irqs() argument
2863 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */ in adv7611_setup_irqs()
2866 static void adv7612_setup_irqs(struct v4l2_subdev *sd) in adv7612_setup_irqs() argument
2868 io_write(sd, 0x41, 0xd0); /* disable INT2 */ in adv7612_setup_irqs()
2875 for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) in adv76xx_unregister_clients()
2876 i2c_unregister_device(state->i2c_clients[i]); in adv76xx_unregister_clients()
2879 static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd, in adv76xx_dummy_client() argument
2882 struct i2c_client *client = v4l2_get_subdevdata(sd); in adv76xx_dummy_client()
2883 struct adv76xx_state *state = to_state(sd); in adv76xx_dummy_client()
2884 struct adv76xx_platform_data *pdata = &state->pdata; in adv76xx_dummy_client()
2888 if (pdata && pdata->i2c_addresses[page]) in adv76xx_dummy_client()
2889 new_client = i2c_new_dummy_device(client->adapter, in adv76xx_dummy_client()
2890 pdata->i2c_addresses[page]); in adv76xx_dummy_client()
2897 io_write(sd, io_reg, new_client->addr << 1); in adv76xx_dummy_client()
2907 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2922 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2924 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
2933 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
3007 [1] = adv7604_recommended_settings_hdmi,
3011 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
3037 .num_dv_ports = 1,
3055 [1] = adv7611_recommended_settings_hdmi,
3058 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
3081 .num_dv_ports = 1, /* normally 2 */
3099 [1] = adv7612_recommended_settings_hdmi,
3102 [1] = ARRAY_SIZE(adv7612_recommended_settings_hdmi),
3147 np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node; in adv76xx_parse_dt()
3152 return -EINVAL; in adv76xx_parse_dt()
3159 if (!of_property_read_u32(np, "default-input", &v)) in adv76xx_parse_dt()
3160 state->pdata.default_input = v; in adv76xx_parse_dt()
3162 state->pdata.default_input = -1; in adv76xx_parse_dt()
3167 state->pdata.inv_hs_pol = 1; in adv76xx_parse_dt()
3170 state->pdata.inv_vs_pol = 1; in adv76xx_parse_dt()
3173 state->pdata.inv_llc_pol = 1; in adv76xx_parse_dt()
3176 state->pdata.insert_av_codes = 1; in adv76xx_parse_dt()
3178 /* Disable the interrupt for now as no DT-based board uses it. */ in adv76xx_parse_dt()
3179 state->pdata.int1_config = ADV76XX_INT1_CONFIG_ACTIVE_HIGH; in adv76xx_parse_dt()
3182 state->pdata.disable_pwrdnb = 0; in adv76xx_parse_dt()
3183 state->pdata.disable_cable_det_rst = 0; in adv76xx_parse_dt()
3184 state->pdata.blank_data = 1; in adv76xx_parse_dt()
3185 state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0; in adv76xx_parse_dt()
3186 state->pdata.bus_order = ADV7604_BUS_ORDER_RGB; in adv76xx_parse_dt()
3187 state->pdata.dr_str_data = ADV76XX_DR_STR_MEDIUM_HIGH; in adv76xx_parse_dt()
3188 state->pdata.dr_str_clk = ADV76XX_DR_STR_MEDIUM_HIGH; in adv76xx_parse_dt()
3189 state->pdata.dr_str_sync = ADV76XX_DR_STR_MEDIUM_HIGH; in adv76xx_parse_dt()
3306 if (!state->i2c_clients[region]) in configure_regmap()
3307 return -ENODEV; in configure_regmap()
3309 state->regmap[region] = in configure_regmap()
3310 devm_regmap_init_i2c(state->i2c_clients[region], in configure_regmap()
3313 if (IS_ERR(state->regmap[region])) { in configure_regmap()
3314 err = PTR_ERR(state->regmap[region]); in configure_regmap()
3315 v4l_err(state->i2c_clients[region], in configure_regmap()
3318 return -EINVAL; in configure_regmap()
3330 if (err && (err != -ENODEV)) in configure_regmaps()
3338 if (state->reset_gpio) { in adv76xx_reset()
3340 gpiod_set_value_cansleep(state->reset_gpio, 0); in adv76xx_reset()
3342 gpiod_set_value_cansleep(state->reset_gpio, 1); in adv76xx_reset()
3357 struct v4l2_subdev *sd; in adv76xx_probe() local
3363 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) in adv76xx_probe()
3364 return -EIO; in adv76xx_probe()
3365 v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n", in adv76xx_probe()
3366 client->addr << 1); in adv76xx_probe()
3368 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL); in adv76xx_probe()
3370 return -ENOMEM; in adv76xx_probe()
3372 state->i2c_clients[ADV76XX_PAGE_IO] = client; in adv76xx_probe()
3375 state->restart_stdi_once = true; in adv76xx_probe()
3376 state->selected_input = ~0; in adv76xx_probe()
3378 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) { in adv76xx_probe()
3381 oid = of_match_node(adv76xx_of_id, client->dev.of_node); in adv76xx_probe()
3382 state->info = oid->data; in adv76xx_probe()
3389 } else if (client->dev.platform_data) { in adv76xx_probe()
3390 struct adv76xx_platform_data *pdata = client->dev.platform_data; in adv76xx_probe()
3392 state->info = (const struct adv76xx_chip_info *)id->driver_data; in adv76xx_probe()
3393 state->pdata = *pdata; in adv76xx_probe()
3396 return -ENODEV; in adv76xx_probe()
3400 for (i = 0; i < state->info->num_dv_ports; ++i) { in adv76xx_probe()
3401 state->hpd_gpio[i] = in adv76xx_probe()
3402 devm_gpiod_get_index_optional(&client->dev, "hpd", i, in adv76xx_probe()
3404 if (IS_ERR(state->hpd_gpio[i])) in adv76xx_probe()
3405 return PTR_ERR(state->hpd_gpio[i]); in adv76xx_probe()
3407 if (state->hpd_gpio[i]) in adv76xx_probe()
3410 state->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", in adv76xx_probe()
3412 if (IS_ERR(state->reset_gpio)) in adv76xx_probe()
3413 return PTR_ERR(state->reset_gpio); in adv76xx_probe()
3417 state->timings = cea640x480; in adv76xx_probe()
3418 state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8); in adv76xx_probe()
3420 sd = &state->sd; in adv76xx_probe()
3421 v4l2_i2c_subdev_init(sd, client, &adv76xx_ops); in adv76xx_probe()
3422 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x", in adv76xx_probe()
3423 id->name, i2c_adapter_id(client->adapter), in adv76xx_probe()
3424 client->addr); in adv76xx_probe()
3425 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; in adv76xx_probe()
3426 sd->internal_ops = &adv76xx_int_ops; in adv76xx_probe()
3432 v4l2_err(sd, "Error configuring IO regmap region\n"); in adv76xx_probe()
3433 return -ENODEV; in adv76xx_probe()
3441 switch (state->info->type) { in adv76xx_probe()
3443 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val); in adv76xx_probe()
3445 v4l2_err(sd, "Error %d reading IO Regmap\n", err); in adv76xx_probe()
3446 return -ENODEV; in adv76xx_probe()
3449 v4l2_err(sd, "not an adv7604 on address 0x%x\n", in adv76xx_probe()
3450 client->addr << 1); in adv76xx_probe()
3451 return -ENODEV; in adv76xx_probe()
3456 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], in adv76xx_probe()
3460 v4l2_err(sd, "Error %d reading IO Regmap\n", err); in adv76xx_probe()
3461 return -ENODEV; in adv76xx_probe()
3464 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], in adv76xx_probe()
3468 v4l2_err(sd, "Error %d reading IO Regmap\n", err); in adv76xx_probe()
3469 return -ENODEV; in adv76xx_probe()
3472 if ((state->info->type == ADV7611 && val != 0x2051) || in adv76xx_probe()
3473 (state->info->type == ADV7612 && val != 0x2041)) { in adv76xx_probe()
3474 v4l2_err(sd, "not an adv761x on address 0x%x\n", in adv76xx_probe()
3475 client->addr << 1); in adv76xx_probe()
3476 return -ENODEV; in adv76xx_probe()
3482 hdl = &state->hdl; in adv76xx_probe()
3486 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0); in adv76xx_probe()
3488 V4L2_CID_CONTRAST, 0, 255, 1, 128); in adv76xx_probe()
3490 V4L2_CID_SATURATION, 0, 255, 1, 128); in adv76xx_probe()
3492 V4L2_CID_HUE, 0, 128, 1, 0); in adv76xx_probe()
3497 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; in adv76xx_probe()
3499 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL, in adv76xx_probe()
3501 (1 << state->info->num_dv_ports) - 1, 0, 0); in adv76xx_probe()
3502 state->rgb_quantization_range_ctrl = in adv76xx_probe()
3509 state->analog_sampling_phase_ctrl = in adv76xx_probe()
3511 state->free_run_color_manual_ctrl = in adv76xx_probe()
3513 state->free_run_color_ctrl = in adv76xx_probe()
3516 sd->ctrl_handler = hdl; in adv76xx_probe()
3517 if (hdl->error) { in adv76xx_probe()
3518 err = hdl->error; in adv76xx_probe()
3521 if (adv76xx_s_detect_tx_5v_ctrl(sd)) { in adv76xx_probe()
3522 err = -ENODEV; in adv76xx_probe()
3526 for (i = 1; i < ADV76XX_PAGE_MAX; ++i) { in adv76xx_probe()
3529 if (!(BIT(i) & state->info->page_mask)) in adv76xx_probe()
3532 dummy_client = adv76xx_dummy_client(sd, i); in adv76xx_probe()
3535 v4l2_err(sd, "failed to create i2c client %u\n", i); in adv76xx_probe()
3539 state->i2c_clients[i] = dummy_client; in adv76xx_probe()
3542 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug, in adv76xx_probe()
3545 state->source_pad = state->info->num_dv_ports in adv76xx_probe()
3546 + (state->info->has_afe ? 2 : 0); in adv76xx_probe()
3547 for (i = 0; i < state->source_pad; ++i) in adv76xx_probe()
3548 state->pads[i].flags = MEDIA_PAD_FL_SINK; in adv76xx_probe()
3549 state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE; in adv76xx_probe()
3550 sd->entity.function = MEDIA_ENT_F_DV_DECODER; in adv76xx_probe()
3552 err = media_entity_pads_init(&sd->entity, state->source_pad + 1, in adv76xx_probe()
3553 state->pads); in adv76xx_probe()
3562 err = adv76xx_core_init(sd); in adv76xx_probe()
3566 if (client->irq) { in adv76xx_probe()
3567 err = devm_request_threaded_irq(&client->dev, in adv76xx_probe()
3568 client->irq, in adv76xx_probe()
3571 client->name, state); in adv76xx_probe()
3577 state->cec_adap = cec_allocate_adapter(&adv76xx_cec_adap_ops, in adv76xx_probe()
3578 state, dev_name(&client->dev), in adv76xx_probe()
3580 err = PTR_ERR_OR_ZERO(state->cec_adap); in adv76xx_probe()
3585 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name, in adv76xx_probe()
3586 client->addr << 1, client->adapter->name); in adv76xx_probe()
3588 err = v4l2_async_register_subdev(sd); in adv76xx_probe()
3595 media_entity_cleanup(&sd->entity); in adv76xx_probe()
3597 cancel_delayed_work(&state->delayed_work_enable_hotplug); in adv76xx_probe()
3605 /* ----------------------------------------------------------------------- */
3609 struct v4l2_subdev *sd = i2c_get_clientdata(client); in adv76xx_remove() local
3610 struct adv76xx_state *state = to_state(sd); in adv76xx_remove()
3613 io_write(sd, 0x40, 0); in adv76xx_remove()
3614 io_write(sd, 0x41, 0); in adv76xx_remove()
3615 io_write(sd, 0x46, 0); in adv76xx_remove()
3616 io_write(sd, 0x6e, 0); in adv76xx_remove()
3617 io_write(sd, 0x73, 0); in adv76xx_remove()
3619 cancel_delayed_work(&state->delayed_work_enable_hotplug); in adv76xx_remove()
3620 v4l2_async_unregister_subdev(sd); in adv76xx_remove()
3621 media_entity_cleanup(&sd->entity); in adv76xx_remove()
3622 adv76xx_unregister_clients(to_state(sd)); in adv76xx_remove()
3623 v4l2_ctrl_handler_free(sd->ctrl_handler); in adv76xx_remove()
3627 /* ----------------------------------------------------------------------- */