Lines Matching +full:0 +full:x09
34 #define BER_SRC_S 0x20
35 #define BER_SRC_S2 0x20
144 u8 data[3] = {reg >> 8, reg & 0xff, val}; in write_reg()
145 struct i2c_msg msg = {.addr = state->base->adr, .flags = 0, in write_reg()
153 return 0; in write_reg()
159 u8 msg[2] = {reg >> 8, reg & 0xff}; in i2c_read_regs16()
160 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0, in i2c_read_regs16()
170 return 0; in i2c_read_regs16()
206 mask = field & 0xff; in write_field()
207 shift = (field >> 12) & 0xf; in write_field()
210 return 0; in write_field()
227 { 0, 9242 }, /* C/N= 0dB */
290 { 0, 11520 }, /* C/N= 0dB */
347 { 0, 118000 }, /* PADC= +0dBm */
375 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x2A, 0x1C, 0x3A, 0x3B,
377 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x3A, 0x0C, 0x3A, 0x2B,
379 0x1C, 0x3C, 0x1B, 0x3C, 0x3A, 0x1C, 0x3A, 0x3B, 0x3A, 0x2B,
381 0x0C, 0x1C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,
383 0x1C, 0x1C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,
385 0x2C, 0x2C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,
387 0x3C, 0x2C, 0x3B, 0x2C, 0x1B, 0x1C, 0x1B, 0x3B, 0x3A, 0x1B,
389 0x0D, 0x3C, 0x3B, 0x2C, 0x1B, 0x1C, 0x1B, 0x3B, 0x3A, 0x1B,
391 0x1D, 0x3C, 0x0C, 0x2C, 0x2B, 0x1C, 0x1B, 0x3B, 0x0B, 0x1B,
393 0x3D, 0x0D, 0x0C, 0x2C, 0x2B, 0x0C, 0x2B, 0x2B, 0x0B, 0x0B,
395 0x1E, 0x0D, 0x1C, 0x2C, 0x3B, 0x0C, 0x2B, 0x2B, 0x1B, 0x0B,
397 0x28, 0x09, 0x28, 0x09, 0x28, 0x09, 0x28, 0x08, 0x28, 0x27,
399 0x19, 0x29, 0x19, 0x29, 0x19, 0x29, 0x38, 0x19, 0x28, 0x09,
401 0x1A, 0x0B, 0x1A, 0x3A, 0x0A, 0x2A, 0x39, 0x2A, 0x39, 0x1A,
403 0x2B, 0x2B, 0x1B, 0x1B, 0x0B, 0x1B, 0x1A, 0x0B, 0x1A, 0x1A,
405 0x0C, 0x0C, 0x3B, 0x3B, 0x1B, 0x1B, 0x2A, 0x0B, 0x2A, 0x2A,
407 0x0C, 0x1C, 0x0C, 0x3B, 0x2B, 0x1B, 0x3A, 0x0B, 0x2A, 0x2A,
419 0x0A, 0x0A, 0x0A, 0x0A, 0x1A, 0x0A, 0x39, 0x0A, 0x29, 0x0A,
421 0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x0A, 0x2A, 0x0A, 0x1A, 0x0A,
423 0x0A, 0x0A, 0x0A, 0x0A, 0x1B, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A,
425 0x0A, 0x0A, 0x0A, 0x0A, 0x1B, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A,
427 0x0A, 0x0A, 0x0A, 0x0A, 0x2B, 0x0A, 0x0B, 0x0A, 0x3A, 0x0A,
429 0x0A, 0x0A, 0x0A, 0x0A, 0x2B, 0x0A, 0x0B, 0x0A, 0x3A, 0x0A,
431 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
433 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
435 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
437 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
439 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,
445 int i = 0; in get_optim_cloop()
453 i += 0; in get_optim_cloop()
471 int status = 0; in get_cur_symbol_rate()
482 *p_symbol_rate = 0; in get_cur_symbol_rate()
499 if ((timing_offset & (1 << 23)) != 0) in get_cur_symbol_rate()
500 timing_offset |= 0xFF000000; /* Sign extent */ in get_cur_symbol_rate()
507 return 0; in get_cur_symbol_rate()
519 state->mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2); in get_signal_parameters()
520 state->pilots = (tmp & 0x01) != 0; in get_signal_parameters()
521 state->fectype = (enum dvbs2_fectype)((tmp & 0x02) >> 1); in get_signal_parameters()
526 switch (tmp & 0x1F) { in get_signal_parameters()
527 case 0x0d: in get_signal_parameters()
530 case 0x12: in get_signal_parameters()
533 case 0x15: in get_signal_parameters()
536 case 0x18: in get_signal_parameters()
539 case 0x1a: in get_signal_parameters()
543 state->is_vcm = 0; in get_signal_parameters()
547 return 0; in get_signal_parameters()
555 tmp &= ~0xC0; in tracking_optimization()
559 tmp |= 0x40; in tracking_optimization()
562 tmp |= 0x80; in tracking_optimization()
565 tmp |= 0xC0; in tracking_optimization()
573 RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01, in tracking_optimization()
574 0x03); in tracking_optimization()
585 state->regoff, 0x2a); in tracking_optimization()
590 state->regoff, 0x2a); in tracking_optimization()
595 state->regoff, 0x2a); in tracking_optimization()
601 return 0; in tracking_optimization()
608 int imin = 0; in table_lookup()
613 /* Assumes Table[0].RegValue > Table[imax].RegValue */ in table_lookup()
614 if (reg_value >= table[0].reg_value) { in table_lookup()
615 value = table[0].value; in table_lookup()
630 if (reg_diff != 0) in table_lookup()
648 *signal_to_noise = 0; in get_signal_to_noise()
670 return 0; in get_signal_to_noise()
685 if ((regs[0] & 0x80) == 0) { in get_bit_error_rate_s()
688 state->last_bernumerator = ((u32)(regs[0] & 0x7F) << 16) | in get_bit_error_rate_s()
694 0x20 | state->berscale); in get_bit_error_rate_s()
699 state->regoff, 0x20 | in get_bit_error_rate_s()
705 return 0; in get_bit_error_rate_s()
711 { 0, 0}, /* DUMMY_PLF */ in dvbs2_nbch()
759 if ((regs[0] & 0x80) == 0) { in get_bit_error_rate_s2()
764 state->last_bernumerator = (((u32)regs[0] & 0x7F) << 16) | in get_bit_error_rate_s2()
769 0x20 | state->berscale); in get_bit_error_rate_s2()
774 0x20 | state->berscale); in get_bit_error_rate_s2()
785 *bernumerator = 0; in get_bit_error_rate()
798 return 0; in get_bit_error_rate()
861 return 0; in set_mclock()
870 state->tscfgh | 0x01); in stop()
872 tmp &= ~0x01; /* release reset DVBS2 packet delin */ in stop()
875 write_reg(state, RSTV0910_P2_AGC2O + state->regoff, 0x5B); in stop()
877 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5c); in stop()
878 state->started = 0; in stop()
881 return 0; in stop()
891 pls_code & 0xff); in set_pls()
893 (pls_code >> 8) & 0xff); in set_pls()
895 0x04 | ((pls_code >> 16) & 0x03)); in set_pls()
903 if (isi == 0x80000000) { in set_isi()
909 isi & 0xff); in set_isi()
910 write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0xff); in set_isi()
913 SET_FIELD(ALGOSWRST, 0); in set_isi()
926 SET_FIELD(FORCE_CONTINUOUS, 0); in init_search_param()
927 SET_FIELD(FRAME_MODE, 0); in init_search_param()
928 SET_FIELD(FILTER_EN, 0); in init_search_param()
929 SET_FIELD(TSOUT_NOSYNC, 0); in init_search_param()
930 SET_FIELD(TSFIFO_EMBINDVB, 0); in init_search_param()
931 SET_FIELD(TSDEL_SYNCBYTE, 0); in init_search_param()
932 SET_REG(UPLCCST0, 0xe0); in init_search_param()
933 SET_FIELD(TSINS_TOKEN, 0); in init_search_param()
934 SET_FIELD(HYSTERESIS_THRESHOLD, 0); in init_search_param()
938 return 0; in init_search_param()
947 val = 0x01; in enable_puncture_rate()
950 val = 0x02; in enable_puncture_rate()
953 val = 0x04; in enable_puncture_rate()
956 val = 0x08; in enable_puncture_rate()
959 val = 0x20; in enable_puncture_rate()
963 val = 0x2f; in enable_puncture_rate()
972 state->vth[0] = 0xd7; in set_vth_default()
973 state->vth[1] = 0x85; in set_vth_default()
974 state->vth[2] = 0x58; in set_vth_default()
975 state->vth[3] = 0x3a; in set_vth_default()
976 state->vth[4] = 0x34; in set_vth_default()
977 state->vth[5] = 0x28; in set_vth_default()
978 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]); in set_vth_default()
984 return 0; in set_vth_default()
1002 u16 reg_value = (tmp[0] << 8) | tmp[1]; in set_vth()
1006 for (i = 0; i < 6; i += 1) in set_vth()
1010 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]); in set_vth()
1029 state->demod_lock_time = 0; in start()
1033 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5C); in start()
1060 ((symb >> 8) & 0x7F)); in start()
1061 write_reg(state, RSTV0910_P2_SFRINIT0 + state->regoff, (symb & 0xFF)); in start()
1063 state->demod_bits |= 0x80; in start()
1069 reg_dmdcfgmd |= 0xC0); in start()
1072 RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01, 0x00); in start()
1075 write_reg(state, RSTV0910_P2_FECM + state->regoff, 0x00); in start()
1076 write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x2F); in start()
1081 write_reg(state, RSTV0910_P2_ACLC2S2Q + state->regoff, 0x0B); in start()
1082 write_reg(state, RSTV0910_P2_ACLC2S28 + state->regoff, 0x0A); in start()
1083 write_reg(state, RSTV0910_P2_BCLC2S2Q + state->regoff, 0x84); in start()
1084 write_reg(state, RSTV0910_P2_BCLC2S28 + state->regoff, 0x84); in start()
1085 write_reg(state, RSTV0910_P2_CARHDR + state->regoff, 0x1C); in start()
1086 write_reg(state, RSTV0910_P2_CARFREQ + state->regoff, 0x79); in start()
1088 write_reg(state, RSTV0910_P2_ACLC2S216A + state->regoff, 0x29); in start()
1089 write_reg(state, RSTV0910_P2_ACLC2S232A + state->regoff, 0x09); in start()
1090 write_reg(state, RSTV0910_P2_BCLC2S216A + state->regoff, 0x84); in start()
1091 write_reg(state, RSTV0910_P2_BCLC2S232A + state->regoff, 0x84); in start()
1097 write_reg(state, RSTV0910_TSTRES0, state->nr ? 0x04 : 0x08); in start()
1098 write_reg(state, RSTV0910_TSTRES0, 0); in start()
1102 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F); in start()
1104 write_reg(state, RSTV0910_P2_CARCFG + state->regoff, 0x46); in start()
1113 (freq >> 8) & 0xff); in start()
1114 write_reg(state, RSTV0910_P2_CFRUP0 + state->regoff, (freq & 0xff)); in start()
1118 (freq >> 8) & 0xff); in start()
1119 write_reg(state, RSTV0910_P2_CFRLOW0 + state->regoff, (freq & 0xff)); in start()
1121 /* init the demod frequency offset to 0 */ in start()
1122 write_reg(state, RSTV0910_P2_CFRINIT1 + state->regoff, 0); in start()
1123 write_reg(state, RSTV0910_P2_CFRINIT0 + state->regoff, 0); in start()
1125 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F); in start()
1127 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x15); in start()
1132 return 0; in start()
1137 u16 offs = state->nr ? 0x40 : 0; /* Address offset */ in init_diseqc()
1141 write_reg(state, RSTV0910_P1_DISRXCFG + offs, 0x00); in init_diseqc()
1142 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0xBA); /* Reset = 1 */ in init_diseqc()
1143 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A); /* Reset = 0 */ in init_diseqc()
1145 return 0; in init_diseqc()
1153 state->started = 0; in probe()
1155 if (read_reg(state, RSTV0910_MID, &id) < 0) in probe()
1158 if (id != 0x51) in probe()
1162 write_reg(state, RSTV0910_P1_I2CRPT, 0x24); in probe()
1164 write_reg(state, RSTV0910_P2_I2CRPT, 0x24); in probe()
1166 write_reg(state, RSTV0910_I2CCFG, 0x88); /* state->i2ccfg */ in probe()
1168 write_reg(state, RSTV0910_OUTCFG, 0x00); /* OUTCFG */ in probe()
1169 write_reg(state, RSTV0910_PADCFG, 0x05); /* RFAGC Pads Dev = 05 */ in probe()
1170 write_reg(state, RSTV0910_SYNTCTRL, 0x02); /* SYNTCTRL */ in probe()
1172 write_reg(state, RSTV0910_CFGEXT, 0x02); /* CFGEXT */ in probe()
1175 write_reg(state, RSTV0910_GENCFG, 0x14); /* GENCFG */ in probe()
1177 write_reg(state, RSTV0910_GENCFG, 0x15); /* GENCFG */ in probe()
1179 write_reg(state, RSTV0910_P1_TNRCFG2, 0x02); /* IQSWAP = 0 */ in probe()
1180 write_reg(state, RSTV0910_P2_TNRCFG2, 0x82); /* IQSWAP = 1 */ in probe()
1182 write_reg(state, RSTV0910_P1_CAR3CFG, 0x02); in probe()
1183 write_reg(state, RSTV0910_P2_CAR3CFG, 0x02); in probe()
1184 write_reg(state, RSTV0910_P1_DMDCFG4, 0x04); in probe()
1185 write_reg(state, RSTV0910_P2_DMDCFG4, 0x04); in probe()
1187 write_reg(state, RSTV0910_TSTRES0, 0x80); /* LDPC Reset */ in probe()
1188 write_reg(state, RSTV0910_TSTRES0, 0x00); in probe()
1190 write_reg(state, RSTV0910_P1_TSPIDFLT1, 0x00); in probe()
1191 write_reg(state, RSTV0910_P2_TSPIDFLT1, 0x00); in probe()
1193 write_reg(state, RSTV0910_P1_TMGCFG2, 0x80); in probe()
1194 write_reg(state, RSTV0910_P2_TMGCFG2, 0x80); in probe()
1199 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01); in probe()
1201 write_reg(state, RSTV0910_P1_TSCFGM, 0xC0); /* Manual speed */ in probe()
1202 write_reg(state, RSTV0910_P1_TSCFGL, 0x20); in probe()
1206 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01); in probe()
1208 write_reg(state, RSTV0910_P2_TSCFGM, 0xC0); /* Manual speed */ in probe()
1209 write_reg(state, RSTV0910_P2_TSCFGL, 0x20); in probe()
1214 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01); in probe()
1215 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01); in probe()
1222 write_reg(state, RSTV0910_P1_TSINSDELM, 0x17); in probe()
1223 write_reg(state, RSTV0910_P1_TSINSDELL, 0xff); in probe()
1225 write_reg(state, RSTV0910_P2_TSINSDELM, 0x17); in probe()
1226 write_reg(state, RSTV0910_P2_TSINSDELL, 0xff); in probe()
1229 return 0; in probe()
1235 u8 i2crpt = state->i2crpt & ~0x86; in gate_ctrl()
1244 * enable=0 (close I2C gate) releases the lock in gate_ctrl()
1249 i2crpt |= 0x80; in gate_ctrl()
1251 i2crpt |= 0x02; in gate_ctrl()
1255 RSTV0910_P1_I2CRPT, i2crpt) < 0) { in gate_ctrl()
1270 return 0; in gate_ctrl()
1278 if (state->base->count == 0) { in release()
1287 int stat = 0; in set_parameters()
1309 (enum fe_stv0910_roll_off)(bbheader[0] & 0x03); in manage_matype_info()
1310 state->is_vcm = (bbheader[0] & 0x10) == 0; in manage_matype_info()
1311 state->is_standard_broadcast = (bbheader[0] & 0xFC) == 0xF0; in manage_matype_info()
1313 state->is_vcm = 0; in manage_matype_info()
1317 return 0; in manage_matype_info()
1327 p->cnr.stat[0].scale = FE_SCALE_DECIBEL; in read_snr()
1328 p->cnr.stat[0].svalue = 100 * snrval; /* fix scale */ in read_snr()
1330 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_snr()
1333 return 0; in read_snr()
1344 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; in read_ber()
1345 p->pre_bit_error.stat[0].uvalue = n; in read_ber()
1346 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; in read_ber()
1347 p->pre_bit_count.stat[0].uvalue = d; in read_ber()
1349 return 0; in read_ber()
1358 s32 padc, power = 0; in read_signal_strength()
1363 agc = (((u32)reg[0]) << 8) | reg[1]; in read_signal_strength()
1365 for (i = 0; i < 5; i += 1) { in read_signal_strength()
1367 power += (u32)reg[0] * (u32)reg[0] in read_signal_strength()
1375 p->strength.stat[0].scale = FE_SCALE_DECIBEL; in read_signal_strength()
1376 p->strength.stat[0].svalue = (padc - agc); in read_signal_strength()
1383 u8 dmd_state = 0; in read_status()
1384 u8 dstatus = 0; in read_status()
1386 u32 feclock = 0; in read_status()
1388 *status = 0; in read_status()
1392 if (dmd_state & 0x40) { in read_status()
1394 if (dstatus & 0x08) in read_status()
1395 cur_receive_mode = (dmd_state & 0x20) ? in read_status()
1402 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_status()
1403 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_status()
1404 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_status()
1405 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_status()
1407 return 0; in read_status()
1427 state->tscfgh | 0x01); in read_status()
1431 if (dmd_state & 0x40) { in read_status()
1438 feclock = (pdelstatus & 0x02) != 0; in read_status()
1445 feclock = (vstatus & 0x08) != 0; in read_status()
1455 state->first_time_lock = 0; in read_status()
1462 * FSTV0910_P2_MANUALS2_ROLLOFF = 0 in read_status()
1464 state->demod_bits &= ~0x84; in read_status()
1472 tmp |= 0x40; in read_status()
1477 tmp &= ~0x40; in read_status()
1483 state->last_bernumerator = 0; in read_status()
1491 state->last_bernumerator = 0; in read_status()
1500 RSTV0910_P2_FBERCPT4 + state->regoff, 0x00); in read_status()
1506 RSTV0910_P2_ERRCTRL2 + state->regoff, 0xc1); in read_status()
1521 mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2); in read_status()
1537 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_status()
1543 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_status()
1544 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in read_status()
1547 return 0; in read_status()
1559 const enum fe_modulation modcod2mod[0x20] = { in get_frontend()
1569 const enum fe_code_rate modcod2fec[0x20] = { in get_frontend()
1580 mc = ((tmp & 0x7c) >> 2); in get_frontend()
1581 p->pilot = (tmp & 0x01) ? PILOT_ON : PILOT_OFF; in get_frontend()
1586 switch (tmp & 0x1F) { in get_frontend()
1587 case 0x0d: in get_frontend()
1590 case 0x12: in get_frontend()
1593 case 0x15: in get_frontend()
1596 case 0x18: in get_frontend()
1599 case 0x1a: in get_frontend()
1613 return 0; in get_frontend()
1635 return 0; in tune()
1638 return 0; in tune()
1649 u16 offs = state->nr ? 0x40 : 0; in set_tone()
1653 return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x38); in set_tone()
1655 return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3a); in set_tone()
1666 u16 offs = state->nr ? 0x40 : 0; in wait_dis()
1668 for (i = 0; i < 10; i++) { in wait_dis()
1671 return 0; in wait_dis()
1685 for (i = 0; i < cmd->msg_len; i++) { in send_master_cmd()
1686 wait_dis(state, 0x40, 0x00); in send_master_cmd()
1689 SET_FIELD(DIS_PRECHARGE, 0); in send_master_cmd()
1690 wait_dis(state, 0x20, 0x20); in send_master_cmd()
1691 return 0; in send_master_cmd()
1701 value = 0x00; in send_burst()
1704 value = 0xFF; in send_burst()
1708 wait_dis(state, 0x40, 0x00); in send_burst()
1710 SET_FIELD(DIS_PRECHARGE, 0); in send_burst()
1711 wait_dis(state, 0x20, 0x20); in send_burst()
1713 return 0; in send_burst()
1721 return 0; in sleep()
1767 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in stv0910_init_stats()
1769 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in stv0910_init_stats()
1771 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in stv0910_init_stats()
1773 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in stv0910_init_stats()
1787 state->tscfgh = 0x20 | (cfg->parallel ? 0 : 0x40); in stv0910_attach()
1788 state->tsgeneral = (cfg->parallel == 2) ? 0x02 : 0x00; in stv0910_attach()
1789 state->i2crpt = 0x0A | ((cfg->rptlvl & 0x07) << 4); in stv0910_attach()
1791 state->tsspeed = (cfg->tsspeed ? cfg->tsspeed : 0x28); in stv0910_attach()
1793 state->regoff = state->nr ? 0 : 0x200; in stv0910_attach()
1795 state->demod_bits = 0x10; /* Inversion : Auto with reset to 0 */ in stv0910_attach()
1797 state->cur_scrambling_code = (~0U); in stv0910_attach()
1798 state->single = cfg->single ? 1 : 0; in stv0910_attach()
1816 if (probe(state) < 0) { in stv0910_attach()