228 	int status;  in i2c_write()  local
239 	status = drxk_i2c_transfer(state, &msg, 1);  in i2c_write()
240 	if (status >= 0 && status != 1)  in i2c_write()
241 		status = -EIO;  in i2c_write()
243 	if (status < 0)  in i2c_write()
246 	return status;  in i2c_write()
252 	int status;  in i2c_read()  local
260 	status = drxk_i2c_transfer(state, msgs, 2);  in i2c_read()
261 	if (status != 2) {  in i2c_read()
264 		if (status >= 0)  in i2c_read()
265 			status = -EIO;  in i2c_read()
268 		return status;  in i2c_read()
285 	int status;  in read16_flags()  local
303 	status = i2c_read(state, adr, mm1, len, mm2, 2);  in read16_flags()
304 	if (status < 0)  in read16_flags()
305 		return status;  in read16_flags()
319 	int status;  in read32_flags()  local
337 	status = i2c_read(state, adr, mm1, len, mm2, 4);  in read32_flags()
338 	if (status < 0)  in read32_flags()
339 		return status;  in read32_flags()
415 	int status = 0, blk_size = block_size;  in write_block()  local
451 		status = i2c_write(state, state->demod_address,  in write_block()
453 		if (status < 0) {  in write_block()
462 	return status;  in write_block()
471 	int status;  in power_up_device()  local
477 	status = i2c_read1(state, state->demod_address, &data);  in power_up_device()
478 	if (status < 0) {  in power_up_device()
481 			status = i2c_write(state, state->demod_address,  in power_up_device()
485 			if (status < 0)  in power_up_device()
487 			status = i2c_read1(state, state->demod_address,  in power_up_device()
489 		} while (status < 0 &&  in power_up_device()
491 		if (status < 0 && retry_count >= DRXK_MAX_RETRIES_POWERUP)  in power_up_device()
496 	status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);  in power_up_device()
497 	if (status < 0)  in power_up_device()
499 	status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);  in power_up_device()
500 	if (status < 0)  in power_up_device()
503 	status = write16(state, SIO_CC_PLL_LOCK__A, 1);  in power_up_device()
504 	if (status < 0)  in power_up_device()
510 	if (status < 0)  in power_up_device()
511 		pr_err("Error %d on %s\n", status, __func__);  in power_up_device()
513 	return status;  in power_up_device()
754 	int status = 0;  in drxx_open()  local
761 	status = write16(state, SCU_RAM_GPIO__A,  in drxx_open()
763 	if (status < 0)  in drxx_open()
766 	status = read16(state, SIO_TOP_COMM_KEY__A, &key);  in drxx_open()
767 	if (status < 0)  in drxx_open()
769 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);  in drxx_open()
770 	if (status < 0)  in drxx_open()
772 	status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);  in drxx_open()
773 	if (status < 0)  in drxx_open()
775 	status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);  in drxx_open()
776 	if (status < 0)  in drxx_open()
778 	status = write16(state, SIO_TOP_COMM_KEY__A, key);  in drxx_open()
780 	if (status < 0)  in drxx_open()
781 		pr_err("Error %d on %s\n", status, __func__);  in drxx_open()
782 	return status;  in drxx_open()
789 	int status;  in get_device_capabilities()  local
796 	status = write16(state, SCU_RAM_GPIO__A,  in get_device_capabilities()
798 	if (status < 0)  in get_device_capabilities()
800 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);  in get_device_capabilities()
801 	if (status < 0)  in get_device_capabilities()
803 	status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg);  in get_device_capabilities()
804 	if (status < 0)  in get_device_capabilities()
806 	status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);  in get_device_capabilities()
807 	if (status < 0)  in get_device_capabilities()
834 	status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo);  in get_device_capabilities()
835 	if (status < 0)  in get_device_capabilities()
838 	pr_info("status = 0x%08x\n", sio_top_jtagid_lo);  in get_device_capabilities()
856 		status = -EINVAL;  in get_device_capabilities()
968 		status = -EINVAL;  in get_device_capabilities()
978 	if (status < 0)  in get_device_capabilities()
979 		pr_err("Error %d on %s\n", status, __func__);  in get_device_capabilities()
982 	return status;  in get_device_capabilities()
987 	int status;  in hi_command()  local
993 	status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);  in hi_command()
994 	if (status < 0)  in hi_command()
1012 			status = read16(state, SIO_HI_RA_RAM_CMD__A,  in hi_command()
1014 		} while ((status < 0 || wait_cmd) && (retry_count < DRXK_MAX_RETRIES));  in hi_command()
1015 		if (status < 0)  in hi_command()
1017 		status = read16(state, SIO_HI_RA_RAM_RES__A, p_result);  in hi_command()
1020 	if (status < 0)  in hi_command()
1021 		pr_err("Error %d on %s\n", status, __func__);  in hi_command()
1023 	return status;  in hi_command()
1028 	int status;  in hi_cfg_command()  local
1034 	status = write16(state, SIO_HI_RA_RAM_PAR_6__A,  in hi_cfg_command()
1036 	if (status < 0)  in hi_cfg_command()
1038 	status = write16(state, SIO_HI_RA_RAM_PAR_5__A,  in hi_cfg_command()
1040 	if (status < 0)  in hi_cfg_command()
1042 	status = write16(state, SIO_HI_RA_RAM_PAR_4__A,  in hi_cfg_command()
1044 	if (status < 0)  in hi_cfg_command()
1046 	status = write16(state, SIO_HI_RA_RAM_PAR_3__A,  in hi_cfg_command()
1048 	if (status < 0)  in hi_cfg_command()
1050 	status = write16(state, SIO_HI_RA_RAM_PAR_2__A,  in hi_cfg_command()
1052 	if (status < 0)  in hi_cfg_command()
1054 	status = write16(state, SIO_HI_RA_RAM_PAR_1__A,  in hi_cfg_command()
1056 	if (status < 0)  in hi_cfg_command()
1058 	status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL);  in hi_cfg_command()
1059 	if (status < 0)  in hi_cfg_command()
1065 	if (status < 0)  in hi_cfg_command()
1066 		pr_err("Error %d on %s\n", status, __func__);  in hi_cfg_command()
1067 	return status;  in hi_cfg_command()
1084 	int status;  in mpegts_configure_pins()  local
1094 	status = write16(state, SCU_RAM_GPIO__A,  in mpegts_configure_pins()
1096 	if (status < 0)  in mpegts_configure_pins()
1100 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);  in mpegts_configure_pins()
1101 	if (status < 0)  in mpegts_configure_pins()
1106 		status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);  in mpegts_configure_pins()
1107 		if (status < 0)  in mpegts_configure_pins()
1109 		status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);  in mpegts_configure_pins()
1110 		if (status < 0)  in mpegts_configure_pins()
1112 		status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);  in mpegts_configure_pins()
1113 		if (status < 0)  in mpegts_configure_pins()
1115 		status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);  in mpegts_configure_pins()
1116 		if (status < 0)  in mpegts_configure_pins()
1118 		status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);  in mpegts_configure_pins()
1119 		if (status < 0)  in mpegts_configure_pins()
1121 		status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);  in mpegts_configure_pins()
1122 		if (status < 0)  in mpegts_configure_pins()
1124 		status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);  in mpegts_configure_pins()
1125 		if (status < 0)  in mpegts_configure_pins()
1127 		status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);  in mpegts_configure_pins()
1128 		if (status < 0)  in mpegts_configure_pins()
1130 		status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);  in mpegts_configure_pins()
1131 		if (status < 0)  in mpegts_configure_pins()
1133 		status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);  in mpegts_configure_pins()
1134 		if (status < 0)  in mpegts_configure_pins()
1136 		status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);  in mpegts_configure_pins()
1137 		if (status < 0)  in mpegts_configure_pins()
1139 		status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);  in mpegts_configure_pins()
1140 		if (status < 0)  in mpegts_configure_pins()
1151 		status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg);  in mpegts_configure_pins()
1152 		if (status < 0)  in mpegts_configure_pins()
1158 		status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);  in mpegts_configure_pins()
1159 		if (status < 0)  in mpegts_configure_pins()
1161 		status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);  in mpegts_configure_pins()
1162 		if (status < 0)  in mpegts_configure_pins()
1167 			status = write16(state, SIO_PDR_MD1_CFG__A,  in mpegts_configure_pins()
1169 			if (status < 0)  in mpegts_configure_pins()
1171 			status = write16(state, SIO_PDR_MD2_CFG__A,  in mpegts_configure_pins()
1173 			if (status < 0)  in mpegts_configure_pins()
1175 			status = write16(state, SIO_PDR_MD3_CFG__A,  in mpegts_configure_pins()
1177 			if (status < 0)  in mpegts_configure_pins()
1179 			status = write16(state, SIO_PDR_MD4_CFG__A,  in mpegts_configure_pins()
1181 			if (status < 0)  in mpegts_configure_pins()
1183 			status = write16(state, SIO_PDR_MD5_CFG__A,  in mpegts_configure_pins()
1185 			if (status < 0)  in mpegts_configure_pins()
1187 			status = write16(state, SIO_PDR_MD6_CFG__A,  in mpegts_configure_pins()
1189 			if (status < 0)  in mpegts_configure_pins()
1191 			status = write16(state, SIO_PDR_MD7_CFG__A,  in mpegts_configure_pins()
1193 			if (status < 0)  in mpegts_configure_pins()
1200 			status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);  in mpegts_configure_pins()
1201 			if (status < 0)  in mpegts_configure_pins()
1203 			status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);  in mpegts_configure_pins()
1204 			if (status < 0)  in mpegts_configure_pins()
1206 			status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);  in mpegts_configure_pins()
1207 			if (status < 0)  in mpegts_configure_pins()
1209 			status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);  in mpegts_configure_pins()
1210 			if (status < 0)  in mpegts_configure_pins()
1212 			status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);  in mpegts_configure_pins()
1213 			if (status < 0)  in mpegts_configure_pins()
1215 			status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);  in mpegts_configure_pins()
1216 			if (status < 0)  in mpegts_configure_pins()
1218 			status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);  in mpegts_configure_pins()
1219 			if (status < 0)  in mpegts_configure_pins()
1222 		status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg);  in mpegts_configure_pins()
1223 		if (status < 0)  in mpegts_configure_pins()
1225 		status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg);  in mpegts_configure_pins()
1226 		if (status < 0)  in mpegts_configure_pins()
1230 	status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);  in mpegts_configure_pins()
1231 	if (status < 0)  in mpegts_configure_pins()
1234 	status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);  in mpegts_configure_pins()
1236 	if (status < 0)  in mpegts_configure_pins()
1237 		pr_err("Error %d on %s\n", status, __func__);  in mpegts_configure_pins()
1238 	return status;  in mpegts_configure_pins()
1252 	int status;  in bl_chain_cmd()  local
1257 	status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);  in bl_chain_cmd()
1258 	if (status < 0)  in bl_chain_cmd()
1260 	status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset);  in bl_chain_cmd()
1261 	if (status < 0)  in bl_chain_cmd()
1263 	status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements);  in bl_chain_cmd()
1264 	if (status < 0)  in bl_chain_cmd()
1266 	status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);  in bl_chain_cmd()
1267 	if (status < 0)  in bl_chain_cmd()
1273 		status = read16(state, SIO_BL_STATUS__A, &bl_status);  in bl_chain_cmd()
1274 		if (status < 0)  in bl_chain_cmd()
1281 		status = -EINVAL;  in bl_chain_cmd()
1285 	if (status < 0)  in bl_chain_cmd()
1286 		pr_err("Error %d on %s\n", status, __func__);  in bl_chain_cmd()
1289 	return status;  in bl_chain_cmd()
1302 	int status = 0;  in download_microcode()  local
1346 		status = write_block(state, address, block_size, p_src);  in download_microcode()
1347 		if (status < 0) {  in download_microcode()
1348 			pr_err("Error %d while loading firmware\n", status);  in download_microcode()
1354 	return status;  in download_microcode()
1359 	int status;  in dvbt_enable_ofdm_token_ring()  local
1372 	status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);  in dvbt_enable_ofdm_token_ring()
1373 	if (status >= 0 && data == desired_status) {  in dvbt_enable_ofdm_token_ring()
1374 		/* tokenring already has correct status */  in dvbt_enable_ofdm_token_ring()
1375 		return status;  in dvbt_enable_ofdm_token_ring()
1378 	status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl);  in dvbt_enable_ofdm_token_ring()
1382 		status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);  in dvbt_enable_ofdm_token_ring()
1383 		if ((status >= 0 && data == desired_status)  in dvbt_enable_ofdm_token_ring()
1392 	return status;  in dvbt_enable_ofdm_token_ring()
1397 	int status = 0;  in mpegts_stop()  local
1404 	status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);  in mpegts_stop()
1405 	if (status < 0)  in mpegts_stop()
1408 	status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);  in mpegts_stop()
1409 	if (status < 0)  in mpegts_stop()
1413 	status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode);  in mpegts_stop()
1414 	if (status < 0)  in mpegts_stop()
1417 	status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode);  in mpegts_stop()
1420 	if (status < 0)  in mpegts_stop()
1421 		pr_err("Error %d on %s\n", status, __func__);  in mpegts_stop()
1423 	return status;  in mpegts_stop()
1434 	int status = -EINVAL;  in scu_command()  local
1445 		pr_err("Error %d on %s\n", status, __func__);  in scu_command()
1446 		return status;  in scu_command()
1468 		status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd);  in scu_command()
1469 		if (status < 0)  in scu_command()
1474 		status = -EIO;  in scu_command()
1483 			status = read16(state, SCU_RAM_PARAM_0__A - ii,  in scu_command()
1485 			if (status < 0)  in scu_command()
1514 		status = -EINVAL;  in scu_command()
1519 	if (status < 0)  in scu_command()
1520 		pr_err("Error %d on %s\n", status, __func__);  in scu_command()
1523 	return status;  in scu_command()
1529 	int status;  in set_iqm_af()  local
1534 	status = read16(state, IQM_AF_STDBY__A, &data);  in set_iqm_af()
1535 	if (status < 0)  in set_iqm_af()
1552 	status = write16(state, IQM_AF_STDBY__A, data);  in set_iqm_af()
1555 	if (status < 0)  in set_iqm_af()
1556 		pr_err("Error %d on %s\n", status, __func__);  in set_iqm_af()
1557 	return status;  in set_iqm_af()
1562 	int status = 0;  in ctrl_power_mode()  local
1598 		status = power_up_device(state);  in ctrl_power_mode()
1599 		if (status < 0)  in ctrl_power_mode()
1601 		status = dvbt_enable_ofdm_token_ring(state, true);  in ctrl_power_mode()
1602 		if (status < 0)  in ctrl_power_mode()
1620 			status = mpegts_stop(state);  in ctrl_power_mode()
1621 			if (status < 0)  in ctrl_power_mode()
1623 			status = power_down_dvbt(state, false);  in ctrl_power_mode()
1624 			if (status < 0)  in ctrl_power_mode()
1629 			status = mpegts_stop(state);  in ctrl_power_mode()
1630 			if (status < 0)  in ctrl_power_mode()
1632 			status = power_down_qam(state);  in ctrl_power_mode()
1633 			if (status < 0)  in ctrl_power_mode()
1639 		status = dvbt_enable_ofdm_token_ring(state, false);  in ctrl_power_mode()
1640 		if (status < 0)  in ctrl_power_mode()
1642 		status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode);  in ctrl_power_mode()
1643 		if (status < 0)  in ctrl_power_mode()
1645 		status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);  in ctrl_power_mode()
1646 		if (status < 0)  in ctrl_power_mode()
1652 			status = hi_cfg_command(state);  in ctrl_power_mode()
1653 			if (status < 0)  in ctrl_power_mode()
1660 	if (status < 0)  in ctrl_power_mode()
1661 		pr_err("Error %d on %s\n", status, __func__);  in ctrl_power_mode()
1663 	return status;  in ctrl_power_mode()
1671 	int status;  in power_down_dvbt()  local
1675 	status = read16(state, SCU_COMM_EXEC__A, &data);  in power_down_dvbt()
1676 	if (status < 0)  in power_down_dvbt()
1680 		status = scu_command(state,  in power_down_dvbt()
1684 		if (status < 0)  in power_down_dvbt()
1687 		status = scu_command(state,  in power_down_dvbt()
1691 		if (status < 0)  in power_down_dvbt()
1696 	status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);  in power_down_dvbt()
1697 	if (status < 0)  in power_down_dvbt()
1699 	status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);  in power_down_dvbt()
1700 	if (status < 0)  in power_down_dvbt()
1702 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);  in power_down_dvbt()
1703 	if (status < 0)  in power_down_dvbt()
1707 	status = set_iqm_af(state, false);  in power_down_dvbt()
1708 	if (status < 0)  in power_down_dvbt()
1713 		status = ctrl_power_mode(state, &power_mode);  in power_down_dvbt()
1714 		if (status < 0)  in power_down_dvbt()
1718 	if (status < 0)  in power_down_dvbt()
1719 		pr_err("Error %d on %s\n", status, __func__);  in power_down_dvbt()
1720 	return status;  in power_down_dvbt()
1726 	int status = 0;  in setoperation_mode()  local
1736 	status = write16(state, SCU_RAM_GPIO__A,  in setoperation_mode()
1738 	if (status < 0)  in setoperation_mode()
1750 		status = mpegts_stop(state);  in setoperation_mode()
1751 		if (status < 0)  in setoperation_mode()
1753 		status = power_down_dvbt(state, true);  in setoperation_mode()
1754 		if (status < 0)  in setoperation_mode()
1760 		status = mpegts_stop(state);  in setoperation_mode()
1761 		if (status < 0)  in setoperation_mode()
1763 		status = power_down_qam(state);  in setoperation_mode()
1764 		if (status < 0)  in setoperation_mode()
1770 		status = -EINVAL;  in setoperation_mode()
1781 		status = set_dvbt_standard(state, o_mode);  in setoperation_mode()
1782 		if (status < 0)  in setoperation_mode()
1790 		status = set_qam_standard(state, o_mode);  in setoperation_mode()
1791 		if (status < 0)  in setoperation_mode()
1796 		status = -EINVAL;  in setoperation_mode()
1799 	if (status < 0)  in setoperation_mode()
1800 		pr_err("Error %d on %s\n", status, __func__);  in setoperation_mode()
1801 	return status;  in setoperation_mode()
1807 	int status = -EINVAL;  in start()  local
1828 		status = set_qam(state, i_freqk_hz, offsetk_hz);  in start()
1829 		if (status < 0)  in start()
1835 		status = mpegts_stop(state);  in start()
1836 		if (status < 0)  in start()
1838 		status = set_dvbt(state, i_freqk_hz, offsetk_hz);  in start()
1839 		if (status < 0)  in start()
1841 		status = dvbt_start(state);  in start()
1842 		if (status < 0)  in start()
1850 	if (status < 0)  in start()
1851 		pr_err("Error %d on %s\n", status, __func__);  in start()
1852 	return status;  in start()
1865 	int status = -EINVAL;  in get_lock_status()  local
1879 		status = get_qam_lock_status(state, p_lock_status);  in get_lock_status()
1882 		status = get_dvbt_lock_status(state, p_lock_status);  in get_lock_status()
1890 	if (status < 0)  in get_lock_status()
1891 		pr_err("Error %d on %s\n", status, __func__);  in get_lock_status()
1892 	return status;  in get_lock_status()
1897 	int status;  in mpegts_start()  local
1902 	status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);  in mpegts_start()
1903 	if (status < 0)  in mpegts_start()
1906 	status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);  in mpegts_start()
1907 	if (status < 0)  in mpegts_start()
1909 	status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);  in mpegts_start()
1911 	if (status < 0)  in mpegts_start()
1912 		pr_err("Error %d on %s\n", status, __func__);  in mpegts_start()
1913 	return status;  in mpegts_start()
1918 	int status;  in mpegts_dto_init()  local
1923 	status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);  in mpegts_dto_init()
1924 	if (status < 0)  in mpegts_dto_init()
1926 	status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);  in mpegts_dto_init()
1927 	if (status < 0)  in mpegts_dto_init()
1929 	status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);  in mpegts_dto_init()
1930 	if (status < 0)  in mpegts_dto_init()
1932 	status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);  in mpegts_dto_init()
1933 	if (status < 0)  in mpegts_dto_init()
1935 	status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);  in mpegts_dto_init()
1936 	if (status < 0)  in mpegts_dto_init()
1938 	status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);  in mpegts_dto_init()
1939 	if (status < 0)  in mpegts_dto_init()
1941 	status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);  in mpegts_dto_init()
1942 	if (status < 0)  in mpegts_dto_init()
1944 	status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);  in mpegts_dto_init()
1945 	if (status < 0)  in mpegts_dto_init()
1949 	status = write16(state, FEC_OC_OCR_INVERT__A, 0);  in mpegts_dto_init()
1950 	if (status < 0)  in mpegts_dto_init()
1952 	status = write16(state, FEC_OC_SNC_LWM__A, 2);  in mpegts_dto_init()
1953 	if (status < 0)  in mpegts_dto_init()
1955 	status = write16(state, FEC_OC_SNC_HWM__A, 12);  in mpegts_dto_init()
1957 	if (status < 0)  in mpegts_dto_init()
1958 		pr_err("Error %d on %s\n", status, __func__);  in mpegts_dto_init()
1960 	return status;  in mpegts_dto_init()
1966 	int status;  in mpegts_dto_setup()  local
1983 	status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode);  in mpegts_dto_setup()
1984 	if (status < 0)  in mpegts_dto_setup()
1986 	status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode);  in mpegts_dto_setup()
1987 	if (status < 0)  in mpegts_dto_setup()
2022 		status = -EINVAL;  in mpegts_dto_setup()
2024 	if (status < 0)  in mpegts_dto_setup()
2066 	status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len);  in mpegts_dto_setup()
2067 	if (status < 0)  in mpegts_dto_setup()
2069 	status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period);  in mpegts_dto_setup()
2070 	if (status < 0)  in mpegts_dto_setup()
2072 	status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode);  in mpegts_dto_setup()
2073 	if (status < 0)  in mpegts_dto_setup()
2075 	status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode);  in mpegts_dto_setup()
2076 	if (status < 0)  in mpegts_dto_setup()
2078 	status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode);  in mpegts_dto_setup()
2079 	if (status < 0)  in mpegts_dto_setup()
2081 	status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode);  in mpegts_dto_setup()
2082 	if (status < 0)  in mpegts_dto_setup()
2086 	status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate);  in mpegts_dto_setup()
2087 	if (status < 0)  in mpegts_dto_setup()
2089 	status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A,  in mpegts_dto_setup()
2091 	if (status < 0)  in mpegts_dto_setup()
2093 	status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode);  in mpegts_dto_setup()
2095 	if (status < 0)  in mpegts_dto_setup()
2096 		pr_err("Error %d on %s\n", status, __func__);  in mpegts_dto_setup()
2097 	return status;  in mpegts_dto_setup()
2138 	int status = -EINVAL;  in set_agc_rf()  local
2150 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_rf()
2151 		if (status < 0)  in set_agc_rf()
2154 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_rf()
2155 		if (status < 0)  in set_agc_rf()
2157 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_rf()
2158 		if (status < 0)  in set_agc_rf()
2169 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_rf()
2170 		if (status < 0)  in set_agc_rf()
2174 		status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);  in set_agc_rf()
2175 		if (status < 0)  in set_agc_rf()
2183 		status = write16(state, SCU_RAM_AGC_KI_RED__A, data);  in set_agc_rf()
2184 		if (status < 0)  in set_agc_rf()
2194 			status = -EINVAL;  in set_agc_rf()
2200 			status = write16(state,  in set_agc_rf()
2203 			if (status < 0)  in set_agc_rf()
2208 		status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A,  in set_agc_rf()
2210 		if (status < 0)  in set_agc_rf()
2214 		status = write16(state, SCU_RAM_AGC_RF_MAX__A,  in set_agc_rf()
2216 		if (status < 0)  in set_agc_rf()
2223 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_rf()
2224 		if (status < 0)  in set_agc_rf()
2227 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_rf()
2228 		if (status < 0)  in set_agc_rf()
2232 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_rf()
2233 		if (status < 0)  in set_agc_rf()
2240 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_rf()
2241 		if (status < 0)  in set_agc_rf()
2245 		status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);  in set_agc_rf()
2246 		if (status < 0)  in set_agc_rf()
2250 		status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A,  in set_agc_rf()
2252 		if (status < 0)  in set_agc_rf()
2258 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_rf()
2259 		if (status < 0)  in set_agc_rf()
2262 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_rf()
2263 		if (status < 0)  in set_agc_rf()
2267 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_rf()
2268 		if (status < 0)  in set_agc_rf()
2271 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_rf()
2272 		if (status < 0)  in set_agc_rf()
2277 		status = -EINVAL;  in set_agc_rf()
2281 	if (status < 0)  in set_agc_rf()
2282 		pr_err("Error %d on %s\n", status, __func__);  in set_agc_rf()
2283 	return status;  in set_agc_rf()
2292 	int status = 0;  in set_agc_if()  local
2301 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_if()
2302 		if (status < 0)  in set_agc_if()
2305 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_if()
2306 		if (status < 0)  in set_agc_if()
2309 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_if()
2310 		if (status < 0)  in set_agc_if()
2321 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_if()
2322 		if (status < 0)  in set_agc_if()
2326 		status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);  in set_agc_if()
2327 		if (status < 0)  in set_agc_if()
2334 		status = write16(state, SCU_RAM_AGC_KI_RED__A, data);  in set_agc_if()
2335 		if (status < 0)  in set_agc_if()
2345 		status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,  in set_agc_if()
2347 		if (status < 0)  in set_agc_if()
2354 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_if()
2355 		if (status < 0)  in set_agc_if()
2358 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_if()
2359 		if (status < 0)  in set_agc_if()
2362 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_if()
2363 		if (status < 0)  in set_agc_if()
2374 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_if()
2375 		if (status < 0)  in set_agc_if()
2379 		status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,  in set_agc_if()
2381 		if (status < 0)  in set_agc_if()
2388 		status = read16(state, IQM_AF_STDBY__A, &data);  in set_agc_if()
2389 		if (status < 0)  in set_agc_if()
2392 		status = write16(state, IQM_AF_STDBY__A, data);  in set_agc_if()
2393 		if (status < 0)  in set_agc_if()
2397 		status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);  in set_agc_if()
2398 		if (status < 0)  in set_agc_if()
2401 		status = write16(state, SCU_RAM_AGC_CONFIG__A, data);  in set_agc_if()
2402 		if (status < 0)  in set_agc_if()
2409 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top);  in set_agc_if()
2411 	if (status < 0)  in set_agc_if()
2412 		pr_err("Error %d on %s\n", status, __func__);  in set_agc_if()
2413 	return status;  in set_agc_if()
2419 	int status = 0;  in get_qam_signal_to_noise()  local
2431 	status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power);  in get_qam_signal_to_noise()
2432 	if (status < 0) {  in get_qam_signal_to_noise()
2433 		pr_err("Error %d on %s\n", status, __func__);  in get_qam_signal_to_noise()
2462 	return status;  in get_qam_signal_to_noise()
2468 	int status;  in get_dvbt_signal_to_noise()  local
2485 	status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A,  in get_dvbt_signal_to_noise()
2487 	if (status < 0)  in get_dvbt_signal_to_noise()
2489 	status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A,  in get_dvbt_signal_to_noise()
2491 	if (status < 0)  in get_dvbt_signal_to_noise()
2493 	status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A,  in get_dvbt_signal_to_noise()
2495 	if (status < 0)  in get_dvbt_signal_to_noise()
2497 	status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A,  in get_dvbt_signal_to_noise()
2499 	if (status < 0)  in get_dvbt_signal_to_noise()
2507 	status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, &reg_data);  in get_dvbt_signal_to_noise()
2508 	if (status < 0)  in get_dvbt_signal_to_noise()
2516 	status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A,  in get_dvbt_signal_to_noise()
2518 	if (status < 0)  in get_dvbt_signal_to_noise()
2564 	if (status < 0)  in get_dvbt_signal_to_noise()
2565 		pr_err("Error %d on %s\n", status, __func__);  in get_dvbt_signal_to_noise()
2566 	return status;  in get_dvbt_signal_to_noise()
2590 	int status = 0;
2621 		status = get_dvbt_signal_to_noise(state, &signal_to_noise);
2622 		if (status < 0)
2624 		status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
2626 		if (status < 0)
2630 		status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
2632 		if (status < 0)
2656 	int status = 0;
2666 		status = get_qam_signal_to_noise(state, &signal_to_noise);
2667 		if (status < 0)
2698 	return status;
2733 	int status = -EINVAL;  in ConfigureI2CBridge()  local
2745 	status = write16(state, SIO_HI_RA_RAM_PAR_1__A,  in ConfigureI2CBridge()
2747 	if (status < 0)  in ConfigureI2CBridge()
2750 		status = write16(state, SIO_HI_RA_RAM_PAR_2__A,  in ConfigureI2CBridge()
2752 		if (status < 0)  in ConfigureI2CBridge()
2755 		status = write16(state, SIO_HI_RA_RAM_PAR_2__A,  in ConfigureI2CBridge()
2757 		if (status < 0)  in ConfigureI2CBridge()
2761 	status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL);  in ConfigureI2CBridge()
2764 	if (status < 0)  in ConfigureI2CBridge()
2765 		pr_err("Error %d on %s\n", status, __func__);  in ConfigureI2CBridge()
2766 	return status;  in ConfigureI2CBridge()
2772 	int status = -EINVAL;  in set_pre_saw()  local
2780 	status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference);  in set_pre_saw()
2782 	if (status < 0)  in set_pre_saw()
2783 		pr_err("Error %d on %s\n", status, __func__);  in set_pre_saw()
2784 	return status;  in set_pre_saw()
2793 	int status;  in bl_direct_cmd()  local
2799 	status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);  in bl_direct_cmd()
2800 	if (status < 0)  in bl_direct_cmd()
2802 	status = write16(state, SIO_BL_TGT_HDR__A, blockbank);  in bl_direct_cmd()
2803 	if (status < 0)  in bl_direct_cmd()
2805 	status = write16(state, SIO_BL_TGT_ADDR__A, offset);  in bl_direct_cmd()
2806 	if (status < 0)  in bl_direct_cmd()
2808 	status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset);  in bl_direct_cmd()
2809 	if (status < 0)  in bl_direct_cmd()
2811 	status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements);  in bl_direct_cmd()
2812 	if (status < 0)  in bl_direct_cmd()
2814 	status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);  in bl_direct_cmd()
2815 	if (status < 0)  in bl_direct_cmd()
2820 		status = read16(state, SIO_BL_STATUS__A, &bl_status);  in bl_direct_cmd()
2821 		if (status < 0)  in bl_direct_cmd()
2826 		status = -EINVAL;  in bl_direct_cmd()
2830 	if (status < 0)  in bl_direct_cmd()
2831 		pr_err("Error %d on %s\n", status, __func__);  in bl_direct_cmd()
2834 	return status;  in bl_direct_cmd()
2841 	int status;  in adc_sync_measurement()  local
2846 	status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);  in adc_sync_measurement()
2847 	if (status < 0)  in adc_sync_measurement()
2849 	status = write16(state, IQM_AF_START_LOCK__A, 1);  in adc_sync_measurement()
2850 	if (status < 0)  in adc_sync_measurement()
2854 	status = read16(state, IQM_AF_PHASE0__A, &data);  in adc_sync_measurement()
2855 	if (status < 0)  in adc_sync_measurement()
2859 	status = read16(state, IQM_AF_PHASE1__A, &data);  in adc_sync_measurement()
2860 	if (status < 0)  in adc_sync_measurement()
2864 	status = read16(state, IQM_AF_PHASE2__A, &data);  in adc_sync_measurement()
2865 	if (status < 0)  in adc_sync_measurement()
2871 	if (status < 0)  in adc_sync_measurement()
2872 		pr_err("Error %d on %s\n", status, __func__);  in adc_sync_measurement()
2873 	return status;  in adc_sync_measurement()
2879 	int status;  in adc_synchronization()  local
2883 	status = adc_sync_measurement(state, &count);  in adc_synchronization()
2884 	if (status < 0)  in adc_synchronization()
2891 		status = read16(state, IQM_AF_CLKNEG__A, &clk_neg);  in adc_synchronization()
2892 		if (status < 0)  in adc_synchronization()
2904 		status = write16(state, IQM_AF_CLKNEG__A, clk_neg);  in adc_synchronization()
2905 		if (status < 0)  in adc_synchronization()
2907 		status = adc_sync_measurement(state, &count);  in adc_synchronization()
2908 		if (status < 0)  in adc_synchronization()
2913 		status = -EINVAL;  in adc_synchronization()
2915 	if (status < 0)  in adc_synchronization()
2916 		pr_err("Error %d on %s\n", status, __func__);  in adc_synchronization()
2917 	return status;  in adc_synchronization()
2930 	int status;  in set_frequency_shifter()  local
2979 	status = write32(state, IQM_FS_RATE_OFS_LO__A,  in set_frequency_shifter()
2981 	if (status < 0)  in set_frequency_shifter()
2982 		pr_err("Error %d on %s\n", status, __func__);  in set_frequency_shifter()
2983 	return status;  in set_frequency_shifter()
3005 	int status = 0;  in init_agc()  local
3038 	status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,  in init_agc()
3040 	if (status < 0)  in init_agc()
3043 	status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode);  in init_agc()
3044 	if (status < 0)  in init_agc()
3046 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt);  in init_agc()
3047 	if (status < 0)  in init_agc()
3049 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min);  in init_agc()
3050 	if (status < 0)  in init_agc()
3052 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max);  in init_agc()
3053 	if (status < 0)  in init_agc()
3055 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,  in init_agc()
3057 	if (status < 0)  in init_agc()
3059 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,  in init_agc()
3061 	if (status < 0)  in init_agc()
3063 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);  in init_agc()
3064 	if (status < 0)  in init_agc()
3066 	status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);  in init_agc()
3067 	if (status < 0)  in init_agc()
3069 	status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);  in init_agc()
3070 	if (status < 0)  in init_agc()
3072 	status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);  in init_agc()
3073 	if (status < 0)  in init_agc()
3075 	status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max);  in init_agc()
3076 	if (status < 0)  in init_agc()
3078 	status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max);  in init_agc()
3079 	if (status < 0)  in init_agc()
3082 	status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A,  in init_agc()
3084 	if (status < 0)  in init_agc()
3086 	status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A,  in init_agc()
3088 	if (status < 0)  in init_agc()
3090 	status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen);  in init_agc()
3091 	if (status < 0)  in init_agc()
3094 	status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);  in init_agc()
3095 	if (status < 0)  in init_agc()
3097 	status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);  in init_agc()
3098 	if (status < 0)  in init_agc()
3100 	status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);  in init_agc()
3101 	if (status < 0)  in init_agc()
3104 	status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);  in init_agc()
3105 	if (status < 0)  in init_agc()
3107 	status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min);  in init_agc()
3108 	if (status < 0)  in init_agc()
3110 	status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min);  in init_agc()
3111 	if (status < 0)  in init_agc()
3113 	status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to);  in init_agc()
3114 	if (status < 0)  in init_agc()
3116 	status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to);  in init_agc()
3117 	if (status < 0)  in init_agc()
3119 	status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);  in init_agc()
3120 	if (status < 0)  in init_agc()
3122 	status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);  in init_agc()
3123 	if (status < 0)  in init_agc()
3125 	status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);  in init_agc()
3126 	if (status < 0)  in init_agc()
3128 	status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);  in init_agc()
3129 	if (status < 0)  in init_agc()
3131 	status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);  in init_agc()
3132 	if (status < 0)  in init_agc()
3134 	status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);  in init_agc()
3135 	if (status < 0)  in init_agc()
3137 	status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);  in init_agc()
3138 	if (status < 0)  in init_agc()
3140 	status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);  in init_agc()
3141 	if (status < 0)  in init_agc()
3143 	status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);  in init_agc()
3144 	if (status < 0)  in init_agc()
3146 	status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);  in init_agc()
3147 	if (status < 0)  in init_agc()
3149 	status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);  in init_agc()
3150 	if (status < 0)  in init_agc()
3152 	status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);  in init_agc()
3153 	if (status < 0)  in init_agc()
3155 	status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);  in init_agc()
3156 	if (status < 0)  in init_agc()
3158 	status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);  in init_agc()
3159 	if (status < 0)  in init_agc()
3163 	status = read16(state, SCU_RAM_AGC_KI__A, &data);  in init_agc()
3164 	if (status < 0)  in init_agc()
3173 	status = write16(state, SCU_RAM_AGC_KI__A, data);  in init_agc()
3175 	if (status < 0)  in init_agc()
3176 		pr_err("Error %d on %s\n", status, __func__);  in init_agc()
3177 	return status;  in init_agc()
3182 	int status;  in dvbtqam_get_acc_pkt_err()  local
3186 		status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);  in dvbtqam_get_acc_pkt_err()
3188 		status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A,  in dvbtqam_get_acc_pkt_err()
3190 	if (status < 0)  in dvbtqam_get_acc_pkt_err()
3191 		pr_err("Error %d on %s\n", status, __func__);  in dvbtqam_get_acc_pkt_err()
3192 	return status;  in dvbtqam_get_acc_pkt_err()
3204 	int status;  in dvbt_sc_command()  local
3207 	status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec);  in dvbt_sc_command()
3210 		status = -EINVAL;  in dvbt_sc_command()
3212 	if (status < 0)  in dvbt_sc_command()
3219 		status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);  in dvbt_sc_command()
3222 	if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))  in dvbt_sc_command()
3231 		status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);  in dvbt_sc_command()
3232 		if (status < 0)  in dvbt_sc_command()
3241 	status = 0;  in dvbt_sc_command()
3250 		status |= write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);  in dvbt_sc_command()
3254 		status |= write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);  in dvbt_sc_command()
3259 		status |= write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);  in dvbt_sc_command()
3263 		status = -EINVAL;  in dvbt_sc_command()
3265 	if (status < 0)  in dvbt_sc_command()
3272 		status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);  in dvbt_sc_command()
3275 	if (retry_cnt >= DRXK_MAX_RETRIES && (status < 0))  in dvbt_sc_command()
3279 	status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code);  in dvbt_sc_command()
3282 		status = -EINVAL;  in dvbt_sc_command()
3284 	if (status < 0)  in dvbt_sc_command()
3296 		status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));  in dvbt_sc_command()
3307 		status = -EINVAL;  in dvbt_sc_command()
3311 	if (status < 0)  in dvbt_sc_command()
3312 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_sc_command()
3313 	return status;  in dvbt_sc_command()
3319 	int status;  in power_up_dvbt()  local
3322 	status = ctrl_power_mode(state, &power_mode);  in power_up_dvbt()
3323 	if (status < 0)  in power_up_dvbt()
3324 		pr_err("Error %d on %s\n", status, __func__);  in power_up_dvbt()
3325 	return status;  in power_up_dvbt()
3330 	int status;  in dvbt_ctrl_set_inc_enable()  local
3334 		status = write16(state, IQM_CF_BYPASSDET__A, 0);  in dvbt_ctrl_set_inc_enable()
3336 		status = write16(state, IQM_CF_BYPASSDET__A, 1);  in dvbt_ctrl_set_inc_enable()
3337 	if (status < 0)  in dvbt_ctrl_set_inc_enable()
3338 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_ctrl_set_inc_enable()
3339 	return status;  in dvbt_ctrl_set_inc_enable()
3346 	int status;  in dvbt_ctrl_set_fr_enable()  local
3351 		status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,  in dvbt_ctrl_set_fr_enable()
3355 		status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);  in dvbt_ctrl_set_fr_enable()
3357 	if (status < 0)  in dvbt_ctrl_set_fr_enable()
3358 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_ctrl_set_fr_enable()
3360 	return status;  in dvbt_ctrl_set_fr_enable()
3367 	int status;  in dvbt_ctrl_set_echo_threshold()  local
3370 	status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);  in dvbt_ctrl_set_echo_threshold()
3371 	if (status < 0)  in dvbt_ctrl_set_echo_threshold()
3391 	status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);  in dvbt_ctrl_set_echo_threshold()
3393 	if (status < 0)  in dvbt_ctrl_set_echo_threshold()
3394 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_ctrl_set_echo_threshold()
3395 	return status;  in dvbt_ctrl_set_echo_threshold()
3401 	int status = -EINVAL;  in dvbt_ctrl_set_sqi_speed()  local
3413 	status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,  in dvbt_ctrl_set_sqi_speed()
3416 	if (status < 0)  in dvbt_ctrl_set_sqi_speed()
3417 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_ctrl_set_sqi_speed()
3418 	return status;  in dvbt_ctrl_set_sqi_speed()
3433 	int status;  in dvbt_activate_presets()  local
3441 	status = dvbt_ctrl_set_inc_enable(state, &setincenable);  in dvbt_activate_presets()
3442 	if (status < 0)  in dvbt_activate_presets()
3444 	status = dvbt_ctrl_set_fr_enable(state, &setfrenable);  in dvbt_activate_presets()
3445 	if (status < 0)  in dvbt_activate_presets()
3447 	status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k);  in dvbt_activate_presets()
3448 	if (status < 0)  in dvbt_activate_presets()
3450 	status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k);  in dvbt_activate_presets()
3451 	if (status < 0)  in dvbt_activate_presets()
3453 	status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,  in dvbt_activate_presets()
3456 	if (status < 0)  in dvbt_activate_presets()
3457 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_activate_presets()
3458 	return status;  in dvbt_activate_presets()
3476 	int status;  in set_dvbt_standard()  local
3484 	status = scu_command(state,  in set_dvbt_standard()
3488 	if (status < 0)  in set_dvbt_standard()
3492 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM  in set_dvbt_standard()
3495 	if (status < 0)  in set_dvbt_standard()
3499 	status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);  in set_dvbt_standard()
3500 	if (status < 0)  in set_dvbt_standard()
3502 	status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);  in set_dvbt_standard()
3503 	if (status < 0)  in set_dvbt_standard()
3505 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);  in set_dvbt_standard()
3506 	if (status < 0)  in set_dvbt_standard()
3511 	status = write16(state, IQM_AF_UPD_SEL__A, 1);  in set_dvbt_standard()
3512 	if (status < 0)  in set_dvbt_standard()
3515 	status = write16(state, IQM_AF_CLP_LEN__A, 0);  in set_dvbt_standard()
3516 	if (status < 0)  in set_dvbt_standard()
3519 	status = write16(state, IQM_AF_SNS_LEN__A, 0);  in set_dvbt_standard()
3520 	if (status < 0)  in set_dvbt_standard()
3523 	status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);  in set_dvbt_standard()
3524 	if (status < 0)  in set_dvbt_standard()
3526 	status = set_iqm_af(state, true);  in set_dvbt_standard()
3527 	if (status < 0)  in set_dvbt_standard()
3530 	status = write16(state, IQM_AF_AGC_RF__A, 0);  in set_dvbt_standard()
3531 	if (status < 0)  in set_dvbt_standard()
3535 	status = write16(state, IQM_AF_INC_LCT__A, 0);	/* crunch in IQM_CF */  in set_dvbt_standard()
3536 	if (status < 0)  in set_dvbt_standard()
3538 	status = write16(state, IQM_CF_DET_LCT__A, 0);	/* detect in IQM_CF */  in set_dvbt_standard()
3539 	if (status < 0)  in set_dvbt_standard()
3541 	status = write16(state, IQM_CF_WND_LEN__A, 3);	/* peak detector window length */  in set_dvbt_standard()
3542 	if (status < 0)  in set_dvbt_standard()
3545 	status = write16(state, IQM_RC_STRETCH__A, 16);  in set_dvbt_standard()
3546 	if (status < 0)  in set_dvbt_standard()
3548 	status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */  in set_dvbt_standard()
3549 	if (status < 0)  in set_dvbt_standard()
3551 	status = write16(state, IQM_CF_DS_ENA__A, 0x4);	/* decimate output 2 */  in set_dvbt_standard()
3552 	if (status < 0)  in set_dvbt_standard()
3554 	status = write16(state, IQM_CF_SCALE__A, 1600);  in set_dvbt_standard()
3555 	if (status < 0)  in set_dvbt_standard()
3557 	status = write16(state, IQM_CF_SCALE_SH__A, 0);  in set_dvbt_standard()
3558 	if (status < 0)  in set_dvbt_standard()
3562 	status = write16(state, IQM_AF_CLP_TH__A, 448);  in set_dvbt_standard()
3563 	if (status < 0)  in set_dvbt_standard()
3565 	status = write16(state, IQM_CF_DATATH__A, 495);	/* crunching threshold */  in set_dvbt_standard()
3566 	if (status < 0)  in set_dvbt_standard()
3569 	status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT,  in set_dvbt_standard()
3571 	if (status < 0)  in set_dvbt_standard()
3574 	status = write16(state, IQM_CF_PKDTH__A, 2);	/* peak detector threshold */  in set_dvbt_standard()
3575 	if (status < 0)  in set_dvbt_standard()
3577 	status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);  in set_dvbt_standard()
3578 	if (status < 0)  in set_dvbt_standard()
3581 	status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);  in set_dvbt_standard()
3582 	if (status < 0)  in set_dvbt_standard()
3584 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);  in set_dvbt_standard()
3585 	if (status < 0)  in set_dvbt_standard()
3589 	status = adc_synchronization(state);  in set_dvbt_standard()
3590 	if (status < 0)  in set_dvbt_standard()
3592 	status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg);  in set_dvbt_standard()
3593 	if (status < 0)  in set_dvbt_standard()
3597 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);  in set_dvbt_standard()
3598 	if (status < 0)  in set_dvbt_standard()
3601 	status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true);  in set_dvbt_standard()
3602 	if (status < 0)  in set_dvbt_standard()
3604 	status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true);  in set_dvbt_standard()
3605 	if (status < 0)  in set_dvbt_standard()
3609 	status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);  in set_dvbt_standard()
3610 	if (status < 0)  in set_dvbt_standard()
3613 	status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);  in set_dvbt_standard()
3614 	if (status < 0)  in set_dvbt_standard()
3618 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in set_dvbt_standard()
3619 	if (status < 0)  in set_dvbt_standard()
3624 		status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,  in set_dvbt_standard()
3626 		if (status < 0)  in set_dvbt_standard()
3632 	status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);  in set_dvbt_standard()
3633 	if (status < 0)  in set_dvbt_standard()
3635 	status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);  in set_dvbt_standard()
3636 	if (status < 0)  in set_dvbt_standard()
3641 	status = write16(state, FEC_DI_INPUT_CTL__A, 1);	/* OFDM input */  in set_dvbt_standard()
3642 	if (status < 0)  in set_dvbt_standard()
3647 	status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);  in set_dvbt_standard()
3648 	if (status < 0)  in set_dvbt_standard()
3651 	status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);  in set_dvbt_standard()
3652 	if (status < 0)  in set_dvbt_standard()
3655 	status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);  in set_dvbt_standard()
3656 	if (status < 0)  in set_dvbt_standard()
3660 	status = mpegts_dto_setup(state, OM_DVBT);  in set_dvbt_standard()
3661 	if (status < 0)  in set_dvbt_standard()
3664 	status = dvbt_activate_presets(state);  in set_dvbt_standard()
3665 	if (status < 0)  in set_dvbt_standard()
3669 	if (status < 0)  in set_dvbt_standard()
3670 		pr_err("Error %d on %s\n", status, __func__);  in set_dvbt_standard()
3671 	return status;  in set_dvbt_standard()
3683 	int status;  in dvbt_start()  local
3690 	status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0,  in dvbt_start()
3693 	if (status < 0)  in dvbt_start()
3696 	status = mpegts_start(state);  in dvbt_start()
3697 	if (status < 0)  in dvbt_start()
3699 	status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);  in dvbt_start()
3700 	if (status < 0)  in dvbt_start()
3703 	if (status < 0)  in dvbt_start()
3704 		pr_err("Error %d on %s\n", status, __func__);  in dvbt_start()
3705 	return status;  in dvbt_start()
3726 	int status;  in set_dvbt()  local
3731 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM  in set_dvbt()
3734 	if (status < 0)  in set_dvbt()
3738 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);  in set_dvbt()
3739 	if (status < 0)  in set_dvbt()
3743 	status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);  in set_dvbt()
3744 	if (status < 0)  in set_dvbt()
3746 	status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);  in set_dvbt()
3747 	if (status < 0)  in set_dvbt()
3752 	status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);  in set_dvbt()
3753 	if (status < 0)  in set_dvbt()
3845 		status = -EINVAL;  in set_dvbt()
3851 	status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);  in set_dvbt()
3852 	if (status < 0)  in set_dvbt()
3898 		status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,  in set_dvbt()
3900 		if (status < 0)  in set_dvbt()
3903 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,  in set_dvbt()
3905 		if (status < 0)  in set_dvbt()
3907 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,  in set_dvbt()
3909 		if (status < 0)  in set_dvbt()
3911 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,  in set_dvbt()
3913 		if (status < 0)  in set_dvbt()
3915 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,  in set_dvbt()
3917 		if (status < 0)  in set_dvbt()
3922 		status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,  in set_dvbt()
3924 		if (status < 0)  in set_dvbt()
3927 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,  in set_dvbt()
3929 		if (status < 0)  in set_dvbt()
3931 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,  in set_dvbt()
3933 		if (status < 0)  in set_dvbt()
3935 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,  in set_dvbt()
3937 		if (status < 0)  in set_dvbt()
3939 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,  in set_dvbt()
3941 		if (status < 0)  in set_dvbt()
3946 		status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,  in set_dvbt()
3948 		if (status < 0)  in set_dvbt()
3951 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,  in set_dvbt()
3953 		if (status < 0)  in set_dvbt()
3955 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,  in set_dvbt()
3957 		if (status < 0)  in set_dvbt()
3959 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,  in set_dvbt()
3961 		if (status < 0)  in set_dvbt()
3963 		status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,  in set_dvbt()
3965 		if (status < 0)  in set_dvbt()
3969 		status = -EINVAL;  in set_dvbt()
4000 	status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs);  in set_dvbt()
4001 	if (status < 0)  in set_dvbt()
4007 	status = dvbt_set_frequency_shift(demod, channel, tuner_offset);  in set_dvbt()
4008 	if (status < 0)  in set_dvbt()
4011 	status = set_frequency_shifter(state, intermediate_freqk_hz,  in set_dvbt()
4013 	if (status < 0)  in set_dvbt()
4019 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in set_dvbt()
4020 	if (status < 0)  in set_dvbt()
4024 	status = write16(state, OFDM_SC_COMM_STATE__A, 0);  in set_dvbt()
4025 	if (status < 0)  in set_dvbt()
4027 	status = write16(state, OFDM_SC_COMM_EXEC__A, 1);  in set_dvbt()
4028 	if (status < 0)  in set_dvbt()
4032 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM  in set_dvbt()
4035 	if (status < 0)  in set_dvbt()
4044 	status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,  in set_dvbt()
4046 	if (status < 0)  in set_dvbt()
4050 		status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed);  in set_dvbt()
4052 	if (status < 0)  in set_dvbt()
4053 		pr_err("Error %d on %s\n", status, __func__);  in set_dvbt()
4055 	return status;  in set_dvbt()
4062 * \brief Retrieve lock status .
4064 * \param lockStat Pointer to lock status structure.
4070 	int status;  in get_dvbt_lock_status()  local
4084 	status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec);  in get_dvbt_lock_status()
4085 	if (status < 0)  in get_dvbt_lock_status()
4090 	status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock);  in get_dvbt_lock_status()
4091 	if (status < 0)  in get_dvbt_lock_status()
4103 	if (status < 0)  in get_dvbt_lock_status()
4104 		pr_err("Error %d on %s\n", status, __func__);  in get_dvbt_lock_status()
4106 	return status;  in get_dvbt_lock_status()
4112 	int status;  in power_up_qam()  local
4115 	status = ctrl_power_mode(state, &power_mode);  in power_up_qam()
4116 	if (status < 0)  in power_up_qam()
4117 		pr_err("Error %d on %s\n", status, __func__);  in power_up_qam()
4119 	return status;  in power_up_qam()
4128 	int status = 0;  in power_down_qam()  local
4131 	status = read16(state, SCU_COMM_EXEC__A, &data);  in power_down_qam()
4132 	if (status < 0)  in power_down_qam()
4140 		status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);  in power_down_qam()
4141 		if (status < 0)  in power_down_qam()
4143 		status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM  in power_down_qam()
4146 		if (status < 0)  in power_down_qam()
4150 	status = set_iqm_af(state, false);  in power_down_qam()
4153 	if (status < 0)  in power_down_qam()
4154 		pr_err("Error %d on %s\n", status, __func__);  in power_down_qam()
4156 	return status;  in power_down_qam()
4180 	int status = 0;  in set_qam_measurement()  local
4208 		status = -EINVAL;  in set_qam_measurement()
4210 	if (status < 0)  in set_qam_measurement()
4224 		status = -EINVAL;  in set_qam_measurement()
4225 		if (status < 0)  in set_qam_measurement()
4233 	status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period);  in set_qam_measurement()
4234 	if (status < 0)  in set_qam_measurement()
4236 	status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A,  in set_qam_measurement()
4238 	if (status < 0)  in set_qam_measurement()
4240 	status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period);  in set_qam_measurement()
4242 	if (status < 0)  in set_qam_measurement()
4243 		pr_err("Error %d on %s\n", status, __func__);  in set_qam_measurement()
4244 	return status;  in set_qam_measurement()
4249 	int status = 0;  in set_qam16()  local
4254 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);  in set_qam16()
4255 	if (status < 0)  in set_qam16()
4257 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);  in set_qam16()
4258 	if (status < 0)  in set_qam16()
4260 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);  in set_qam16()
4261 	if (status < 0)  in set_qam16()
4263 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);  in set_qam16()
4264 	if (status < 0)  in set_qam16()
4266 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);  in set_qam16()
4267 	if (status < 0)  in set_qam16()
4269 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);  in set_qam16()
4270 	if (status < 0)  in set_qam16()
4273 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);  in set_qam16()
4274 	if (status < 0)  in set_qam16()
4276 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);  in set_qam16()
4277 	if (status < 0)  in set_qam16()
4279 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);  in set_qam16()
4280 	if (status < 0)  in set_qam16()
4282 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);  in set_qam16()
4283 	if (status < 0)  in set_qam16()
4285 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);  in set_qam16()
4286 	if (status < 0)  in set_qam16()
4288 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam16()
4289 	if (status < 0)  in set_qam16()
4292 	status = write16(state, QAM_SY_SYNC_HWM__A, 5);  in set_qam16()
4293 	if (status < 0)  in set_qam16()
4295 	status = write16(state, QAM_SY_SYNC_AWM__A, 4);  in set_qam16()
4296 	if (status < 0)  in set_qam16()
4298 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam16()
4299 	if (status < 0)  in set_qam16()
4303 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam16()
4305 	if (status < 0)  in set_qam16()
4309 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam16()
4310 	if (status < 0)  in set_qam16()
4312 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam16()
4313 	if (status < 0)  in set_qam16()
4315 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam16()
4316 	if (status < 0)  in set_qam16()
4318 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam16()
4319 	if (status < 0)  in set_qam16()
4321 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam16()
4322 	if (status < 0)  in set_qam16()
4324 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam16()
4325 	if (status < 0)  in set_qam16()
4327 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam16()
4328 	if (status < 0)  in set_qam16()
4330 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam16()
4331 	if (status < 0)  in set_qam16()
4334 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam16()
4335 	if (status < 0)  in set_qam16()
4337 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);  in set_qam16()
4338 	if (status < 0)  in set_qam16()
4340 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);  in set_qam16()
4341 	if (status < 0)  in set_qam16()
4343 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam16()
4344 	if (status < 0)  in set_qam16()
4346 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);  in set_qam16()
4347 	if (status < 0)  in set_qam16()
4349 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);  in set_qam16()
4350 	if (status < 0)  in set_qam16()
4352 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam16()
4353 	if (status < 0)  in set_qam16()
4355 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);  in set_qam16()
4356 	if (status < 0)  in set_qam16()
4358 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);  in set_qam16()
4359 	if (status < 0)  in set_qam16()
4361 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam16()
4362 	if (status < 0)  in set_qam16()
4364 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam16()
4365 	if (status < 0)  in set_qam16()
4367 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);  in set_qam16()
4368 	if (status < 0)  in set_qam16()
4374 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);  in set_qam16()
4375 	if (status < 0)  in set_qam16()
4377 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);  in set_qam16()
4378 	if (status < 0)  in set_qam16()
4380 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);  in set_qam16()
4381 	if (status < 0)  in set_qam16()
4383 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);  in set_qam16()
4384 	if (status < 0)  in set_qam16()
4386 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);  in set_qam16()
4387 	if (status < 0)  in set_qam16()
4389 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);  in set_qam16()
4390 	if (status < 0)  in set_qam16()
4393 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam16()
4394 	if (status < 0)  in set_qam16()
4396 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);  in set_qam16()
4397 	if (status < 0)  in set_qam16()
4399 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);  in set_qam16()
4400 	if (status < 0)  in set_qam16()
4406 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);  in set_qam16()
4407 	if (status < 0)  in set_qam16()
4409 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);  in set_qam16()
4410 	if (status < 0)  in set_qam16()
4412 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);  in set_qam16()
4413 	if (status < 0)  in set_qam16()
4415 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);  in set_qam16()
4416 	if (status < 0)  in set_qam16()
4418 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);  in set_qam16()
4419 	if (status < 0)  in set_qam16()
4421 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);  in set_qam16()
4422 	if (status < 0)  in set_qam16()
4424 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);  in set_qam16()
4425 	if (status < 0)  in set_qam16()
4429 	if (status < 0)  in set_qam16()
4430 		pr_err("Error %d on %s\n", status, __func__);  in set_qam16()
4431 	return status;  in set_qam16()
4443 	int status = 0;  in set_qam32()  local
4449 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);  in set_qam32()
4450 	if (status < 0)  in set_qam32()
4452 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);  in set_qam32()
4453 	if (status < 0)  in set_qam32()
4455 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);  in set_qam32()
4456 	if (status < 0)  in set_qam32()
4458 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);  in set_qam32()
4459 	if (status < 0)  in set_qam32()
4461 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);  in set_qam32()
4462 	if (status < 0)  in set_qam32()
4464 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);  in set_qam32()
4465 	if (status < 0)  in set_qam32()
4469 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);  in set_qam32()
4470 	if (status < 0)  in set_qam32()
4472 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);  in set_qam32()
4473 	if (status < 0)  in set_qam32()
4475 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);  in set_qam32()
4476 	if (status < 0)  in set_qam32()
4478 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);  in set_qam32()
4479 	if (status < 0)  in set_qam32()
4481 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);  in set_qam32()
4482 	if (status < 0)  in set_qam32()
4484 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam32()
4485 	if (status < 0)  in set_qam32()
4488 	status = write16(state, QAM_SY_SYNC_HWM__A, 6);  in set_qam32()
4489 	if (status < 0)  in set_qam32()
4491 	status = write16(state, QAM_SY_SYNC_AWM__A, 5);  in set_qam32()
4492 	if (status < 0)  in set_qam32()
4494 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam32()
4495 	if (status < 0)  in set_qam32()
4500 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam32()
4502 	if (status < 0)  in set_qam32()
4508 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam32()
4509 	if (status < 0)  in set_qam32()
4511 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam32()
4512 	if (status < 0)  in set_qam32()
4514 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam32()
4515 	if (status < 0)  in set_qam32()
4517 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam32()
4518 	if (status < 0)  in set_qam32()
4520 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam32()
4521 	if (status < 0)  in set_qam32()
4523 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam32()
4524 	if (status < 0)  in set_qam32()
4526 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam32()
4527 	if (status < 0)  in set_qam32()
4529 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam32()
4530 	if (status < 0)  in set_qam32()
4533 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam32()
4534 	if (status < 0)  in set_qam32()
4536 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);  in set_qam32()
4537 	if (status < 0)  in set_qam32()
4539 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);  in set_qam32()
4540 	if (status < 0)  in set_qam32()
4542 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam32()
4543 	if (status < 0)  in set_qam32()
4545 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);  in set_qam32()
4546 	if (status < 0)  in set_qam32()
4548 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);  in set_qam32()
4549 	if (status < 0)  in set_qam32()
4551 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam32()
4552 	if (status < 0)  in set_qam32()
4554 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);  in set_qam32()
4555 	if (status < 0)  in set_qam32()
4557 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);  in set_qam32()
4558 	if (status < 0)  in set_qam32()
4560 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam32()
4561 	if (status < 0)  in set_qam32()
4563 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam32()
4564 	if (status < 0)  in set_qam32()
4566 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);  in set_qam32()
4567 	if (status < 0)  in set_qam32()
4573 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);  in set_qam32()
4574 	if (status < 0)  in set_qam32()
4576 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);  in set_qam32()
4577 	if (status < 0)  in set_qam32()
4579 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);  in set_qam32()
4580 	if (status < 0)  in set_qam32()
4582 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);  in set_qam32()
4583 	if (status < 0)  in set_qam32()
4585 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);  in set_qam32()
4586 	if (status < 0)  in set_qam32()
4588 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);  in set_qam32()
4589 	if (status < 0)  in set_qam32()
4592 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam32()
4593 	if (status < 0)  in set_qam32()
4595 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);  in set_qam32()
4596 	if (status < 0)  in set_qam32()
4598 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);  in set_qam32()
4599 	if (status < 0)  in set_qam32()
4605 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);  in set_qam32()
4606 	if (status < 0)  in set_qam32()
4608 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);  in set_qam32()
4609 	if (status < 0)  in set_qam32()
4611 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);  in set_qam32()
4612 	if (status < 0)  in set_qam32()
4614 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);  in set_qam32()
4615 	if (status < 0)  in set_qam32()
4617 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);  in set_qam32()
4618 	if (status < 0)  in set_qam32()
4620 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);  in set_qam32()
4621 	if (status < 0)  in set_qam32()
4623 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);  in set_qam32()
4625 	if (status < 0)  in set_qam32()
4626 		pr_err("Error %d on %s\n", status, __func__);  in set_qam32()
4627 	return status;  in set_qam32()
4639 	int status = 0;  in set_qam64()  local
4644 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);  in set_qam64()
4645 	if (status < 0)  in set_qam64()
4647 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);  in set_qam64()
4648 	if (status < 0)  in set_qam64()
4650 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);  in set_qam64()
4651 	if (status < 0)  in set_qam64()
4653 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);  in set_qam64()
4654 	if (status < 0)  in set_qam64()
4656 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);  in set_qam64()
4657 	if (status < 0)  in set_qam64()
4659 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);  in set_qam64()
4660 	if (status < 0)  in set_qam64()
4664 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);  in set_qam64()
4665 	if (status < 0)  in set_qam64()
4667 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);  in set_qam64()
4668 	if (status < 0)  in set_qam64()
4670 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);  in set_qam64()
4671 	if (status < 0)  in set_qam64()
4673 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);  in set_qam64()
4674 	if (status < 0)  in set_qam64()
4676 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);  in set_qam64()
4677 	if (status < 0)  in set_qam64()
4679 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam64()
4680 	if (status < 0)  in set_qam64()
4683 	status = write16(state, QAM_SY_SYNC_HWM__A, 5);  in set_qam64()
4684 	if (status < 0)  in set_qam64()
4686 	status = write16(state, QAM_SY_SYNC_AWM__A, 4);  in set_qam64()
4687 	if (status < 0)  in set_qam64()
4689 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam64()
4690 	if (status < 0)  in set_qam64()
4694 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam64()
4696 	if (status < 0)  in set_qam64()
4702 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam64()
4703 	if (status < 0)  in set_qam64()
4705 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam64()
4706 	if (status < 0)  in set_qam64()
4708 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam64()
4709 	if (status < 0)  in set_qam64()
4711 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam64()
4712 	if (status < 0)  in set_qam64()
4714 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam64()
4715 	if (status < 0)  in set_qam64()
4717 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam64()
4718 	if (status < 0)  in set_qam64()
4720 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam64()
4721 	if (status < 0)  in set_qam64()
4723 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam64()
4724 	if (status < 0)  in set_qam64()
4727 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam64()
4728 	if (status < 0)  in set_qam64()
4730 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);  in set_qam64()
4731 	if (status < 0)  in set_qam64()
4733 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);  in set_qam64()
4734 	if (status < 0)  in set_qam64()
4736 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam64()
4737 	if (status < 0)  in set_qam64()
4739 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);  in set_qam64()
4740 	if (status < 0)  in set_qam64()
4742 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);  in set_qam64()
4743 	if (status < 0)  in set_qam64()
4745 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam64()
4746 	if (status < 0)  in set_qam64()
4748 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);  in set_qam64()
4749 	if (status < 0)  in set_qam64()
4751 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);  in set_qam64()
4752 	if (status < 0)  in set_qam64()
4754 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam64()
4755 	if (status < 0)  in set_qam64()
4757 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam64()
4758 	if (status < 0)  in set_qam64()
4760 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);  in set_qam64()
4761 	if (status < 0)  in set_qam64()
4767 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);  in set_qam64()
4768 	if (status < 0)  in set_qam64()
4770 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);  in set_qam64()
4771 	if (status < 0)  in set_qam64()
4773 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);  in set_qam64()
4774 	if (status < 0)  in set_qam64()
4776 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);  in set_qam64()
4777 	if (status < 0)  in set_qam64()
4779 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);  in set_qam64()
4780 	if (status < 0)  in set_qam64()
4782 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);  in set_qam64()
4783 	if (status < 0)  in set_qam64()
4786 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam64()
4787 	if (status < 0)  in set_qam64()
4789 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);  in set_qam64()
4790 	if (status < 0)  in set_qam64()
4792 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);  in set_qam64()
4793 	if (status < 0)  in set_qam64()
4799 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);  in set_qam64()
4800 	if (status < 0)  in set_qam64()
4802 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);  in set_qam64()
4803 	if (status < 0)  in set_qam64()
4805 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);  in set_qam64()
4806 	if (status < 0)  in set_qam64()
4808 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);  in set_qam64()
4809 	if (status < 0)  in set_qam64()
4811 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);  in set_qam64()
4812 	if (status < 0)  in set_qam64()
4814 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);  in set_qam64()
4815 	if (status < 0)  in set_qam64()
4817 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);  in set_qam64()
4819 	if (status < 0)  in set_qam64()
4820 		pr_err("Error %d on %s\n", status, __func__);  in set_qam64()
4822 	return status;  in set_qam64()
4834 	int status = 0;  in set_qam128()  local
4839 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);  in set_qam128()
4840 	if (status < 0)  in set_qam128()
4842 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);  in set_qam128()
4843 	if (status < 0)  in set_qam128()
4845 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);  in set_qam128()
4846 	if (status < 0)  in set_qam128()
4848 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);  in set_qam128()
4849 	if (status < 0)  in set_qam128()
4851 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);  in set_qam128()
4852 	if (status < 0)  in set_qam128()
4854 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);  in set_qam128()
4855 	if (status < 0)  in set_qam128()
4859 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);  in set_qam128()
4860 	if (status < 0)  in set_qam128()
4862 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);  in set_qam128()
4863 	if (status < 0)  in set_qam128()
4865 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);  in set_qam128()
4866 	if (status < 0)  in set_qam128()
4868 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);  in set_qam128()
4869 	if (status < 0)  in set_qam128()
4871 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);  in set_qam128()
4872 	if (status < 0)  in set_qam128()
4874 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam128()
4875 	if (status < 0)  in set_qam128()
4878 	status = write16(state, QAM_SY_SYNC_HWM__A, 6);  in set_qam128()
4879 	if (status < 0)  in set_qam128()
4881 	status = write16(state, QAM_SY_SYNC_AWM__A, 5);  in set_qam128()
4882 	if (status < 0)  in set_qam128()
4884 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam128()
4885 	if (status < 0)  in set_qam128()
4891 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam128()
4893 	if (status < 0)  in set_qam128()
4899 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam128()
4900 	if (status < 0)  in set_qam128()
4902 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam128()
4903 	if (status < 0)  in set_qam128()
4905 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam128()
4906 	if (status < 0)  in set_qam128()
4908 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam128()
4909 	if (status < 0)  in set_qam128()
4911 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam128()
4912 	if (status < 0)  in set_qam128()
4914 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam128()
4915 	if (status < 0)  in set_qam128()
4917 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam128()
4918 	if (status < 0)  in set_qam128()
4920 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam128()
4921 	if (status < 0)  in set_qam128()
4924 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam128()
4925 	if (status < 0)  in set_qam128()
4927 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);  in set_qam128()
4928 	if (status < 0)  in set_qam128()
4930 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);  in set_qam128()
4931 	if (status < 0)  in set_qam128()
4933 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam128()
4934 	if (status < 0)  in set_qam128()
4936 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);  in set_qam128()
4937 	if (status < 0)  in set_qam128()
4939 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);  in set_qam128()
4940 	if (status < 0)  in set_qam128()
4942 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam128()
4943 	if (status < 0)  in set_qam128()
4945 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);  in set_qam128()
4946 	if (status < 0)  in set_qam128()
4948 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);  in set_qam128()
4949 	if (status < 0)  in set_qam128()
4951 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam128()
4952 	if (status < 0)  in set_qam128()
4954 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam128()
4955 	if (status < 0)  in set_qam128()
4957 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);  in set_qam128()
4958 	if (status < 0)  in set_qam128()
4964 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);  in set_qam128()
4965 	if (status < 0)  in set_qam128()
4967 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);  in set_qam128()
4968 	if (status < 0)  in set_qam128()
4970 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);  in set_qam128()
4971 	if (status < 0)  in set_qam128()
4973 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);  in set_qam128()
4974 	if (status < 0)  in set_qam128()
4976 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);  in set_qam128()
4977 	if (status < 0)  in set_qam128()
4979 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);  in set_qam128()
4980 	if (status < 0)  in set_qam128()
4983 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam128()
4984 	if (status < 0)  in set_qam128()
4986 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);  in set_qam128()
4987 	if (status < 0)  in set_qam128()
4990 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);  in set_qam128()
4991 	if (status < 0)  in set_qam128()
4996 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);  in set_qam128()
4997 	if (status < 0)  in set_qam128()
4999 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);  in set_qam128()
5000 	if (status < 0)  in set_qam128()
5002 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);  in set_qam128()
5003 	if (status < 0)  in set_qam128()
5005 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);  in set_qam128()
5006 	if (status < 0)  in set_qam128()
5008 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);  in set_qam128()
5009 	if (status < 0)  in set_qam128()
5011 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);  in set_qam128()
5012 	if (status < 0)  in set_qam128()
5014 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);  in set_qam128()
5016 	if (status < 0)  in set_qam128()
5017 		pr_err("Error %d on %s\n", status, __func__);  in set_qam128()
5019 	return status;  in set_qam128()
5031 	int status = 0;  in set_qam256()  local
5036 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);  in set_qam256()
5037 	if (status < 0)  in set_qam256()
5039 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);  in set_qam256()
5040 	if (status < 0)  in set_qam256()
5042 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);  in set_qam256()
5043 	if (status < 0)  in set_qam256()
5045 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);  in set_qam256()
5046 	if (status < 0)  in set_qam256()
5048 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);  in set_qam256()
5049 	if (status < 0)  in set_qam256()
5051 	status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);  in set_qam256()
5052 	if (status < 0)  in set_qam256()
5056 	status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);  in set_qam256()
5057 	if (status < 0)  in set_qam256()
5059 	status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);  in set_qam256()
5060 	if (status < 0)  in set_qam256()
5062 	status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);  in set_qam256()
5063 	if (status < 0)  in set_qam256()
5065 	status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);  in set_qam256()
5066 	if (status < 0)  in set_qam256()
5068 	status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);  in set_qam256()
5069 	if (status < 0)  in set_qam256()
5071 	status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);  in set_qam256()
5072 	if (status < 0)  in set_qam256()
5075 	status = write16(state, QAM_SY_SYNC_HWM__A, 5);  in set_qam256()
5076 	if (status < 0)  in set_qam256()
5078 	status = write16(state, QAM_SY_SYNC_AWM__A, 4);  in set_qam256()
5079 	if (status < 0)  in set_qam256()
5081 	status = write16(state, QAM_SY_SYNC_LWM__A, 3);  in set_qam256()
5082 	if (status < 0)  in set_qam256()
5087 	status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,  in set_qam256()
5089 	if (status < 0)  in set_qam256()
5095 	status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);  in set_qam256()
5096 	if (status < 0)  in set_qam256()
5098 	status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);  in set_qam256()
5099 	if (status < 0)  in set_qam256()
5101 	status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);  in set_qam256()
5102 	if (status < 0)  in set_qam256()
5104 	status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);  in set_qam256()
5105 	if (status < 0)  in set_qam256()
5107 	status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);  in set_qam256()
5108 	if (status < 0)  in set_qam256()
5110 	status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);  in set_qam256()
5111 	if (status < 0)  in set_qam256()
5113 	status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);  in set_qam256()
5114 	if (status < 0)  in set_qam256()
5116 	status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);  in set_qam256()
5117 	if (status < 0)  in set_qam256()
5120 	status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);  in set_qam256()
5121 	if (status < 0)  in set_qam256()
5123 	status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);  in set_qam256()
5124 	if (status < 0)  in set_qam256()
5126 	status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);  in set_qam256()
5127 	if (status < 0)  in set_qam256()
5129 	status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);  in set_qam256()
5130 	if (status < 0)  in set_qam256()
5132 	status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);  in set_qam256()
5133 	if (status < 0)  in set_qam256()
5135 	status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);  in set_qam256()
5136 	if (status < 0)  in set_qam256()
5138 	status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);  in set_qam256()
5139 	if (status < 0)  in set_qam256()
5141 	status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);  in set_qam256()
5142 	if (status < 0)  in set_qam256()
5144 	status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);  in set_qam256()
5145 	if (status < 0)  in set_qam256()
5147 	status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);  in set_qam256()
5148 	if (status < 0)  in set_qam256()
5150 	status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);  in set_qam256()
5151 	if (status < 0)  in set_qam256()
5153 	status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);  in set_qam256()
5154 	if (status < 0)  in set_qam256()
5160 	status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);  in set_qam256()
5161 	if (status < 0)  in set_qam256()
5163 	status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);  in set_qam256()
5164 	if (status < 0)  in set_qam256()
5166 	status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);  in set_qam256()
5167 	if (status < 0)  in set_qam256()
5169 	status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);  in set_qam256()
5170 	if (status < 0)  in set_qam256()
5172 	status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);  in set_qam256()
5173 	if (status < 0)  in set_qam256()
5175 	status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);  in set_qam256()
5176 	if (status < 0)  in set_qam256()
5179 	status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);  in set_qam256()
5180 	if (status < 0)  in set_qam256()
5182 	status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);  in set_qam256()
5183 	if (status < 0)  in set_qam256()
5185 	status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);  in set_qam256()
5186 	if (status < 0)  in set_qam256()
5192 	status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);  in set_qam256()
5193 	if (status < 0)  in set_qam256()
5195 	status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);  in set_qam256()
5196 	if (status < 0)  in set_qam256()
5198 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);  in set_qam256()
5199 	if (status < 0)  in set_qam256()
5201 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);  in set_qam256()
5202 	if (status < 0)  in set_qam256()
5204 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);  in set_qam256()
5205 	if (status < 0)  in set_qam256()
5207 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);  in set_qam256()
5208 	if (status < 0)  in set_qam256()
5210 	status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);  in set_qam256()
5212 	if (status < 0)  in set_qam256()
5213 		pr_err("Error %d on %s\n", status, __func__);  in set_qam256()
5214 	return status;  in set_qam256()
5227 	int status;  in qam_reset_qam()  local
5232 	status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);  in qam_reset_qam()
5233 	if (status < 0)  in qam_reset_qam()
5236 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM  in qam_reset_qam()
5240 	if (status < 0)  in qam_reset_qam()
5241 		pr_err("Error %d on %s\n", status, __func__);  in qam_reset_qam()
5242 	return status;  in qam_reset_qam()
5260 	int status;  in qam_set_symbolrate()  local
5272 	status = write16(state, IQM_FD_RATESEL__A, ratesel);  in qam_set_symbolrate()
5273 	if (status < 0)  in qam_set_symbolrate()
5282 		status = -EINVAL;  in qam_set_symbolrate()
5288 	status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate);  in qam_set_symbolrate()
5289 	if (status < 0)  in qam_set_symbolrate()
5298 		status = -EINVAL;  in qam_set_symbolrate()
5306 	status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate);  in qam_set_symbolrate()
5309 	if (status < 0)  in qam_set_symbolrate()
5310 		pr_err("Error %d on %s\n", status, __func__);  in qam_set_symbolrate()
5311 	return status;  in qam_set_symbolrate()
5317 * \brief Get QAM lock status.
5325 	int status;  in get_qam_lock_status()  local
5330 	status = scu_command(state,  in get_qam_lock_status()
5334 	if (status < 0)  in get_qam_lock_status()
5335 		pr_err("Error %d on %s\n", status, __func__);  in get_qam_lock_status()
5354 	return status;  in get_qam_lock_status()
5367 	int status;  in qam_demodulator_command()  local
5382 		status = scu_command(state,  in qam_demodulator_command()
5386 		if (status < 0)  in qam_demodulator_command()
5389 		status = scu_command(state,  in qam_demodulator_command()
5405 		status = scu_command(state,  in qam_demodulator_command()
5413 		status = -EINVAL;  in qam_demodulator_command()
5417 	if (status < 0)  in qam_demodulator_command()
5418 		pr_warn("Warning %d on %s\n", status, __func__);  in qam_demodulator_command()
5419 	return status;  in qam_demodulator_command()
5425 	int status;  in set_qam()  local
5436 	status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);  in set_qam()
5437 	if (status < 0)  in set_qam()
5439 	status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);  in set_qam()
5440 	if (status < 0)  in set_qam()
5442 	status = qam_reset_qam(state);  in set_qam()
5443 	if (status < 0)  in set_qam()
5451 	status = qam_set_symbolrate(state);  in set_qam()
5452 	if (status < 0)  in set_qam()
5474 		status = -EINVAL;  in set_qam()
5477 	if (status < 0)  in set_qam()
5485 		status = qam_demodulator_command(state, qam_demod_param_count);  in set_qam()
5492 		|| (!state->qam_demod_parameter_count && status < 0)) {  in set_qam()
5494 		status = qam_demodulator_command(state, qam_demod_param_count);  in set_qam()
5497 	if (status < 0) {  in set_qam()
5521 	status = set_frequency(channel, tuner_freq_offset));  in set_qam()
5522 	if (status < 0)  in set_qam()
5525 	status = set_frequency_shifter(state, intermediate_freqk_hz,  in set_qam()
5527 	if (status < 0)  in set_qam()
5531 	status = set_qam_measurement(state, state->m_constellation,  in set_qam()
5533 	if (status < 0)  in set_qam()
5537 	status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);  in set_qam()
5538 	if (status < 0)  in set_qam()
5540 	status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);  in set_qam()
5541 	if (status < 0)  in set_qam()
5545 	status = write16(state, QAM_LC_RATE_LIMIT__A, 3);  in set_qam()
5546 	if (status < 0)  in set_qam()
5548 	status = write16(state, QAM_LC_LPF_FACTORP__A, 4);  in set_qam()
5549 	if (status < 0)  in set_qam()
5551 	status = write16(state, QAM_LC_LPF_FACTORI__A, 4);  in set_qam()
5552 	if (status < 0)  in set_qam()
5554 	status = write16(state, QAM_LC_MODE__A, 7);  in set_qam()
5555 	if (status < 0)  in set_qam()
5558 	status = write16(state, QAM_LC_QUAL_TAB0__A, 1);  in set_qam()
5559 	if (status < 0)  in set_qam()
5561 	status = write16(state, QAM_LC_QUAL_TAB1__A, 1);  in set_qam()
5562 	if (status < 0)  in set_qam()
5564 	status = write16(state, QAM_LC_QUAL_TAB2__A, 1);  in set_qam()
5565 	if (status < 0)  in set_qam()
5567 	status = write16(state, QAM_LC_QUAL_TAB3__A, 1);  in set_qam()
5568 	if (status < 0)  in set_qam()
5570 	status = write16(state, QAM_LC_QUAL_TAB4__A, 2);  in set_qam()
5571 	if (status < 0)  in set_qam()
5573 	status = write16(state, QAM_LC_QUAL_TAB5__A, 2);  in set_qam()
5574 	if (status < 0)  in set_qam()
5576 	status = write16(state, QAM_LC_QUAL_TAB6__A, 2);  in set_qam()
5577 	if (status < 0)  in set_qam()
5579 	status = write16(state, QAM_LC_QUAL_TAB8__A, 2);  in set_qam()
5580 	if (status < 0)  in set_qam()
5582 	status = write16(state, QAM_LC_QUAL_TAB9__A, 2);  in set_qam()
5583 	if (status < 0)  in set_qam()
5585 	status = write16(state, QAM_LC_QUAL_TAB10__A, 2);  in set_qam()
5586 	if (status < 0)  in set_qam()
5588 	status = write16(state, QAM_LC_QUAL_TAB12__A, 2);  in set_qam()
5589 	if (status < 0)  in set_qam()
5591 	status = write16(state, QAM_LC_QUAL_TAB15__A, 3);  in set_qam()
5592 	if (status < 0)  in set_qam()
5594 	status = write16(state, QAM_LC_QUAL_TAB16__A, 3);  in set_qam()
5595 	if (status < 0)  in set_qam()
5597 	status = write16(state, QAM_LC_QUAL_TAB20__A, 4);  in set_qam()
5598 	if (status < 0)  in set_qam()
5600 	status = write16(state, QAM_LC_QUAL_TAB25__A, 4);  in set_qam()
5601 	if (status < 0)  in set_qam()
5605 	status = write16(state, QAM_SY_SP_INV__A,  in set_qam()
5607 	if (status < 0)  in set_qam()
5611 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);  in set_qam()
5612 	if (status < 0)  in set_qam()
5618 		status = set_qam16(state);  in set_qam()
5621 		status = set_qam32(state);  in set_qam()
5625 		status = set_qam64(state);  in set_qam()
5628 		status = set_qam128(state);  in set_qam()
5631 		status = set_qam256(state);  in set_qam()
5634 		status = -EINVAL;  in set_qam()
5637 	if (status < 0)  in set_qam()
5641 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in set_qam()
5642 	if (status < 0)  in set_qam()
5648 	status = mpegts_dto_setup(state, state->m_operation_mode);  in set_qam()
5649 	if (status < 0)  in set_qam()
5653 	status = mpegts_start(state);  in set_qam()
5654 	if (status < 0)  in set_qam()
5656 	status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);  in set_qam()
5657 	if (status < 0)  in set_qam()
5659 	status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);  in set_qam()
5660 	if (status < 0)  in set_qam()
5662 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);  in set_qam()
5663 	if (status < 0)  in set_qam()
5667 	status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM  in set_qam()
5670 	if (status < 0)  in set_qam()
5677 	if (status < 0)  in set_qam()
5678 		pr_err("Error %d on %s\n", status, __func__);  in set_qam()
5679 	return status;  in set_qam()
5685 	int status;  in set_qam_standard()  local
5698 	status = power_up_qam(state);  in set_qam_standard()
5699 	if (status < 0)  in set_qam_standard()
5702 	status = qam_reset_qam(state);  in set_qam_standard()
5703 	if (status < 0)  in set_qam_standard()
5708 	status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);  in set_qam_standard()
5709 	if (status < 0)  in set_qam_standard()
5711 	status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);  in set_qam_standard()
5712 	if (status < 0)  in set_qam_standard()
5719 		status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A,  in set_qam_standard()
5724 		status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A,  in set_qam_standard()
5728 		if (status < 0)  in set_qam_standard()
5730 		status = bl_direct_cmd(state,  in set_qam_standard()
5737 		status = -EINVAL;  in set_qam_standard()
5739 	if (status < 0)  in set_qam_standard()
5742 	status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B);  in set_qam_standard()
5743 	if (status < 0)  in set_qam_standard()
5745 	status = write16(state, IQM_CF_SYMMETRIC__A, 0);  in set_qam_standard()
5746 	if (status < 0)  in set_qam_standard()
5748 	status = write16(state, IQM_CF_MIDTAP__A,  in set_qam_standard()
5750 	if (status < 0)  in set_qam_standard()
5753 	status = write16(state, IQM_RC_STRETCH__A, 21);  in set_qam_standard()
5754 	if (status < 0)  in set_qam_standard()
5756 	status = write16(state, IQM_AF_CLP_LEN__A, 0);  in set_qam_standard()
5757 	if (status < 0)  in set_qam_standard()
5759 	status = write16(state, IQM_AF_CLP_TH__A, 448);  in set_qam_standard()
5760 	if (status < 0)  in set_qam_standard()
5762 	status = write16(state, IQM_AF_SNS_LEN__A, 0);  in set_qam_standard()
5763 	if (status < 0)  in set_qam_standard()
5765 	status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);  in set_qam_standard()
5766 	if (status < 0)  in set_qam_standard()
5769 	status = write16(state, IQM_FS_ADJ_SEL__A, 1);  in set_qam_standard()
5770 	if (status < 0)  in set_qam_standard()
5772 	status = write16(state, IQM_RC_ADJ_SEL__A, 1);  in set_qam_standard()
5773 	if (status < 0)  in set_qam_standard()
5775 	status = write16(state, IQM_CF_ADJ_SEL__A, 1);  in set_qam_standard()
5776 	if (status < 0)  in set_qam_standard()
5778 	status = write16(state, IQM_AF_UPD_SEL__A, 0);  in set_qam_standard()
5779 	if (status < 0)  in set_qam_standard()
5783 	status = write16(state, IQM_CF_CLP_VAL__A, 500);  in set_qam_standard()
5784 	if (status < 0)  in set_qam_standard()
5786 	status = write16(state, IQM_CF_DATATH__A, 1000);  in set_qam_standard()
5787 	if (status < 0)  in set_qam_standard()
5789 	status = write16(state, IQM_CF_BYPASSDET__A, 1);  in set_qam_standard()
5790 	if (status < 0)  in set_qam_standard()
5792 	status = write16(state, IQM_CF_DET_LCT__A, 0);  in set_qam_standard()
5793 	if (status < 0)  in set_qam_standard()
5795 	status = write16(state, IQM_CF_WND_LEN__A, 1);  in set_qam_standard()
5796 	if (status < 0)  in set_qam_standard()
5798 	status = write16(state, IQM_CF_PKDTH__A, 1);  in set_qam_standard()
5799 	if (status < 0)  in set_qam_standard()
5801 	status = write16(state, IQM_AF_INC_BYPASS__A, 1);  in set_qam_standard()
5802 	if (status < 0)  in set_qam_standard()
5806 	status = set_iqm_af(state, true);  in set_qam_standard()
5807 	if (status < 0)  in set_qam_standard()
5809 	status = write16(state, IQM_AF_START_LOCK__A, 0x01);  in set_qam_standard()
5810 	if (status < 0)  in set_qam_standard()
5814 	status = adc_synchronization(state);  in set_qam_standard()
5815 	if (status < 0)  in set_qam_standard()
5819 	status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);  in set_qam_standard()
5820 	if (status < 0)  in set_qam_standard()
5824 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);  in set_qam_standard()
5825 	if (status < 0)  in set_qam_standard()
5831 	status = init_agc(state, true);  in set_qam_standard()
5832 	if (status < 0)  in set_qam_standard()
5834 	status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg));  in set_qam_standard()
5835 	if (status < 0)  in set_qam_standard()
5839 	status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true);  in set_qam_standard()
5840 	if (status < 0)  in set_qam_standard()
5842 	status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true);  in set_qam_standard()
5843 	if (status < 0)  in set_qam_standard()
5847 	status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in set_qam_standard()
5849 	if (status < 0)  in set_qam_standard()
5850 		pr_err("Error %d on %s\n", status, __func__);  in set_qam_standard()
5851 	return status;  in set_qam_standard()
5856 	int status;  in write_gpio()  local
5861 	status = write16(state, SCU_RAM_GPIO__A,  in write_gpio()
5863 	if (status < 0)  in write_gpio()
5867 	status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);  in write_gpio()
5868 	if (status < 0)  in write_gpio()
5874 			status = write16(state, SIO_PDR_SMA_TX_CFG__A,  in write_gpio()
5876 			if (status < 0)  in write_gpio()
5880 			status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);  in write_gpio()
5881 			if (status < 0)  in write_gpio()
5888 			status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);  in write_gpio()
5889 			if (status < 0)  in write_gpio()
5894 			status = write16(state, SIO_PDR_SMA_RX_CFG__A,  in write_gpio()
5896 			if (status < 0)  in write_gpio()
5900 			status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);  in write_gpio()
5901 			if (status < 0)  in write_gpio()
5908 			status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);  in write_gpio()
5909 			if (status < 0)  in write_gpio()
5914 			status = write16(state, SIO_PDR_GPIO_CFG__A,  in write_gpio()
5916 			if (status < 0)  in write_gpio()
5920 			status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);  in write_gpio()
5921 			if (status < 0)  in write_gpio()
5928 			status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);  in write_gpio()
5929 			if (status < 0)  in write_gpio()
5934 	status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);  in write_gpio()
5936 	if (status < 0)  in write_gpio()
5937 		pr_err("Error %d on %s\n", status, __func__);  in write_gpio()
5938 	return status;  in write_gpio()
5943 	int status = 0;  in switch_antenna_to_qam()  local
5959 		status = write_gpio(state);  in switch_antenna_to_qam()
5961 	if (status < 0)  in switch_antenna_to_qam()
5962 		pr_err("Error %d on %s\n", status, __func__);  in switch_antenna_to_qam()
5963 	return status;  in switch_antenna_to_qam()
5968 	int status = 0;  in switch_antenna_to_dvbt()  local
5984 		status = write_gpio(state);  in switch_antenna_to_dvbt()
5986 	if (status < 0)  in switch_antenna_to_dvbt()
5987 		pr_err("Error %d on %s\n", status, __func__);  in switch_antenna_to_dvbt()
5988 	return status;  in switch_antenna_to_dvbt()
6000 	int status;  in power_down_device()  local
6005 		status = ConfigureI2CBridge(state, true);  in power_down_device()
6006 		if (status < 0)  in power_down_device()
6010 	status = dvbt_enable_ofdm_token_ring(state, false);  in power_down_device()
6011 	if (status < 0)  in power_down_device()
6014 	status = write16(state, SIO_CC_PWD_MODE__A,  in power_down_device()
6016 	if (status < 0)  in power_down_device()
6018 	status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);  in power_down_device()
6019 	if (status < 0)  in power_down_device()
6022 	status = hi_cfg_command(state);  in power_down_device()
6024 	if (status < 0)  in power_down_device()
6025 		pr_err("Error %d on %s\n", status, __func__);  in power_down_device()
6027 	return status;  in power_down_device()
6032 	int status = 0, n = 0;  in init_drxk()  local
6039 		status = power_up_device(state);  in init_drxk()
6040 		if (status < 0)  in init_drxk()
6042 		status = drxx_open(state);  in init_drxk()
6043 		if (status < 0)  in init_drxk()
6046 		status = write16(state, SIO_CC_SOFT_RST__A,  in init_drxk()
6050 		if (status < 0)  in init_drxk()
6052 		status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);  in init_drxk()
6053 		if (status < 0)  in init_drxk()
6061 		status = get_device_capabilities(state);  in init_drxk()
6062 		if (status < 0)  in init_drxk()
6082 		status = init_hi(state);  in init_drxk()
6083 		if (status < 0)  in init_drxk()
6091 			status = write16(state, SCU_RAM_GPIO__A,  in init_drxk()
6093 			if (status < 0)  in init_drxk()
6098 		status = mpegts_disable(state);  in init_drxk()
6099 		if (status < 0)  in init_drxk()
6103 		status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);  in init_drxk()
6104 		if (status < 0)  in init_drxk()
6106 		status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);  in init_drxk()
6107 		if (status < 0)  in init_drxk()
6111 		status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,  in init_drxk()
6113 		if (status < 0)  in init_drxk()
6117 		status = write16(state, SIO_BL_COMM_EXEC__A,  in init_drxk()
6119 		if (status < 0)  in init_drxk()
6121 		status = bl_chain_cmd(state, 0, 6, 100);  in init_drxk()
6122 		if (status < 0)  in init_drxk()
6126 			status = download_microcode(state, state->fw->data,  in init_drxk()
6128 			if (status < 0)  in init_drxk()
6133 		status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,  in init_drxk()
6135 		if (status < 0)  in init_drxk()
6139 		status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);  in init_drxk()
6140 		if (status < 0)  in init_drxk()
6142 		status = drxx_open(state);  in init_drxk()
6143 		if (status < 0)  in init_drxk()
6149 		status = ctrl_power_mode(state, &power_mode);  in init_drxk()
6150 		if (status < 0)  in init_drxk()
6164 		status = write16(state, SCU_RAM_DRIVER_VER_HI__A,  in init_drxk()
6166 		if (status < 0)  in init_drxk()
6173 		status = write16(state, SCU_RAM_DRIVER_VER_LO__A,  in init_drxk()
6175 		if (status < 0)  in init_drxk()
6193 		status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);  in init_drxk()
6194 		if (status < 0)  in init_drxk()
6199 		status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);  in init_drxk()
6200 		if (status < 0)  in init_drxk()
6203 		status = mpegts_dto_init(state);  in init_drxk()
6204 		if (status < 0)  in init_drxk()
6206 		status = mpegts_stop(state);  in init_drxk()
6207 		if (status < 0)  in init_drxk()
6209 		status = mpegts_configure_polarity(state);  in init_drxk()
6210 		if (status < 0)  in init_drxk()
6212 		status = mpegts_configure_pins(state, state->m_enable_mpeg_output);  in init_drxk()
6213 		if (status < 0)  in init_drxk()
6216 		status = write_gpio(state);  in init_drxk()
6217 		if (status < 0)  in init_drxk()
6223 			status = power_down_device(state);  in init_drxk()
6224 			if (status < 0)  in init_drxk()
6246 	if (status < 0) {  in init_drxk()
6249 		pr_err("Error %d on %s\n", status, __func__);  in init_drxk()
6252 	return status;  in init_drxk()
6395 	int status;  in get_strength()  local
6421 		status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl);  in get_strength()
6422 		if (status < 0)  in get_strength()
6423 			return status;  in get_strength()
6426 		status = read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc);  in get_strength()
6427 		if (status < 0)  in get_strength()
6428 			return status;  in get_strength()
6454 		status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,  in get_strength()
6456 		if (status < 0)  in get_strength()
6457 			return status;  in get_strength()
6459 		status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,  in get_strength()
6461 		if (status < 0)  in get_strength()
6462 			return status;  in get_strength()
6498 	int status;  in drxk_get_stats()  local
6515 	/* get status */  in drxk_get_stats()
6561 	status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, &reg16);  in drxk_get_stats()
6562 	if (status < 0)  in drxk_get_stats()
6566 	status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , &reg16);  in drxk_get_stats()
6567 	if (status < 0)  in drxk_get_stats()
6572 	status = read16(state, FEC_RS_NR_BIT_ERRORS__A, &reg16);  in drxk_get_stats()
6573 	if (status < 0)  in drxk_get_stats()
6577 	status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, &reg16);  in drxk_get_stats()
6578 	if (status < 0)  in drxk_get_stats()
6582 	status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, &reg16);  in drxk_get_stats()
6583 	if (status < 0)  in drxk_get_stats()
6587 	status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &reg16);  in drxk_get_stats()
6588 	if (status < 0)  in drxk_get_stats()
6614 	return status;  in drxk_get_stats()
6618 static int drxk_read_status(struct dvb_frontend *fe, enum fe_status *status)  in drxk_read_status()  argument
6629 	*status = state->fe_status;  in drxk_read_status()
6754 	int status;  in drxk_attach()  local
6811 		status = request_firmware(&fw, state->microcode_name,  in drxk_attach()
6813 		if (status < 0)  in drxk_attach()