Lines Matching refs:rc
1421 int rc; in drxdap_fasi_read_block() local
1483 rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, in drxdap_fasi_read_block()
1485 if (rc == 0) in drxdap_fasi_read_block()
1486 rc = drxbsp_i2c_write_read(NULL, 0, NULL, dev_addr, todo, data); in drxdap_fasi_read_block()
1489 rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo, in drxdap_fasi_read_block()
1495 } while (datasize && rc == 0); in drxdap_fasi_read_block()
1497 return rc; in drxdap_fasi_read_block()
1524 int rc; in drxdap_fasi_read_reg16() local
1529 rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags); in drxdap_fasi_read_reg16()
1531 return rc; in drxdap_fasi_read_reg16()
1557 int rc; in drxdap_fasi_read_reg32() local
1562 rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags); in drxdap_fasi_read_reg32()
1566 return rc; in drxdap_fasi_read_reg32()
1767 int rc = -EIO; in drxdap_fasi_read_modify_write_reg16() local
1773 rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW); in drxdap_fasi_read_modify_write_reg16()
1774 if (rc == 0) in drxdap_fasi_read_modify_write_reg16()
1775 rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0); in drxdap_fasi_read_modify_write_reg16()
1778 return rc; in drxdap_fasi_read_modify_write_reg16()
1840 int rc; in drxj_dap_rm_write_reg16short() local
1846 rc = drxdap_fasi_write_reg16(dev_addr, in drxj_dap_rm_write_reg16short()
1850 if (rc == 0) { in drxj_dap_rm_write_reg16short()
1852 rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, in drxj_dap_rm_write_reg16short()
1855 if (rc == 0) { in drxj_dap_rm_write_reg16short()
1857 rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, in drxj_dap_rm_write_reg16short()
1860 if (rc == 0) { in drxj_dap_rm_write_reg16short()
1862 rc = drxdap_fasi_write_reg16(dev_addr, in drxj_dap_rm_write_reg16short()
1867 return rc; in drxj_dap_rm_write_reg16short()
2108 int rc; in drxj_dap_atomic_read_write_block() local
2145 rc = hi_command(dev_addr, &hi_cmd, &dummy); in drxj_dap_atomic_read_write_block()
2146 if (rc != 0) { in drxj_dap_atomic_read_write_block()
2147 pr_err("error %d\n", rc); in drxj_dap_atomic_read_write_block()
2154 rc = drxj_dap_read_reg16(dev_addr, in drxj_dap_atomic_read_write_block()
2157 if (rc) { in drxj_dap_atomic_read_write_block()
2158 pr_err("error %d\n", rc); in drxj_dap_atomic_read_write_block()
2169 return rc; in drxj_dap_atomic_read_write_block()
2185 int rc; in drxj_dap_atomic_read_reg32() local
2191 rc = drxj_dap_atomic_read_write_block(dev_addr, addr, in drxj_dap_atomic_read_reg32()
2194 if (rc < 0) in drxj_dap_atomic_read_reg32()
2207 return rc; in drxj_dap_atomic_read_reg32()
2238 int rc; in hi_cfg_command() local
2250 rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result); in hi_cfg_command()
2251 if (rc != 0) { in hi_cfg_command()
2252 pr_err("error %d\n", rc); in hi_cfg_command()
2262 return rc; in hi_cfg_command()
2282 int rc; in hi_command() local
2289 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0); in hi_command()
2290 if (rc != 0) { in hi_command()
2291 pr_err("error %d\n", rc); in hi_command()
2294 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0); in hi_command()
2295 if (rc != 0) { in hi_command()
2296 pr_err("error %d\n", rc); in hi_command()
2299 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0); in hi_command()
2300 if (rc != 0) { in hi_command()
2301 pr_err("error %d\n", rc); in hi_command()
2304 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0); in hi_command()
2305 if (rc != 0) { in hi_command()
2306 pr_err("error %d\n", rc); in hi_command()
2311 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0); in hi_command()
2312 if (rc != 0) { in hi_command()
2313 pr_err("error %d\n", rc); in hi_command()
2316 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0); in hi_command()
2317 if (rc != 0) { in hi_command()
2318 pr_err("error %d\n", rc); in hi_command()
2332 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0); in hi_command()
2333 if (rc != 0) { in hi_command()
2334 pr_err("error %d\n", rc); in hi_command()
2355 rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd, 0); in hi_command()
2356 if (rc != 0) { in hi_command()
2357 pr_err("error %d\n", rc); in hi_command()
2363 rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_RES__A, result, 0); in hi_command()
2364 if (rc != 0) { in hi_command()
2365 pr_err("error %d\n", rc); in hi_command()
2373 return rc; in hi_command()
2394 int rc; in init_hi() local
2401 rc = drxj_dap_write_reg16(dev_addr, 0x4301D7, 0x801, 0); in init_hi()
2402 if (rc != 0) { in init_hi()
2403 pr_err("error %d\n", rc); in init_hi()
2435 rc = hi_cfg_command(demod); in init_hi()
2436 if (rc != 0) { in init_hi()
2437 pr_err("error %d\n", rc); in init_hi()
2444 return rc; in init_hi()
2481 int rc; in get_device_capabilities() local
2487 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); in get_device_capabilities()
2488 if (rc != 0) { in get_device_capabilities()
2489 pr_err("error %d\n", rc); in get_device_capabilities()
2492 rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg, 0); in get_device_capabilities()
2493 if (rc != 0) { in get_device_capabilities()
2494 pr_err("error %d\n", rc); in get_device_capabilities()
2497 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0); in get_device_capabilities()
2498 if (rc != 0) { in get_device_capabilities()
2499 pr_err("error %d\n", rc); in get_device_capabilities()
2527 rc = drxdap_fasi_read_reg32(dev_addr, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo, 0); in get_device_capabilities()
2528 if (rc != 0) { in get_device_capabilities()
2529 pr_err("error %d\n", rc); in get_device_capabilities()
2536 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); in get_device_capabilities()
2537 if (rc != 0) { in get_device_capabilities()
2538 pr_err("error %d\n", rc); in get_device_capabilities()
2541 rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0); in get_device_capabilities()
2542 if (rc != 0) { in get_device_capabilities()
2543 pr_err("error %d\n", rc); in get_device_capabilities()
2547 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0); in get_device_capabilities()
2548 if (rc != 0) { in get_device_capabilities()
2549 pr_err("error %d\n", rc); in get_device_capabilities()
2660 return rc; in get_device_capabilities()
2733 int rc; in ctrl_set_cfg_mpeg_output() local
2769 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_INVERT__A, 0, 0); in ctrl_set_cfg_mpeg_output()
2770 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2771 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2776 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, 7, 0); in ctrl_set_cfg_mpeg_output()
2777 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2778 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2781 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, 10, 0); in ctrl_set_cfg_mpeg_output()
2782 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2783 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2786 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 10, 0); in ctrl_set_cfg_mpeg_output()
2787 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2788 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2791 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, 5, 0); in ctrl_set_cfg_mpeg_output()
2792 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2793 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2796 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, 7, 0); in ctrl_set_cfg_mpeg_output()
2797 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2798 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2801 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 10, 0); in ctrl_set_cfg_mpeg_output()
2802 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2803 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2807 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 3, 0); in ctrl_set_cfg_mpeg_output()
2808 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2809 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2813 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 5, 0); in ctrl_set_cfg_mpeg_output()
2814 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2815 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2846 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0); in ctrl_set_cfg_mpeg_output()
2847 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2848 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2851 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE, 0); in ctrl_set_cfg_mpeg_output()
2852 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2853 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2856 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 5, 0); in ctrl_set_cfg_mpeg_output()
2857 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2858 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2861 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE, 0); in ctrl_set_cfg_mpeg_output()
2862 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2863 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2866 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE, 0); in ctrl_set_cfg_mpeg_output()
2867 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2868 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2872 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 0xD, 0); in ctrl_set_cfg_mpeg_output()
2873 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2874 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2878 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE, 0); in ctrl_set_cfg_mpeg_output()
2879 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2880 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2884 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 2, 0); in ctrl_set_cfg_mpeg_output()
2885 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2886 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2889 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 12, 0); in ctrl_set_cfg_mpeg_output()
2890 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2891 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2900 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0); in ctrl_set_cfg_mpeg_output()
2901 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2902 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2905 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode, 0); in ctrl_set_cfg_mpeg_output()
2906 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2907 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3062 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_HI__A, (u16)((dto_rate >> 16) & FEC_OC_DTO_RAT… in ctrl_set_cfg_mpeg_output()
3063 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3064 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3067 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_LO__A, (u16)(dto_rate & FEC_OC_DTO_RATE_LO_RAT… in ctrl_set_cfg_mpeg_output()
3068 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3069 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3072 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MO… in ctrl_set_cfg_mpeg_output()
3073 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3074 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3077 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MO… in ctrl_set_cfg_mpeg_output()
3078 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3079 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3082 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len, 0); in ctrl_set_cfg_mpeg_output()
3083 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3084 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3089 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period, 0); in ctrl_set_cfg_mpeg_output()
3090 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3091 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3096 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M, 0); in ctrl_set_cfg_mpeg_output()
3097 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3098 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3101 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, 0, 0); in ctrl_set_cfg_mpeg_output()
3102 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3103 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3108 rc = drxdap_fasi_write_reg32(dev_addr, FEC_OC_RCN_CTL_RATE_LO__A, rcn_rate, 0); in ctrl_set_cfg_mpeg_output()
3109 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3110 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3115 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode, 0); in ctrl_set_cfg_mpeg_output()
3116 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3117 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3120 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode, 0); in ctrl_set_cfg_mpeg_output()
3121 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3122 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3125 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert, 0); in ctrl_set_cfg_mpeg_output()
3126 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3127 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3133 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); in ctrl_set_cfg_mpeg_output()
3134 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3135 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3139 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0013, 0); in ctrl_set_cfg_mpeg_output()
3140 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3141 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3144 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0013, 0); in ctrl_set_cfg_mpeg_output()
3145 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3146 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3149 …rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR… in ctrl_set_cfg_mpeg_output()
3150 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3151 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3154 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0013, 0); in ctrl_set_cfg_mpeg_output()
3155 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3156 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3162 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3163 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3164 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3172 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3173 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3174 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3177 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3178 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3179 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3182 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3183 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3184 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3187 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3188 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3189 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3192 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3193 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3194 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3197 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3198 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3199 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3202 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3203 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3204 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3207 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3208 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3209 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3213 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3214 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3215 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3218 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3219 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3220 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3223 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3224 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3225 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3228 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3229 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3230 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3233 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3234 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3235 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3238 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3239 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3240 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3243 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3244 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3245 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3250 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3251 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3252 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3256 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3257 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3258 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3263 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); in ctrl_set_cfg_mpeg_output()
3264 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3265 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3269 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3270 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3271 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3274 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3275 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3276 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3279 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3280 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3281 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3284 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3285 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3286 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3289 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3290 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3291 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3294 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3295 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3296 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3299 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3300 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3301 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3304 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3305 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3306 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3309 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3310 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3311 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3314 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3315 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3316 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3319 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3320 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3321 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3324 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3325 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3326 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3330 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3331 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3332 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3336 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3337 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3338 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3348 return rc; in ctrl_set_cfg_mpeg_output()
3375 int rc; in set_mpegtei_handling() local
3383 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode, 0); in set_mpegtei_handling()
3384 if (rc != 0) { in set_mpegtei_handling()
3385 pr_err("error %d\n", rc); in set_mpegtei_handling()
3388 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0); in set_mpegtei_handling()
3389 if (rc != 0) { in set_mpegtei_handling()
3390 pr_err("error %d\n", rc); in set_mpegtei_handling()
3393 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_EMS_MODE__A, &fec_oc_ems_mode, 0); in set_mpegtei_handling()
3394 if (rc != 0) { in set_mpegtei_handling()
3395 pr_err("error %d\n", rc); in set_mpegtei_handling()
3413 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DPR_MODE__A, fec_oc_dpr_mode, 0); in set_mpegtei_handling()
3414 if (rc != 0) { in set_mpegtei_handling()
3415 pr_err("error %d\n", rc); in set_mpegtei_handling()
3418 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode, 0); in set_mpegtei_handling()
3419 if (rc != 0) { in set_mpegtei_handling()
3420 pr_err("error %d\n", rc); in set_mpegtei_handling()
3423 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_EMS_MODE__A, fec_oc_ems_mode, 0); in set_mpegtei_handling()
3424 if (rc != 0) { in set_mpegtei_handling()
3425 pr_err("error %d\n", rc); in set_mpegtei_handling()
3431 return rc; in set_mpegtei_handling()
3448 int rc; in bit_reverse_mpeg_output() local
3454 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode, 0); in bit_reverse_mpeg_output()
3455 if (rc != 0) { in bit_reverse_mpeg_output()
3456 pr_err("error %d\n", rc); in bit_reverse_mpeg_output()
3466 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode, 0); in bit_reverse_mpeg_output()
3467 if (rc != 0) { in bit_reverse_mpeg_output()
3468 pr_err("error %d\n", rc); in bit_reverse_mpeg_output()
3474 return rc; in bit_reverse_mpeg_output()
3492 int rc; in set_mpeg_start_width() local
3501 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_COMM_MB__A, &fec_oc_comm_mb, 0); in set_mpeg_start_width()
3502 if (rc != 0) { in set_mpeg_start_width()
3503 pr_err("error %d\n", rc); in set_mpeg_start_width()
3509 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb, 0); in set_mpeg_start_width()
3510 if (rc != 0) { in set_mpeg_start_width()
3511 pr_err("error %d\n", rc); in set_mpeg_start_width()
3518 return rc; in set_mpeg_start_width()
3538 int rc; in ctrl_set_uio_cfg() local
3546 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); in ctrl_set_uio_cfg()
3547 if (rc != 0) { in ctrl_set_uio_cfg()
3548 pr_err("error %d\n", rc); in ctrl_set_uio_cfg()
3566 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0); in ctrl_set_uio_cfg()
3567 if (rc != 0) { in ctrl_set_uio_cfg()
3568 pr_err("error %d\n", rc); in ctrl_set_uio_cfg()
3589 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0); in ctrl_set_uio_cfg()
3590 if (rc != 0) { in ctrl_set_uio_cfg()
3591 pr_err("error %d\n", rc); in ctrl_set_uio_cfg()
3613 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0); in ctrl_set_uio_cfg()
3614 if (rc != 0) { in ctrl_set_uio_cfg()
3615 pr_err("error %d\n", rc); in ctrl_set_uio_cfg()
3635 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0); in ctrl_set_uio_cfg()
3636 if (rc != 0) { in ctrl_set_uio_cfg()
3637 pr_err("error %d\n", rc); in ctrl_set_uio_cfg()
3654 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in ctrl_set_uio_cfg()
3655 if (rc != 0) { in ctrl_set_uio_cfg()
3656 pr_err("error %d\n", rc); in ctrl_set_uio_cfg()
3662 return rc; in ctrl_set_uio_cfg()
3676 int rc; in ctrl_uio_write() local
3686 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); in ctrl_uio_write()
3687 if (rc != 0) { in ctrl_uio_write()
3688 pr_err("error %d\n", rc); in ctrl_uio_write()
3708 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0); in ctrl_uio_write()
3709 if (rc != 0) { in ctrl_uio_write()
3710 pr_err("error %d\n", rc); in ctrl_uio_write()
3715 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); in ctrl_uio_write()
3716 if (rc != 0) { in ctrl_uio_write()
3717 pr_err("error %d\n", rc); in ctrl_uio_write()
3726 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); in ctrl_uio_write()
3727 if (rc != 0) { in ctrl_uio_write()
3728 pr_err("error %d\n", rc); in ctrl_uio_write()
3747 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0); in ctrl_uio_write()
3748 if (rc != 0) { in ctrl_uio_write()
3749 pr_err("error %d\n", rc); in ctrl_uio_write()
3754 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); in ctrl_uio_write()
3755 if (rc != 0) { in ctrl_uio_write()
3756 pr_err("error %d\n", rc); in ctrl_uio_write()
3765 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); in ctrl_uio_write()
3766 if (rc != 0) { in ctrl_uio_write()
3767 pr_err("error %d\n", rc); in ctrl_uio_write()
3786 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0); in ctrl_uio_write()
3787 if (rc != 0) { in ctrl_uio_write()
3788 pr_err("error %d\n", rc); in ctrl_uio_write()
3793 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0); in ctrl_uio_write()
3794 if (rc != 0) { in ctrl_uio_write()
3795 pr_err("error %d\n", rc); in ctrl_uio_write()
3804 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0); in ctrl_uio_write()
3805 if (rc != 0) { in ctrl_uio_write()
3806 pr_err("error %d\n", rc); in ctrl_uio_write()
3826 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0); in ctrl_uio_write()
3827 if (rc != 0) { in ctrl_uio_write()
3828 pr_err("error %d\n", rc); in ctrl_uio_write()
3833 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); in ctrl_uio_write()
3834 if (rc != 0) { in ctrl_uio_write()
3835 pr_err("error %d\n", rc); in ctrl_uio_write()
3844 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); in ctrl_uio_write()
3845 if (rc != 0) { in ctrl_uio_write()
3846 pr_err("error %d\n", rc); in ctrl_uio_write()
3856 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in ctrl_uio_write()
3857 if (rc != 0) { in ctrl_uio_write()
3858 pr_err("error %d\n", rc); in ctrl_uio_write()
3864 return rc; in ctrl_uio_write()
3921 int rc; in smart_ant_init() local
3928 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); in smart_ant_init()
3929 if (rc != 0) { in smart_ant_init()
3930 pr_err("error %d\n", rc); in smart_ant_init()
3934 rc = drxj_dap_read_reg16(dev_addr, SIO_SA_TX_COMMAND__A, &data, 0); in smart_ant_init()
3935 if (rc != 0) { in smart_ant_init()
3936 pr_err("error %d\n", rc); in smart_ant_init()
3940 …rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) … in smart_ant_init()
3941 if (rc != 0) { in smart_ant_init()
3942 pr_err("error %d\n", rc); in smart_ant_init()
3946 …rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M… in smart_ant_init()
3947 if (rc != 0) { in smart_ant_init()
3948 pr_err("error %d\n", rc); in smart_ant_init()
3954 rc = ctrl_set_uio_cfg(demod, &uio_cfg); in smart_ant_init()
3955 if (rc != 0) { in smart_ant_init()
3956 pr_err("error %d\n", rc); in smart_ant_init()
3959 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0); in smart_ant_init()
3960 if (rc != 0) { in smart_ant_init()
3961 pr_err("error %d\n", rc); in smart_ant_init()
3964 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0); in smart_ant_init()
3965 if (rc != 0) { in smart_ant_init()
3966 pr_err("error %d\n", rc); in smart_ant_init()
3971 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in smart_ant_init()
3972 if (rc != 0) { in smart_ant_init()
3973 pr_err("error %d\n", rc); in smart_ant_init()
3979 return rc; in smart_ant_init()
3984 int rc; in scu_command() local
3993 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0); in scu_command()
3994 if (rc != 0) { in scu_command()
3995 pr_err("error %d\n", rc); in scu_command()
4003 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0); in scu_command()
4004 if (rc != 0) { in scu_command()
4005 pr_err("error %d\n", rc); in scu_command()
4010 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0); in scu_command()
4011 if (rc != 0) { in scu_command()
4012 pr_err("error %d\n", rc); in scu_command()
4017 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0); in scu_command()
4018 if (rc != 0) { in scu_command()
4019 pr_err("error %d\n", rc); in scu_command()
4024 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0); in scu_command()
4025 if (rc != 0) { in scu_command()
4026 pr_err("error %d\n", rc); in scu_command()
4031 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0); in scu_command()
4032 if (rc != 0) { in scu_command()
4033 pr_err("error %d\n", rc); in scu_command()
4044 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0); in scu_command()
4045 if (rc != 0) { in scu_command()
4046 pr_err("error %d\n", rc); in scu_command()
4053 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0); in scu_command()
4054 if (rc != 0) { in scu_command()
4055 pr_err("error %d\n", rc); in scu_command()
4072 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0); in scu_command()
4073 if (rc != 0) { in scu_command()
4074 pr_err("error %d\n", rc); in scu_command()
4079 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0); in scu_command()
4080 if (rc != 0) { in scu_command()
4081 pr_err("error %d\n", rc); in scu_command()
4086 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0); in scu_command()
4087 if (rc != 0) { in scu_command()
4088 pr_err("error %d\n", rc); in scu_command()
4093 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0); in scu_command()
4094 if (rc != 0) { in scu_command()
4095 pr_err("error %d\n", rc); in scu_command()
4128 return rc; in scu_command()
4149 int rc; in drxj_dap_scu_atomic_read_write_block() local
4179 rc = scu_command(dev_addr, &scu_cmd); in drxj_dap_scu_atomic_read_write_block()
4180 if (rc != 0) { in drxj_dap_scu_atomic_read_write_block()
4181 pr_err("error %d\n", rc); in drxj_dap_scu_atomic_read_write_block()
4197 return rc; in drxj_dap_scu_atomic_read_write_block()
4213 int rc; in drxj_dap_scu_atomic_read_reg16() local
4219 rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, true); in drxj_dap_scu_atomic_read_reg16()
4220 if (rc < 0) in drxj_dap_scu_atomic_read_reg16()
4221 return rc; in drxj_dap_scu_atomic_read_reg16()
4227 return rc; in drxj_dap_scu_atomic_read_reg16()
4241 int rc; in drxj_dap_scu_atomic_write_reg16() local
4246 rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, false); in drxj_dap_scu_atomic_write_reg16()
4248 return rc; in drxj_dap_scu_atomic_write_reg16()
4264 int rc; in adc_sync_measurement() local
4270 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE, 0); in adc_sync_measurement()
4271 if (rc != 0) { in adc_sync_measurement()
4272 pr_err("error %d\n", rc); in adc_sync_measurement()
4275 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_START_LOCK__A, 1, 0); in adc_sync_measurement()
4276 if (rc != 0) { in adc_sync_measurement()
4277 pr_err("error %d\n", rc); in adc_sync_measurement()
4285 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE0__A, &data, 0); in adc_sync_measurement()
4286 if (rc != 0) { in adc_sync_measurement()
4287 pr_err("error %d\n", rc); in adc_sync_measurement()
4292 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE1__A, &data, 0); in adc_sync_measurement()
4293 if (rc != 0) { in adc_sync_measurement()
4294 pr_err("error %d\n", rc); in adc_sync_measurement()
4299 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE2__A, &data, 0); in adc_sync_measurement()
4300 if (rc != 0) { in adc_sync_measurement()
4301 pr_err("error %d\n", rc); in adc_sync_measurement()
4309 return rc; in adc_sync_measurement()
4327 int rc; in adc_synchronization() local
4332 rc = adc_sync_measurement(demod, &count); in adc_synchronization()
4333 if (rc != 0) { in adc_synchronization()
4334 pr_err("error %d\n", rc); in adc_synchronization()
4342 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_CLKNEG__A, &clk_neg, 0); in adc_synchronization()
4343 if (rc != 0) { in adc_synchronization()
4344 pr_err("error %d\n", rc); in adc_synchronization()
4349 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLKNEG__A, clk_neg, 0); in adc_synchronization()
4350 if (rc != 0) { in adc_synchronization()
4351 pr_err("error %d\n", rc); in adc_synchronization()
4355 rc = adc_sync_measurement(demod, &count); in adc_synchronization()
4356 if (rc != 0) { in adc_synchronization()
4357 pr_err("error %d\n", rc); in adc_synchronization()
4368 return rc; in adc_synchronization()
4394 int rc; in init_agc() local
4428 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0); in init_agc()
4429 if (rc != 0) { in init_agc()
4430 pr_err("error %d\n", rc); in init_agc()
4433 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0); in init_agc()
4434 if (rc != 0) { in init_agc()
4435 pr_err("error %d\n", rc); in init_agc()
4438 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0); in init_agc()
4439 if (rc != 0) { in init_agc()
4440 pr_err("error %d\n", rc); in init_agc()
4443 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0); in init_agc()
4444 if (rc != 0) { in init_agc()
4445 pr_err("error %d\n", rc); in init_agc()
4448 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0); in init_agc()
4449 if (rc != 0) { in init_agc()
4450 pr_err("error %d\n", rc); in init_agc()
4453 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0); in init_agc()
4454 if (rc != 0) { in init_agc()
4455 pr_err("error %d\n", rc); in init_agc()
4458 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0); in init_agc()
4459 if (rc != 0) { in init_agc()
4460 pr_err("error %d\n", rc); in init_agc()
4463 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0); in init_agc()
4464 if (rc != 0) { in init_agc()
4465 pr_err("error %d\n", rc); in init_agc()
4468 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0); in init_agc()
4469 if (rc != 0) { in init_agc()
4470 pr_err("error %d\n", rc); in init_agc()
4473 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0); in init_agc()
4474 if (rc != 0) { in init_agc()
4475 pr_err("error %d\n", rc); in init_agc()
4478 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, 1024, 0); in init_agc()
4479 if (rc != 0) { in init_agc()
4480 pr_err("error %d\n", rc); in init_agc()
4483 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600, 0); in init_agc()
4484 if (rc != 0) { in init_agc()
4485 pr_err("error %d\n", rc); in init_agc()
4488 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, 13200, 0); in init_agc()
4489 if (rc != 0) { in init_agc()
4490 pr_err("error %d\n", rc); in init_agc()
4511 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0); in init_agc()
4512 if (rc != 0) { in init_agc()
4513 pr_err("error %d\n", rc); in init_agc()
4516 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0); in init_agc()
4517 if (rc != 0) { in init_agc()
4518 pr_err("error %d\n", rc); in init_agc()
4521 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0); in init_agc()
4522 if (rc != 0) { in init_agc()
4523 pr_err("error %d\n", rc); in init_agc()
4526 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0); in init_agc()
4527 if (rc != 0) { in init_agc()
4528 pr_err("error %d\n", rc); in init_agc()
4531 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0); in init_agc()
4532 if (rc != 0) { in init_agc()
4533 pr_err("error %d\n", rc); in init_agc()
4536 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0); in init_agc()
4537 if (rc != 0) { in init_agc()
4538 pr_err("error %d\n", rc); in init_agc()
4541 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0); in init_agc()
4542 if (rc != 0) { in init_agc()
4543 pr_err("error %d\n", rc); in init_agc()
4546 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0); in init_agc()
4547 if (rc != 0) { in init_agc()
4548 pr_err("error %d\n", rc); in init_agc()
4551 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0); in init_agc()
4552 if (rc != 0) { in init_agc()
4553 pr_err("error %d\n", rc); in init_agc()
4556 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0); in init_agc()
4557 if (rc != 0) { in init_agc()
4558 pr_err("error %d\n", rc); in init_agc()
4563 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); in init_agc()
4564 if (rc != 0) { in init_agc()
4565 pr_err("error %d\n", rc); in init_agc()
4569 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &agc_ki, 0); in init_agc()
4570 if (rc != 0) { in init_agc()
4571 pr_err("error %d\n", rc); in init_agc()
4575 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, agc_ki, 0); in init_agc()
4576 if (rc != 0) { in init_agc()
4577 pr_err("error %d\n", rc); in init_agc()
4587 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0); in init_agc()
4588 if (rc != 0) { in init_agc()
4589 pr_err("error %d\n", rc); in init_agc()
4592 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0); in init_agc()
4593 if (rc != 0) { in init_agc()
4594 pr_err("error %d\n", rc); in init_agc()
4597 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max, 0); in init_agc()
4598 if (rc != 0) { in init_agc()
4599 pr_err("error %d\n", rc); in init_agc()
4602 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min, 0); in init_agc()
4603 if (rc != 0) { in init_agc()
4604 pr_err("error %d\n", rc); in init_agc()
4607 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, 0, 0); in init_agc()
4608 if (rc != 0) { in init_agc()
4609 pr_err("error %d\n", rc); in init_agc()
4612 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_LO__A, 0, 0); in init_agc()
4613 if (rc != 0) { in init_agc()
4614 pr_err("error %d\n", rc); in init_agc()
4617 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, 0, 0); in init_agc()
4618 if (rc != 0) { in init_agc()
4619 pr_err("error %d\n", rc); in init_agc()
4622 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_LO__A, 0, 0); in init_agc()
4623 if (rc != 0) { in init_agc()
4624 pr_err("error %d\n", rc); in init_agc()
4627 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_MAX__A, 32767, 0); in init_agc()
4628 if (rc != 0) { in init_agc()
4629 pr_err("error %d\n", rc); in init_agc()
4632 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max, 0); in init_agc()
4633 if (rc != 0) { in init_agc()
4634 pr_err("error %d\n", rc); in init_agc()
4637 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max, 0); in init_agc()
4638 if (rc != 0) { in init_agc()
4639 pr_err("error %d\n", rc); in init_agc()
4642 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min, 0); in init_agc()
4643 if (rc != 0) { in init_agc()
4644 pr_err("error %d\n", rc); in init_agc()
4647 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50, 0); in init_agc()
4648 if (rc != 0) { in init_agc()
4649 pr_err("error %d\n", rc); in init_agc()
4652 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_CYCLEN__A, 500, 0); in init_agc()
4653 if (rc != 0) { in init_agc()
4654 pr_err("error %d\n", rc); in init_agc()
4657 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCLEN__A, 500, 0); in init_agc()
4658 if (rc != 0) { in init_agc()
4659 pr_err("error %d\n", rc); in init_agc()
4662 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20, 0); in init_agc()
4663 if (rc != 0) { in init_agc()
4664 pr_err("error %d\n", rc); in init_agc()
4667 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MIN__A, ki_min, 0); in init_agc()
4668 if (rc != 0) { in init_agc()
4669 pr_err("error %d\n", rc); in init_agc()
4672 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAX__A, ki_max, 0); in init_agc()
4673 if (rc != 0) { in init_agc()
4674 pr_err("error %d\n", rc); in init_agc()
4677 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_RED__A, 0, 0); in init_agc()
4678 if (rc != 0) { in init_agc()
4679 pr_err("error %d\n", rc); in init_agc()
4682 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8, 0); in init_agc()
4683 if (rc != 0) { in init_agc()
4684 pr_err("error %d\n", rc); in init_agc()
4687 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCLEN__A, 500, 0); in init_agc()
4688 if (rc != 0) { in init_agc()
4689 pr_err("error %d\n", rc); in init_agc()
4692 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to, 0); in init_agc()
4693 if (rc != 0) { in init_agc()
4694 pr_err("error %d\n", rc); in init_agc()
4697 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8, 0); in init_agc()
4698 if (rc != 0) { in init_agc()
4699 pr_err("error %d\n", rc); in init_agc()
4702 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to, 0); in init_agc()
4703 if (rc != 0) { in init_agc()
4704 pr_err("error %d\n", rc); in init_agc()
4707 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50, 0); in init_agc()
4708 if (rc != 0) { in init_agc()
4709 pr_err("error %d\n", rc); in init_agc()
4712 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode, 0); in init_agc()
4713 if (rc != 0) { in init_agc()
4714 pr_err("error %d\n", rc); in init_agc()
4726 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_RF__A, agc_rf, 0); in init_agc()
4727 if (rc != 0) { in init_agc()
4728 pr_err("error %d\n", rc); in init_agc()
4731 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_IF__A, agc_if, 0); in init_agc()
4732 if (rc != 0) { in init_agc()
4733 pr_err("error %d\n", rc); in init_agc()
4738 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); in init_agc()
4739 if (rc != 0) { in init_agc()
4740 pr_err("error %d\n", rc); in init_agc()
4745 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, data, 0); in init_agc()
4746 if (rc != 0) { in init_agc()
4747 pr_err("error %d\n", rc); in init_agc()
4753 return rc; in init_agc()
4770 int rc; in set_frequency() local
4841 rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0); in set_frequency()
4842 if (rc != 0) { in set_frequency()
4843 pr_err("error %d\n", rc); in set_frequency()
4851 return rc; in set_frequency()
4867 int rc; in get_acc_pkt_err() local
4877 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data, 0); in get_acc_pkt_err()
4878 if (rc != 0) { in get_acc_pkt_err()
4879 pr_err("error %d\n", rc); in get_acc_pkt_err()
4899 return rc; in get_acc_pkt_err()
4920 int rc; in set_agc_rf() local
4948 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); in set_agc_rf()
4949 if (rc != 0) { in set_agc_rf()
4950 pr_err("error %d\n", rc); in set_agc_rf()
4954 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); in set_agc_rf()
4955 if (rc != 0) { in set_agc_rf()
4956 pr_err("error %d\n", rc); in set_agc_rf()
4961 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); in set_agc_rf()
4962 if (rc != 0) { in set_agc_rf()
4963 pr_err("error %d\n", rc); in set_agc_rf()
4978 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); in set_agc_rf()
4979 if (rc != 0) { in set_agc_rf()
4980 pr_err("error %d\n", rc); in set_agc_rf()
4985 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0); in set_agc_rf()
4986 if (rc != 0) { in set_agc_rf()
4987 pr_err("error %d\n", rc); in set_agc_rf()
4991 …rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAG… in set_agc_rf()
4992 if (rc != 0) { in set_agc_rf()
4993 pr_err("error %d\n", rc); in set_agc_rf()
5008 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->top, 0); in set_agc_rf()
5009 if (rc != 0) { in set_agc_rf()
5010 pr_err("error %d\n", rc); in set_agc_rf()
5013 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, agc_settings->top, 0); in set_agc_rf()
5014 if (rc != 0) { in set_agc_rf()
5015 pr_err("error %d\n", rc); in set_agc_rf()
5021 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, agc_settings->cut_off_current, 0); in set_agc_rf()
5022 if (rc != 0) { in set_agc_rf()
5023 pr_err("error %d\n", rc); in set_agc_rf()
5030 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); in set_agc_rf()
5031 if (rc != 0) { in set_agc_rf()
5032 pr_err("error %d\n", rc); in set_agc_rf()
5036 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); in set_agc_rf()
5037 if (rc != 0) { in set_agc_rf()
5038 pr_err("error %d\n", rc); in set_agc_rf()
5043 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); in set_agc_rf()
5044 if (rc != 0) { in set_agc_rf()
5045 pr_err("error %d\n", rc); in set_agc_rf()
5053 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); in set_agc_rf()
5054 if (rc != 0) { in set_agc_rf()
5055 pr_err("error %d\n", rc); in set_agc_rf()
5060 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, agc_settings->output_level, 0); in set_agc_rf()
5061 if (rc != 0) { in set_agc_rf()
5062 pr_err("error %d\n", rc); in set_agc_rf()
5069 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); in set_agc_rf()
5070 if (rc != 0) { in set_agc_rf()
5071 pr_err("error %d\n", rc); in set_agc_rf()
5075 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); in set_agc_rf()
5076 if (rc != 0) { in set_agc_rf()
5077 pr_err("error %d\n", rc); in set_agc_rf()
5082 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); in set_agc_rf()
5083 if (rc != 0) { in set_agc_rf()
5084 pr_err("error %d\n", rc); in set_agc_rf()
5088 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); in set_agc_rf()
5089 if (rc != 0) { in set_agc_rf()
5090 pr_err("error %d\n", rc); in set_agc_rf()
5117 return rc; in set_agc_rf()
5136 int rc; in set_agc_if() local
5161 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); in set_agc_if()
5162 if (rc != 0) { in set_agc_if()
5163 pr_err("error %d\n", rc); in set_agc_if()
5167 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); in set_agc_if()
5168 if (rc != 0) { in set_agc_if()
5169 pr_err("error %d\n", rc); in set_agc_if()
5174 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); in set_agc_if()
5175 if (rc != 0) { in set_agc_if()
5176 pr_err("error %d\n", rc); in set_agc_if()
5192 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); in set_agc_if()
5193 if (rc != 0) { in set_agc_if()
5194 pr_err("error %d\n", rc); in set_agc_if()
5199 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0); in set_agc_if()
5200 if (rc != 0) { in set_agc_if()
5201 pr_err("error %d\n", rc); in set_agc_if()
5205 …rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IA… in set_agc_if()
5206 if (rc != 0) { in set_agc_if()
5207 pr_err("error %d\n", rc); in set_agc_if()
5222 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_settings->top, 0); in set_agc_if()
5223 if (rc != 0) { in set_agc_if()
5224 pr_err("error %d\n", rc); in set_agc_if()
5227 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, p_agc_settings->top, 0); in set_agc_if()
5228 if (rc != 0) { in set_agc_if()
5229 pr_err("error %d\n", rc); in set_agc_if()
5233 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 0, 0); in set_agc_if()
5234 if (rc != 0) { in set_agc_if()
5235 pr_err("error %d\n", rc); in set_agc_if()
5238 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, 0); in set_agc_if()
5239 if (rc != 0) { in set_agc_if()
5240 pr_err("error %d\n", rc); in set_agc_if()
5249 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); in set_agc_if()
5250 if (rc != 0) { in set_agc_if()
5251 pr_err("error %d\n", rc); in set_agc_if()
5255 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); in set_agc_if()
5256 if (rc != 0) { in set_agc_if()
5257 pr_err("error %d\n", rc); in set_agc_if()
5262 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); in set_agc_if()
5263 if (rc != 0) { in set_agc_if()
5264 pr_err("error %d\n", rc); in set_agc_if()
5273 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); in set_agc_if()
5274 if (rc != 0) { in set_agc_if()
5275 pr_err("error %d\n", rc); in set_agc_if()
5280 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->output_level, 0); in set_agc_if()
5281 if (rc != 0) { in set_agc_if()
5282 pr_err("error %d\n", rc); in set_agc_if()
5290 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); in set_agc_if()
5291 if (rc != 0) { in set_agc_if()
5292 pr_err("error %d\n", rc); in set_agc_if()
5296 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); in set_agc_if()
5297 if (rc != 0) { in set_agc_if()
5298 pr_err("error %d\n", rc); in set_agc_if()
5303 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); in set_agc_if()
5304 if (rc != 0) { in set_agc_if()
5305 pr_err("error %d\n", rc); in set_agc_if()
5310 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); in set_agc_if()
5311 if (rc != 0) { in set_agc_if()
5312 pr_err("error %d\n", rc); in set_agc_if()
5321 rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, agc_settings->top, 0); in set_agc_if()
5322 if (rc != 0) { in set_agc_if()
5323 pr_err("error %d\n", rc); in set_agc_if()
5346 return rc; in set_agc_if()
5360 int rc; in set_iqm_af() local
5365 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); in set_iqm_af()
5366 if (rc != 0) { in set_iqm_af()
5367 pr_err("error %d\n", rc); in set_iqm_af()
5374 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); in set_iqm_af()
5375 if (rc != 0) { in set_iqm_af()
5376 pr_err("error %d\n", rc); in set_iqm_af()
5382 return rc; in set_iqm_af()
5412 int rc; in power_down_vsb() local
5425 rc = scu_command(dev_addr, &cmd_scu); in power_down_vsb()
5426 if (rc != 0) { in power_down_vsb()
5427 pr_err("error %d\n", rc); in power_down_vsb()
5432 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); in power_down_vsb()
5433 if (rc != 0) { in power_down_vsb()
5434 pr_err("error %d\n", rc); in power_down_vsb()
5437 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0); in power_down_vsb()
5438 if (rc != 0) { in power_down_vsb()
5439 pr_err("error %d\n", rc); in power_down_vsb()
5443 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); in power_down_vsb()
5444 if (rc != 0) { in power_down_vsb()
5445 pr_err("error %d\n", rc); in power_down_vsb()
5448 rc = set_iqm_af(demod, false); in power_down_vsb()
5449 if (rc != 0) { in power_down_vsb()
5450 pr_err("error %d\n", rc); in power_down_vsb()
5454 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); in power_down_vsb()
5455 if (rc != 0) { in power_down_vsb()
5456 pr_err("error %d\n", rc); in power_down_vsb()
5459 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); in power_down_vsb()
5460 if (rc != 0) { in power_down_vsb()
5461 pr_err("error %d\n", rc); in power_down_vsb()
5464 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); in power_down_vsb()
5465 if (rc != 0) { in power_down_vsb()
5466 pr_err("error %d\n", rc); in power_down_vsb()
5469 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); in power_down_vsb()
5470 if (rc != 0) { in power_down_vsb()
5471 pr_err("error %d\n", rc); in power_down_vsb()
5474 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); in power_down_vsb()
5475 if (rc != 0) { in power_down_vsb()
5476 pr_err("error %d\n", rc); in power_down_vsb()
5482 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); in power_down_vsb()
5483 if (rc != 0) { in power_down_vsb()
5484 pr_err("error %d\n", rc); in power_down_vsb()
5490 return rc; in power_down_vsb()
5502 int rc; in set_vsb_leak_n_gain() local
5693 …rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, sizeof(vsb_ffe_leak_g… in set_vsb_leak_n_gain()
5694 if (rc != 0) { in set_vsb_leak_n_gain()
5695 pr_err("error %d\n", rc); in set_vsb_leak_n_gain()
5698 …rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, sizeof(vsb_ffe_leak_gain_… in set_vsb_leak_n_gain()
5699 if (rc != 0) { in set_vsb_leak_n_gain()
5700 pr_err("error %d\n", rc); in set_vsb_leak_n_gain()
5706 return rc; in set_vsb_leak_n_gain()
5719 int rc; in set_vsb() local
5761 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); in set_vsb()
5762 if (rc != 0) { in set_vsb()
5763 pr_err("error %d\n", rc); in set_vsb()
5766 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0); in set_vsb()
5767 if (rc != 0) { in set_vsb()
5768 pr_err("error %d\n", rc); in set_vsb()
5771 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); in set_vsb()
5772 if (rc != 0) { in set_vsb()
5773 pr_err("error %d\n", rc); in set_vsb()
5776 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); in set_vsb()
5777 if (rc != 0) { in set_vsb()
5778 pr_err("error %d\n", rc); in set_vsb()
5781 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); in set_vsb()
5782 if (rc != 0) { in set_vsb()
5783 pr_err("error %d\n", rc); in set_vsb()
5786 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); in set_vsb()
5787 if (rc != 0) { in set_vsb()
5788 pr_err("error %d\n", rc); in set_vsb()
5791 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); in set_vsb()
5792 if (rc != 0) { in set_vsb()
5793 pr_err("error %d\n", rc); in set_vsb()
5804 rc = scu_command(dev_addr, &cmd_scu); in set_vsb()
5805 if (rc != 0) { in set_vsb()
5806 pr_err("error %d\n", rc); in set_vsb()
5810 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_DCF_BYPASS__A, 1, 0); in set_vsb()
5811 if (rc != 0) { in set_vsb()
5812 pr_err("error %d\n", rc); in set_vsb()
5815 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB, 0); in set_vsb()
5816 if (rc != 0) { in set_vsb()
5817 pr_err("error %d\n", rc); in set_vsb()
5820 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB, 0); in set_vsb()
5821 if (rc != 0) { in set_vsb()
5822 pr_err("error %d\n", rc); in set_vsb()
5826 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0); in set_vsb()
5827 if (rc != 0) { in set_vsb()
5828 pr_err("error %d\n", rc); in set_vsb()
5831 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4, 0); in set_vsb()
5832 if (rc != 0) { in set_vsb()
5833 pr_err("error %d\n", rc); in set_vsb()
5836 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 1, 0); in set_vsb()
5837 if (rc != 0) { in set_vsb()
5838 pr_err("error %d\n", rc); in set_vsb()
5842 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_CROUT_ENA__A, 1, 0); in set_vsb()
5843 if (rc != 0) { in set_vsb()
5844 pr_err("error %d\n", rc); in set_vsb()
5847 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, 28, 0); in set_vsb()
5848 if (rc != 0) { in set_vsb()
5849 pr_err("error %d\n", rc); in set_vsb()
5852 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ACTIVE__A, 0, 0); in set_vsb()
5853 if (rc != 0) { in set_vsb()
5854 pr_err("error %d\n", rc); in set_vsb()
5857 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0); in set_vsb()
5858 if (rc != 0) { in set_vsb()
5859 pr_err("error %d\n", rc); in set_vsb()
5862 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0); in set_vsb()
5863 if (rc != 0) { in set_vsb()
5864 pr_err("error %d\n", rc); in set_vsb()
5867 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M, 0); in set_vsb()
5868 if (rc != 0) { in set_vsb()
5869 pr_err("error %d\n", rc); in set_vsb()
5872 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE__A, 1393, 0); in set_vsb()
5873 if (rc != 0) { in set_vsb()
5874 pr_err("error %d\n", rc); in set_vsb()
5877 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0); in set_vsb()
5878 if (rc != 0) { in set_vsb()
5879 pr_err("error %d\n", rc); in set_vsb()
5882 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0); in set_vsb()
5883 if (rc != 0) { in set_vsb()
5884 pr_err("error %d\n", rc); in set_vsb()
5888 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re)… in set_vsb()
5889 if (rc != 0) { in set_vsb()
5890 pr_err("error %d\n", rc); in set_vsb()
5893 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re)… in set_vsb()
5894 if (rc != 0) { in set_vsb()
5895 pr_err("error %d\n", rc); in set_vsb()
5899 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BNTHRESH__A, 330, 0); in set_vsb()
5900 if (rc != 0) { in set_vsb()
5901 pr_err("error %d\n", rc); in set_vsb()
5904 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CLPLASTNUM__A, 90, 0); in set_vsb()
5905 if (rc != 0) { in set_vsb()
5906 pr_err("error %d\n", rc); in set_vsb()
5909 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042, 0); in set_vsb()
5910 if (rc != 0) { in set_vsb()
5911 pr_err("error %d\n", rc); in set_vsb()
5914 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053, 0); in set_vsb()
5915 if (rc != 0) { in set_vsb()
5916 pr_err("error %d\n", rc); in set_vsb()
5919 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_EQCTRL__A, 0x1, 0); in set_vsb()
5920 if (rc != 0) { in set_vsb()
5921 pr_err("error %d\n", rc); in set_vsb()
5924 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0); in set_vsb()
5925 if (rc != 0) { in set_vsb()
5926 pr_err("error %d\n", rc); in set_vsb()
5931 rc = drxj_dap_write_reg16(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D, 0); in set_vsb()
5932 if (rc != 0) { in set_vsb()
5933 pr_err("error %d\n", rc); in set_vsb()
5938 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0); in set_vsb()
5939 if (rc != 0) { in set_vsb()
5940 pr_err("error %d\n", rc); in set_vsb()
5944 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_E… in set_vsb()
5945 if (rc != 0) { in set_vsb()
5946 pr_err("error %d\n", rc); in set_vsb()
5952 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0); in set_vsb()
5953 if (rc != 0) { in set_vsb()
5954 pr_err("error %d\n", rc); in set_vsb()
5957 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 470, 0); in set_vsb()
5958 if (rc != 0) { in set_vsb()
5959 pr_err("error %d\n", rc); in set_vsb()
5962 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0); in set_vsb()
5963 if (rc != 0) { in set_vsb()
5964 pr_err("error %d\n", rc); in set_vsb()
5967 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4, 0); in set_vsb()
5968 if (rc != 0) { in set_vsb()
5969 pr_err("error %d\n", rc); in set_vsb()
5975 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0); in set_vsb()
5976 if (rc != 0) { in set_vsb()
5977 pr_err("error %d\n", rc); in set_vsb()
5980 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__… in set_vsb()
5981 if (rc != 0) { in set_vsb()
5982 pr_err("error %d\n", rc); in set_vsb()
5987 rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_LO__A, 0, 0); in set_vsb()
5988 if (rc != 0) { in set_vsb()
5989 pr_err("error %d\n", rc); in set_vsb()
5992 rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_HI__A, 3, 0); in set_vsb()
5993 if (rc != 0) { in set_vsb()
5994 pr_err("error %d\n", rc); in set_vsb()
5997 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MODE__A, 0, 0); in set_vsb()
5998 if (rc != 0) { in set_vsb()
5999 pr_err("error %d\n", rc); in set_vsb()
6003 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD, 0); in set_vsb()
6004 if (rc != 0) { in set_vsb()
6005 pr_err("error %d\n", rc); in set_vsb()
6008 …rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE, 0… in set_vsb()
6009 if (rc != 0) { in set_vsb()
6010 pr_err("error %d\n", rc); in set_vsb()
6015 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD, 0); in set_vsb()
6016 if (rc != 0) { in set_vsb()
6017 pr_err("error %d\n", rc); in set_vsb()
6020 rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0); in set_vsb()
6021 if (rc != 0) { in set_vsb()
6022 pr_err("error %d\n", rc); in set_vsb()
6025 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0); in set_vsb()
6026 if (rc != 0) { in set_vsb()
6027 pr_err("error %d\n", rc); in set_vsb()
6030 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0); in set_vsb()
6031 if (rc != 0) { in set_vsb()
6032 pr_err("error %d\n", rc); in set_vsb()
6036 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CKGN1TRK__A, 128, 0); in set_vsb()
6037 if (rc != 0) { in set_vsb()
6038 pr_err("error %d\n", rc); in set_vsb()
6043 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0); in set_vsb()
6044 if (rc != 0) { in set_vsb()
6045 pr_err("error %d\n", rc); in set_vsb()
6051 rc = set_iqm_af(demod, true); in set_vsb()
6052 if (rc != 0) { in set_vsb()
6053 pr_err("error %d\n", rc); in set_vsb()
6056 rc = adc_synchronization(demod); in set_vsb()
6057 if (rc != 0) { in set_vsb()
6058 pr_err("error %d\n", rc); in set_vsb()
6062 rc = init_agc(demod); in set_vsb()
6063 if (rc != 0) { in set_vsb()
6064 pr_err("error %d\n", rc); in set_vsb()
6067 rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false); in set_vsb()
6068 if (rc != 0) { in set_vsb()
6069 pr_err("error %d\n", rc); in set_vsb()
6072 rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false); in set_vsb()
6073 if (rc != 0) { in set_vsb()
6074 pr_err("error %d\n", rc); in set_vsb()
6083 rc = ctrl_set_cfg_afe_gain(demod, &vsb_pga_cfg); in set_vsb()
6084 if (rc != 0) { in set_vsb()
6085 pr_err("error %d\n", rc); in set_vsb()
6089 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg)); in set_vsb()
6090 if (rc != 0) { in set_vsb()
6091 pr_err("error %d\n", rc); in set_vsb()
6096 rc = set_mpegtei_handling(demod); in set_vsb()
6097 if (rc != 0) { in set_vsb()
6098 pr_err("error %d\n", rc); in set_vsb()
6101 rc = bit_reverse_mpeg_output(demod); in set_vsb()
6102 if (rc != 0) { in set_vsb()
6103 pr_err("error %d\n", rc); in set_vsb()
6106 rc = set_mpeg_start_width(demod); in set_vsb()
6107 if (rc != 0) { in set_vsb()
6108 pr_err("error %d\n", rc); in set_vsb()
6119 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); in set_vsb()
6120 if (rc != 0) { in set_vsb()
6121 pr_err("error %d\n", rc); in set_vsb()
6134 rc = scu_command(dev_addr, &cmd_scu); in set_vsb()
6135 if (rc != 0) { in set_vsb()
6136 pr_err("error %d\n", rc); in set_vsb()
6140 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004, 0); in set_vsb()
6141 if (rc != 0) { in set_vsb()
6142 pr_err("error %d\n", rc); in set_vsb()
6145 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2, 0); in set_vsb()
6146 if (rc != 0) { in set_vsb()
6147 pr_err("error %d\n", rc); in set_vsb()
6150 …rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_S… in set_vsb()
6151 if (rc != 0) { in set_vsb()
6152 pr_err("error %d\n", rc); in set_vsb()
6155 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142, 0); in set_vsb()
6156 if (rc != 0) { in set_vsb()
6157 pr_err("error %d\n", rc); in set_vsb()
6160 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640, 0); in set_vsb()
6161 if (rc != 0) { in set_vsb()
6162 pr_err("error %d\n", rc); in set_vsb()
6165 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1ACQ__A, 4, 0); in set_vsb()
6166 if (rc != 0) { in set_vsb()
6167 pr_err("error %d\n", rc); in set_vsb()
6170 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 2, 0); in set_vsb()
6171 if (rc != 0) { in set_vsb()
6172 pr_err("error %d\n", rc); in set_vsb()
6175 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN2TRK__A, 3, 0); in set_vsb()
6176 if (rc != 0) { in set_vsb()
6177 pr_err("error %d\n", rc); in set_vsb()
6188 rc = scu_command(dev_addr, &cmd_scu); in set_vsb()
6189 if (rc != 0) { in set_vsb()
6190 pr_err("error %d\n", rc); in set_vsb()
6194 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0); in set_vsb()
6195 if (rc != 0) { in set_vsb()
6196 pr_err("error %d\n", rc); in set_vsb()
6199 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE, 0); in set_vsb()
6200 if (rc != 0) { in set_vsb()
6201 pr_err("error %d\n", rc); in set_vsb()
6204 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0); in set_vsb()
6205 if (rc != 0) { in set_vsb()
6206 pr_err("error %d\n", rc); in set_vsb()
6212 return rc; in set_vsb()
6223 int rc; in get_vsb_post_rs_pck_err() local
6230 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &data, 0); in get_vsb_post_rs_pck_err()
6231 if (rc != 0) { in get_vsb_post_rs_pck_err()
6232 pr_err("error %d\n", rc); in get_vsb_post_rs_pck_err()
6251 return rc; in get_vsb_post_rs_pck_err()
6262 int rc; in get_vs_bpost_viterbi_ber() local
6269 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &data, 0); in get_vs_bpost_viterbi_ber()
6270 if (rc != 0) { in get_vs_bpost_viterbi_ber()
6271 pr_err("error %d\n", rc); in get_vs_bpost_viterbi_ber()
6296 return rc; in get_vs_bpost_viterbi_ber()
6308 int rc; in get_vs_bpre_viterbi_ber() local
6310 rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data, 0); in get_vs_bpre_viterbi_ber()
6311 if (rc != 0) { in get_vs_bpre_viterbi_ber()
6312 pr_err("error %d\n", rc); in get_vs_bpre_viterbi_ber()
6328 int rc; in get_vsbmer() local
6331 rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi, 0); in get_vsbmer()
6332 if (rc != 0) { in get_vsbmer()
6333 pr_err("error %d\n", rc); in get_vsbmer()
6341 return rc; in get_vsbmer()
6370 int rc; in power_down_qam() local
6381 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); in power_down_qam()
6382 if (rc != 0) { in power_down_qam()
6383 pr_err("error %d\n", rc); in power_down_qam()
6386 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0); in power_down_qam()
6387 if (rc != 0) { in power_down_qam()
6388 pr_err("error %d\n", rc); in power_down_qam()
6398 rc = scu_command(dev_addr, &cmd_scu); in power_down_qam()
6399 if (rc != 0) { in power_down_qam()
6400 pr_err("error %d\n", rc); in power_down_qam()
6405 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); in power_down_qam()
6406 if (rc != 0) { in power_down_qam()
6407 pr_err("error %d\n", rc); in power_down_qam()
6410 rc = set_iqm_af(demod, false); in power_down_qam()
6411 if (rc != 0) { in power_down_qam()
6412 pr_err("error %d\n", rc); in power_down_qam()
6416 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); in power_down_qam()
6417 if (rc != 0) { in power_down_qam()
6418 pr_err("error %d\n", rc); in power_down_qam()
6421 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); in power_down_qam()
6422 if (rc != 0) { in power_down_qam()
6423 pr_err("error %d\n", rc); in power_down_qam()
6426 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); in power_down_qam()
6427 if (rc != 0) { in power_down_qam()
6428 pr_err("error %d\n", rc); in power_down_qam()
6431 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); in power_down_qam()
6432 if (rc != 0) { in power_down_qam()
6433 pr_err("error %d\n", rc); in power_down_qam()
6436 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); in power_down_qam()
6437 if (rc != 0) { in power_down_qam()
6438 pr_err("error %d\n", rc); in power_down_qam()
6446 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); in power_down_qam()
6447 if (rc != 0) { in power_down_qam()
6448 pr_err("error %d\n", rc); in power_down_qam()
6454 return rc; in power_down_qam()
6482 int rc; in set_qam_measurement() local
6576 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16)fec_oc_snc_fail_period, 0); in set_qam_measurement()
6577 if (rc != 0) { in set_qam_measurement()
6578 pr_err("error %d\n", rc); in set_qam_measurement()
6581 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, (u16)fec_rs_period, 0); in set_qam_measurement()
6582 if (rc != 0) { in set_qam_measurement()
6583 pr_err("error %d\n", rc); in set_qam_measurement()
6586 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale, 0); in set_qam_measurement()
6587 if (rc != 0) { in set_qam_measurement()
6588 pr_err("error %d\n", rc); in set_qam_measurement()
6593 rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0); in set_qam_measurement()
6594 if (rc != 0) { in set_qam_measurement()
6595 pr_err("error %d\n", rc); in set_qam_measurement()
6598 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0); in set_qam_measurement()
6599 if (rc != 0) { in set_qam_measurement()
6600 pr_err("error %d\n", rc); in set_qam_measurement()
6603 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0); in set_qam_measurement()
6604 if (rc != 0) { in set_qam_measurement()
6605 pr_err("error %d\n", rc); in set_qam_measurement()
6650 rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PERIOD__A, (u16)qam_vd_period, 0); in set_qam_measurement()
6651 if (rc != 0) { in set_qam_measurement()
6652 pr_err("error %d\n", rc); in set_qam_measurement()
6655 rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PRESCALE__A, qam_vd_prescale, 0); in set_qam_measurement()
6656 if (rc != 0) { in set_qam_measurement()
6657 pr_err("error %d\n", rc); in set_qam_measurement()
6666 return rc; in set_qam_measurement()
6680 int rc; in set_qam16() local
6698 …rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq… in set_qam16()
6699 if (rc != 0) { in set_qam16()
6700 pr_err("error %d\n", rc); in set_qam16()
6703 …rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)… in set_qam16()
6704 if (rc != 0) { in set_qam16()
6705 pr_err("error %d\n", rc); in set_qam16()
6709 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 140, 0); in set_qam16()
6710 if (rc != 0) { in set_qam16()
6711 pr_err("error %d\n", rc); in set_qam16()
6714 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0); in set_qam16()
6715 if (rc != 0) { in set_qam16()
6716 pr_err("error %d\n", rc); in set_qam16()
6719 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 120, 0); in set_qam16()
6720 if (rc != 0) { in set_qam16()
6721 pr_err("error %d\n", rc); in set_qam16()
6724 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 230, 0); in set_qam16()
6725 if (rc != 0) { in set_qam16()
6726 pr_err("error %d\n", rc); in set_qam16()
6729 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 95, 0); in set_qam16()
6730 if (rc != 0) { in set_qam16()
6731 pr_err("error %d\n", rc); in set_qam16()
6734 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 105, 0); in set_qam16()
6735 if (rc != 0) { in set_qam16()
6736 pr_err("error %d\n", rc); in set_qam16()
6740 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); in set_qam16()
6741 if (rc != 0) { in set_qam16()
6742 pr_err("error %d\n", rc); in set_qam16()
6745 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0); in set_qam16()
6746 if (rc != 0) { in set_qam16()
6747 pr_err("error %d\n", rc); in set_qam16()
6750 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); in set_qam16()
6751 if (rc != 0) { in set_qam16()
6752 pr_err("error %d\n", rc); in set_qam16()
6756 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16, 0); in set_qam16()
6757 if (rc != 0) { in set_qam16()
6758 pr_err("error %d\n", rc); in set_qam16()
6761 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220, 0); in set_qam16()
6762 if (rc != 0) { in set_qam16()
6763 pr_err("error %d\n", rc); in set_qam16()
6766 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25, 0); in set_qam16()
6767 if (rc != 0) { in set_qam16()
6768 pr_err("error %d\n", rc); in set_qam16()
6771 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6, 0); in set_qam16()
6772 if (rc != 0) { in set_qam16()
6773 pr_err("error %d\n", rc); in set_qam16()
6776 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0); in set_qam16()
6777 if (rc != 0) { in set_qam16()
6778 pr_err("error %d\n", rc); in set_qam16()
6781 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0); in set_qam16()
6782 if (rc != 0) { in set_qam16()
6783 pr_err("error %d\n", rc); in set_qam16()
6786 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0); in set_qam16()
6787 if (rc != 0) { in set_qam16()
6788 pr_err("error %d\n", rc); in set_qam16()
6792 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); in set_qam16()
6793 if (rc != 0) { in set_qam16()
6794 pr_err("error %d\n", rc); in set_qam16()
6797 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); in set_qam16()
6798 if (rc != 0) { in set_qam16()
6799 pr_err("error %d\n", rc); in set_qam16()
6802 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); in set_qam16()
6803 if (rc != 0) { in set_qam16()
6804 pr_err("error %d\n", rc); in set_qam16()
6807 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0); in set_qam16()
6808 if (rc != 0) { in set_qam16()
6809 pr_err("error %d\n", rc); in set_qam16()
6812 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); in set_qam16()
6813 if (rc != 0) { in set_qam16()
6814 pr_err("error %d\n", rc); in set_qam16()
6817 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); in set_qam16()
6818 if (rc != 0) { in set_qam16()
6819 pr_err("error %d\n", rc); in set_qam16()
6822 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0); in set_qam16()
6823 if (rc != 0) { in set_qam16()
6824 pr_err("error %d\n", rc); in set_qam16()
6827 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0); in set_qam16()
6828 if (rc != 0) { in set_qam16()
6829 pr_err("error %d\n", rc); in set_qam16()
6832 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); in set_qam16()
6833 if (rc != 0) { in set_qam16()
6834 pr_err("error %d\n", rc); in set_qam16()
6837 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); in set_qam16()
6838 if (rc != 0) { in set_qam16()
6839 pr_err("error %d\n", rc); in set_qam16()
6842 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); in set_qam16()
6843 if (rc != 0) { in set_qam16()
6844 pr_err("error %d\n", rc); in set_qam16()
6847 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); in set_qam16()
6848 if (rc != 0) { in set_qam16()
6849 pr_err("error %d\n", rc); in set_qam16()
6852 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); in set_qam16()
6853 if (rc != 0) { in set_qam16()
6854 pr_err("error %d\n", rc); in set_qam16()
6857 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); in set_qam16()
6858 if (rc != 0) { in set_qam16()
6859 pr_err("error %d\n", rc); in set_qam16()
6862 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); in set_qam16()
6863 if (rc != 0) { in set_qam16()
6864 pr_err("error %d\n", rc); in set_qam16()
6867 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); in set_qam16()
6868 if (rc != 0) { in set_qam16()
6869 pr_err("error %d\n", rc); in set_qam16()
6872 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 240, 0); in set_qam16()
6873 if (rc != 0) { in set_qam16()
6874 pr_err("error %d\n", rc); in set_qam16()
6877 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); in set_qam16()
6878 if (rc != 0) { in set_qam16()
6879 pr_err("error %d\n", rc); in set_qam16()
6882 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); in set_qam16()
6883 if (rc != 0) { in set_qam16()
6884 pr_err("error %d\n", rc); in set_qam16()
6887 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0); in set_qam16()
6888 if (rc != 0) { in set_qam16()
6889 pr_err("error %d\n", rc); in set_qam16()
6893 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960, 0); in set_qam16()
6894 if (rc != 0) { in set_qam16()
6895 pr_err("error %d\n", rc); in set_qam16()
6901 return rc; in set_qam16()
6915 int rc; in set_qam32() local
6933 …rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq… in set_qam32()
6934 if (rc != 0) { in set_qam32()
6935 pr_err("error %d\n", rc); in set_qam32()
6938 …rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)… in set_qam32()
6939 if (rc != 0) { in set_qam32()
6940 pr_err("error %d\n", rc); in set_qam32()
6944 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 90, 0); in set_qam32()
6945 if (rc != 0) { in set_qam32()
6946 pr_err("error %d\n", rc); in set_qam32()
6949 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0); in set_qam32()
6950 if (rc != 0) { in set_qam32()
6951 pr_err("error %d\n", rc); in set_qam32()
6954 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); in set_qam32()
6955 if (rc != 0) { in set_qam32()
6956 pr_err("error %d\n", rc); in set_qam32()
6959 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 170, 0); in set_qam32()
6960 if (rc != 0) { in set_qam32()
6961 pr_err("error %d\n", rc); in set_qam32()
6964 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); in set_qam32()
6965 if (rc != 0) { in set_qam32()
6966 pr_err("error %d\n", rc); in set_qam32()
6969 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0); in set_qam32()
6970 if (rc != 0) { in set_qam32()
6971 pr_err("error %d\n", rc); in set_qam32()
6975 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); in set_qam32()
6976 if (rc != 0) { in set_qam32()
6977 pr_err("error %d\n", rc); in set_qam32()
6980 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0); in set_qam32()
6981 if (rc != 0) { in set_qam32()
6982 pr_err("error %d\n", rc); in set_qam32()
6985 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); in set_qam32()
6986 if (rc != 0) { in set_qam32()
6987 pr_err("error %d\n", rc); in set_qam32()
6991 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0); in set_qam32()
6992 if (rc != 0) { in set_qam32()
6993 pr_err("error %d\n", rc); in set_qam32()
6996 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140, 0); in set_qam32()
6997 if (rc != 0) { in set_qam32()
6998 pr_err("error %d\n", rc); in set_qam32()
7001 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0); in set_qam32()
7002 if (rc != 0) { in set_qam32()
7003 pr_err("error %d\n", rc); in set_qam32()
7006 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0); in set_qam32()
7007 if (rc != 0) { in set_qam32()
7008 pr_err("error %d\n", rc); in set_qam32()
7011 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0); in set_qam32()
7012 if (rc != 0) { in set_qam32()
7013 pr_err("error %d\n", rc); in set_qam32()
7016 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0); in set_qam32()
7017 if (rc != 0) { in set_qam32()
7018 pr_err("error %d\n", rc); in set_qam32()
7021 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0); in set_qam32()
7022 if (rc != 0) { in set_qam32()
7023 pr_err("error %d\n", rc); in set_qam32()
7027 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); in set_qam32()
7028 if (rc != 0) { in set_qam32()
7029 pr_err("error %d\n", rc); in set_qam32()
7032 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); in set_qam32()
7033 if (rc != 0) { in set_qam32()
7034 pr_err("error %d\n", rc); in set_qam32()
7037 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); in set_qam32()
7038 if (rc != 0) { in set_qam32()
7039 pr_err("error %d\n", rc); in set_qam32()
7042 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0); in set_qam32()
7043 if (rc != 0) { in set_qam32()
7044 pr_err("error %d\n", rc); in set_qam32()
7047 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); in set_qam32()
7048 if (rc != 0) { in set_qam32()
7049 pr_err("error %d\n", rc); in set_qam32()
7052 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); in set_qam32()
7053 if (rc != 0) { in set_qam32()
7054 pr_err("error %d\n", rc); in set_qam32()
7057 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0); in set_qam32()
7058 if (rc != 0) { in set_qam32()
7059 pr_err("error %d\n", rc); in set_qam32()
7062 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0); in set_qam32()
7063 if (rc != 0) { in set_qam32()
7064 pr_err("error %d\n", rc); in set_qam32()
7067 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); in set_qam32()
7068 if (rc != 0) { in set_qam32()
7069 pr_err("error %d\n", rc); in set_qam32()
7072 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); in set_qam32()
7073 if (rc != 0) { in set_qam32()
7074 pr_err("error %d\n", rc); in set_qam32()
7077 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); in set_qam32()
7078 if (rc != 0) { in set_qam32()
7079 pr_err("error %d\n", rc); in set_qam32()
7082 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); in set_qam32()
7083 if (rc != 0) { in set_qam32()
7084 pr_err("error %d\n", rc); in set_qam32()
7087 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); in set_qam32()
7088 if (rc != 0) { in set_qam32()
7089 pr_err("error %d\n", rc); in set_qam32()
7092 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); in set_qam32()
7093 if (rc != 0) { in set_qam32()
7094 pr_err("error %d\n", rc); in set_qam32()
7097 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); in set_qam32()
7098 if (rc != 0) { in set_qam32()
7099 pr_err("error %d\n", rc); in set_qam32()
7102 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); in set_qam32()
7103 if (rc != 0) { in set_qam32()
7104 pr_err("error %d\n", rc); in set_qam32()
7107 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 176, 0); in set_qam32()
7108 if (rc != 0) { in set_qam32()
7109 pr_err("error %d\n", rc); in set_qam32()
7112 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); in set_qam32()
7113 if (rc != 0) { in set_qam32()
7114 pr_err("error %d\n", rc); in set_qam32()
7117 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); in set_qam32()
7118 if (rc != 0) { in set_qam32()
7119 pr_err("error %d\n", rc); in set_qam32()
7122 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8, 0); in set_qam32()
7123 if (rc != 0) { in set_qam32()
7124 pr_err("error %d\n", rc); in set_qam32()
7128 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480, 0); in set_qam32()
7129 if (rc != 0) { in set_qam32()
7130 pr_err("error %d\n", rc); in set_qam32()
7136 return rc; in set_qam32()
7150 int rc; in set_qam64() local
7169 …rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq… in set_qam64()
7170 if (rc != 0) { in set_qam64()
7171 pr_err("error %d\n", rc); in set_qam64()
7174 …rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)… in set_qam64()
7175 if (rc != 0) { in set_qam64()
7176 pr_err("error %d\n", rc); in set_qam64()
7180 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105, 0); in set_qam64()
7181 if (rc != 0) { in set_qam64()
7182 pr_err("error %d\n", rc); in set_qam64()
7185 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); in set_qam64()
7186 if (rc != 0) { in set_qam64()
7187 pr_err("error %d\n", rc); in set_qam64()
7190 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); in set_qam64()
7191 if (rc != 0) { in set_qam64()
7192 pr_err("error %d\n", rc); in set_qam64()
7195 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 195, 0); in set_qam64()
7196 if (rc != 0) { in set_qam64()
7197 pr_err("error %d\n", rc); in set_qam64()
7200 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); in set_qam64()
7201 if (rc != 0) { in set_qam64()
7202 pr_err("error %d\n", rc); in set_qam64()
7205 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 84, 0); in set_qam64()
7206 if (rc != 0) { in set_qam64()
7207 pr_err("error %d\n", rc); in set_qam64()
7211 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); in set_qam64()
7212 if (rc != 0) { in set_qam64()
7213 pr_err("error %d\n", rc); in set_qam64()
7216 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0); in set_qam64()
7217 if (rc != 0) { in set_qam64()
7218 pr_err("error %d\n", rc); in set_qam64()
7221 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); in set_qam64()
7222 if (rc != 0) { in set_qam64()
7223 pr_err("error %d\n", rc); in set_qam64()
7227 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0); in set_qam64()
7228 if (rc != 0) { in set_qam64()
7229 pr_err("error %d\n", rc); in set_qam64()
7232 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141, 0); in set_qam64()
7233 if (rc != 0) { in set_qam64()
7234 pr_err("error %d\n", rc); in set_qam64()
7237 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7, 0); in set_qam64()
7238 if (rc != 0) { in set_qam64()
7239 pr_err("error %d\n", rc); in set_qam64()
7242 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0, 0); in set_qam64()
7243 if (rc != 0) { in set_qam64()
7244 pr_err("error %d\n", rc); in set_qam64()
7247 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0); in set_qam64()
7248 if (rc != 0) { in set_qam64()
7249 pr_err("error %d\n", rc); in set_qam64()
7252 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0); in set_qam64()
7253 if (rc != 0) { in set_qam64()
7254 pr_err("error %d\n", rc); in set_qam64()
7257 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0); in set_qam64()
7258 if (rc != 0) { in set_qam64()
7259 pr_err("error %d\n", rc); in set_qam64()
7263 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); in set_qam64()
7264 if (rc != 0) { in set_qam64()
7265 pr_err("error %d\n", rc); in set_qam64()
7268 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); in set_qam64()
7269 if (rc != 0) { in set_qam64()
7270 pr_err("error %d\n", rc); in set_qam64()
7273 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); in set_qam64()
7274 if (rc != 0) { in set_qam64()
7275 pr_err("error %d\n", rc); in set_qam64()
7278 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30, 0); in set_qam64()
7279 if (rc != 0) { in set_qam64()
7280 pr_err("error %d\n", rc); in set_qam64()
7283 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); in set_qam64()
7284 if (rc != 0) { in set_qam64()
7285 pr_err("error %d\n", rc); in set_qam64()
7288 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); in set_qam64()
7289 if (rc != 0) { in set_qam64()
7290 pr_err("error %d\n", rc); in set_qam64()
7293 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15, 0); in set_qam64()
7294 if (rc != 0) { in set_qam64()
7295 pr_err("error %d\n", rc); in set_qam64()
7298 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); in set_qam64()
7299 if (rc != 0) { in set_qam64()
7300 pr_err("error %d\n", rc); in set_qam64()
7303 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); in set_qam64()
7304 if (rc != 0) { in set_qam64()
7305 pr_err("error %d\n", rc); in set_qam64()
7308 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); in set_qam64()
7309 if (rc != 0) { in set_qam64()
7310 pr_err("error %d\n", rc); in set_qam64()
7313 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); in set_qam64()
7314 if (rc != 0) { in set_qam64()
7315 pr_err("error %d\n", rc); in set_qam64()
7318 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); in set_qam64()
7319 if (rc != 0) { in set_qam64()
7320 pr_err("error %d\n", rc); in set_qam64()
7323 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); in set_qam64()
7324 if (rc != 0) { in set_qam64()
7325 pr_err("error %d\n", rc); in set_qam64()
7328 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); in set_qam64()
7329 if (rc != 0) { in set_qam64()
7330 pr_err("error %d\n", rc); in set_qam64()
7333 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); in set_qam64()
7334 if (rc != 0) { in set_qam64()
7335 pr_err("error %d\n", rc); in set_qam64()
7338 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0); in set_qam64()
7339 if (rc != 0) { in set_qam64()
7340 pr_err("error %d\n", rc); in set_qam64()
7343 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 160, 0); in set_qam64()
7344 if (rc != 0) { in set_qam64()
7345 pr_err("error %d\n", rc); in set_qam64()
7348 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); in set_qam64()
7349 if (rc != 0) { in set_qam64()
7350 pr_err("error %d\n", rc); in set_qam64()
7353 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); in set_qam64()
7354 if (rc != 0) { in set_qam64()
7355 pr_err("error %d\n", rc); in set_qam64()
7358 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0); in set_qam64()
7359 if (rc != 0) { in set_qam64()
7360 pr_err("error %d\n", rc); in set_qam64()
7364 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008, 0); in set_qam64()
7365 if (rc != 0) { in set_qam64()
7366 pr_err("error %d\n", rc); in set_qam64()
7372 return rc; in set_qam64()
7386 int rc; in set_qam128() local
7404 …rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq… in set_qam128()
7405 if (rc != 0) { in set_qam128()
7406 pr_err("error %d\n", rc); in set_qam128()
7409 …rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)… in set_qam128()
7410 if (rc != 0) { in set_qam128()
7411 pr_err("error %d\n", rc); in set_qam128()
7415 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0); in set_qam128()
7416 if (rc != 0) { in set_qam128()
7417 pr_err("error %d\n", rc); in set_qam128()
7420 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); in set_qam128()
7421 if (rc != 0) { in set_qam128()
7422 pr_err("error %d\n", rc); in set_qam128()
7425 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); in set_qam128()
7426 if (rc != 0) { in set_qam128()
7427 pr_err("error %d\n", rc); in set_qam128()
7430 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 140, 0); in set_qam128()
7431 if (rc != 0) { in set_qam128()
7432 pr_err("error %d\n", rc); in set_qam128()
7435 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); in set_qam128()
7436 if (rc != 0) { in set_qam128()
7437 pr_err("error %d\n", rc); in set_qam128()
7440 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0); in set_qam128()
7441 if (rc != 0) { in set_qam128()
7442 pr_err("error %d\n", rc); in set_qam128()
7446 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); in set_qam128()
7447 if (rc != 0) { in set_qam128()
7448 pr_err("error %d\n", rc); in set_qam128()
7451 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0); in set_qam128()
7452 if (rc != 0) { in set_qam128()
7453 pr_err("error %d\n", rc); in set_qam128()
7456 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); in set_qam128()
7457 if (rc != 0) { in set_qam128()
7458 pr_err("error %d\n", rc); in set_qam128()
7462 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0); in set_qam128()
7463 if (rc != 0) { in set_qam128()
7464 pr_err("error %d\n", rc); in set_qam128()
7467 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65, 0); in set_qam128()
7468 if (rc != 0) { in set_qam128()
7469 pr_err("error %d\n", rc); in set_qam128()
7472 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5, 0); in set_qam128()
7473 if (rc != 0) { in set_qam128()
7474 pr_err("error %d\n", rc); in set_qam128()
7477 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3, 0); in set_qam128()
7478 if (rc != 0) { in set_qam128()
7479 pr_err("error %d\n", rc); in set_qam128()
7482 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0); in set_qam128()
7483 if (rc != 0) { in set_qam128()
7484 pr_err("error %d\n", rc); in set_qam128()
7487 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12, 0); in set_qam128()
7488 if (rc != 0) { in set_qam128()
7489 pr_err("error %d\n", rc); in set_qam128()
7492 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0); in set_qam128()
7493 if (rc != 0) { in set_qam128()
7494 pr_err("error %d\n", rc); in set_qam128()
7498 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); in set_qam128()
7499 if (rc != 0) { in set_qam128()
7500 pr_err("error %d\n", rc); in set_qam128()
7503 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); in set_qam128()
7504 if (rc != 0) { in set_qam128()
7505 pr_err("error %d\n", rc); in set_qam128()
7508 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); in set_qam128()
7509 if (rc != 0) { in set_qam128()
7510 pr_err("error %d\n", rc); in set_qam128()
7513 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40, 0); in set_qam128()
7514 if (rc != 0) { in set_qam128()
7515 pr_err("error %d\n", rc); in set_qam128()
7518 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); in set_qam128()
7519 if (rc != 0) { in set_qam128()
7520 pr_err("error %d\n", rc); in set_qam128()
7523 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); in set_qam128()
7524 if (rc != 0) { in set_qam128()
7525 pr_err("error %d\n", rc); in set_qam128()
7528 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20, 0); in set_qam128()
7529 if (rc != 0) { in set_qam128()
7530 pr_err("error %d\n", rc); in set_qam128()
7533 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); in set_qam128()
7534 if (rc != 0) { in set_qam128()
7535 pr_err("error %d\n", rc); in set_qam128()
7538 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); in set_qam128()
7539 if (rc != 0) { in set_qam128()
7540 pr_err("error %d\n", rc); in set_qam128()
7543 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); in set_qam128()
7544 if (rc != 0) { in set_qam128()
7545 pr_err("error %d\n", rc); in set_qam128()
7548 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); in set_qam128()
7549 if (rc != 0) { in set_qam128()
7550 pr_err("error %d\n", rc); in set_qam128()
7553 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); in set_qam128()
7554 if (rc != 0) { in set_qam128()
7555 pr_err("error %d\n", rc); in set_qam128()
7558 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); in set_qam128()
7559 if (rc != 0) { in set_qam128()
7560 pr_err("error %d\n", rc); in set_qam128()
7563 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); in set_qam128()
7564 if (rc != 0) { in set_qam128()
7565 pr_err("error %d\n", rc); in set_qam128()
7568 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); in set_qam128()
7569 if (rc != 0) { in set_qam128()
7570 pr_err("error %d\n", rc); in set_qam128()
7573 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); in set_qam128()
7574 if (rc != 0) { in set_qam128()
7575 pr_err("error %d\n", rc); in set_qam128()
7578 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 144, 0); in set_qam128()
7579 if (rc != 0) { in set_qam128()
7580 pr_err("error %d\n", rc); in set_qam128()
7583 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); in set_qam128()
7584 if (rc != 0) { in set_qam128()
7585 pr_err("error %d\n", rc); in set_qam128()
7588 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); in set_qam128()
7589 if (rc != 0) { in set_qam128()
7590 pr_err("error %d\n", rc); in set_qam128()
7593 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0); in set_qam128()
7594 if (rc != 0) { in set_qam128()
7595 pr_err("error %d\n", rc); in set_qam128()
7599 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992, 0); in set_qam128()
7600 if (rc != 0) { in set_qam128()
7601 pr_err("error %d\n", rc); in set_qam128()
7607 return rc; in set_qam128()
7621 int rc; in set_qam256() local
7639 …rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq… in set_qam256()
7640 if (rc != 0) { in set_qam256()
7641 pr_err("error %d\n", rc); in set_qam256()
7644 …rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)… in set_qam256()
7645 if (rc != 0) { in set_qam256()
7646 pr_err("error %d\n", rc); in set_qam256()
7650 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0); in set_qam256()
7651 if (rc != 0) { in set_qam256()
7652 pr_err("error %d\n", rc); in set_qam256()
7655 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); in set_qam256()
7656 if (rc != 0) { in set_qam256()
7657 pr_err("error %d\n", rc); in set_qam256()
7660 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); in set_qam256()
7661 if (rc != 0) { in set_qam256()
7662 pr_err("error %d\n", rc); in set_qam256()
7665 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 150, 0); in set_qam256()
7666 if (rc != 0) { in set_qam256()
7667 pr_err("error %d\n", rc); in set_qam256()
7670 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); in set_qam256()
7671 if (rc != 0) { in set_qam256()
7672 pr_err("error %d\n", rc); in set_qam256()
7675 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 110, 0); in set_qam256()
7676 if (rc != 0) { in set_qam256()
7677 pr_err("error %d\n", rc); in set_qam256()
7681 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); in set_qam256()
7682 if (rc != 0) { in set_qam256()
7683 pr_err("error %d\n", rc); in set_qam256()
7686 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16, 0); in set_qam256()
7687 if (rc != 0) { in set_qam256()
7688 pr_err("error %d\n", rc); in set_qam256()
7691 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); in set_qam256()
7692 if (rc != 0) { in set_qam256()
7693 pr_err("error %d\n", rc); in set_qam256()
7697 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0); in set_qam256()
7698 if (rc != 0) { in set_qam256()
7699 pr_err("error %d\n", rc); in set_qam256()
7702 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74, 0); in set_qam256()
7703 if (rc != 0) { in set_qam256()
7704 pr_err("error %d\n", rc); in set_qam256()
7707 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18, 0); in set_qam256()
7708 if (rc != 0) { in set_qam256()
7709 pr_err("error %d\n", rc); in set_qam256()
7712 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13, 0); in set_qam256()
7713 if (rc != 0) { in set_qam256()
7714 pr_err("error %d\n", rc); in set_qam256()
7717 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7, 0); in set_qam256()
7718 if (rc != 0) { in set_qam256()
7719 pr_err("error %d\n", rc); in set_qam256()
7722 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0, 0); in set_qam256()
7723 if (rc != 0) { in set_qam256()
7724 pr_err("error %d\n", rc); in set_qam256()
7727 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0); in set_qam256()
7728 if (rc != 0) { in set_qam256()
7729 pr_err("error %d\n", rc); in set_qam256()
7733 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); in set_qam256()
7734 if (rc != 0) { in set_qam256()
7735 pr_err("error %d\n", rc); in set_qam256()
7738 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); in set_qam256()
7739 if (rc != 0) { in set_qam256()
7740 pr_err("error %d\n", rc); in set_qam256()
7743 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); in set_qam256()
7744 if (rc != 0) { in set_qam256()
7745 pr_err("error %d\n", rc); in set_qam256()
7748 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50, 0); in set_qam256()
7749 if (rc != 0) { in set_qam256()
7750 pr_err("error %d\n", rc); in set_qam256()
7753 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); in set_qam256()
7754 if (rc != 0) { in set_qam256()
7755 pr_err("error %d\n", rc); in set_qam256()
7758 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); in set_qam256()
7759 if (rc != 0) { in set_qam256()
7760 pr_err("error %d\n", rc); in set_qam256()
7763 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25, 0); in set_qam256()
7764 if (rc != 0) { in set_qam256()
7765 pr_err("error %d\n", rc); in set_qam256()
7768 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); in set_qam256()
7769 if (rc != 0) { in set_qam256()
7770 pr_err("error %d\n", rc); in set_qam256()
7773 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); in set_qam256()
7774 if (rc != 0) { in set_qam256()
7775 pr_err("error %d\n", rc); in set_qam256()
7778 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); in set_qam256()
7779 if (rc != 0) { in set_qam256()
7780 pr_err("error %d\n", rc); in set_qam256()
7783 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); in set_qam256()
7784 if (rc != 0) { in set_qam256()
7785 pr_err("error %d\n", rc); in set_qam256()
7788 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); in set_qam256()
7789 if (rc != 0) { in set_qam256()
7790 pr_err("error %d\n", rc); in set_qam256()
7793 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); in set_qam256()
7794 if (rc != 0) { in set_qam256()
7795 pr_err("error %d\n", rc); in set_qam256()
7798 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); in set_qam256()
7799 if (rc != 0) { in set_qam256()
7800 pr_err("error %d\n", rc); in set_qam256()
7803 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); in set_qam256()
7804 if (rc != 0) { in set_qam256()
7805 pr_err("error %d\n", rc); in set_qam256()
7808 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0); in set_qam256()
7809 if (rc != 0) { in set_qam256()
7810 pr_err("error %d\n", rc); in set_qam256()
7813 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 80, 0); in set_qam256()
7814 if (rc != 0) { in set_qam256()
7815 pr_err("error %d\n", rc); in set_qam256()
7818 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); in set_qam256()
7819 if (rc != 0) { in set_qam256()
7820 pr_err("error %d\n", rc); in set_qam256()
7823 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); in set_qam256()
7824 if (rc != 0) { in set_qam256()
7825 pr_err("error %d\n", rc); in set_qam256()
7828 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0); in set_qam256()
7829 if (rc != 0) { in set_qam256()
7830 pr_err("error %d\n", rc); in set_qam256()
7834 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520, 0); in set_qam256()
7835 if (rc != 0) { in set_qam256()
7836 pr_err("error %d\n", rc); in set_qam256()
7842 return rc; in set_qam256()
7864 int rc; in set_qam() local
8068 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); in set_qam()
8069 if (rc != 0) { in set_qam()
8070 pr_err("error %d\n", rc); in set_qam()
8073 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0); in set_qam()
8074 if (rc != 0) { in set_qam()
8075 pr_err("error %d\n", rc); in set_qam()
8078 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); in set_qam()
8079 if (rc != 0) { in set_qam()
8080 pr_err("error %d\n", rc); in set_qam()
8083 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); in set_qam()
8084 if (rc != 0) { in set_qam()
8085 pr_err("error %d\n", rc); in set_qam()
8088 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); in set_qam()
8089 if (rc != 0) { in set_qam()
8090 pr_err("error %d\n", rc); in set_qam()
8093 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); in set_qam()
8094 if (rc != 0) { in set_qam()
8095 pr_err("error %d\n", rc); in set_qam()
8098 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); in set_qam()
8099 if (rc != 0) { in set_qam()
8100 pr_err("error %d\n", rc); in set_qam()
8110 rc = scu_command(dev_addr, &cmd_scu); in set_qam()
8111 if (rc != 0) { in set_qam()
8112 pr_err("error %d\n", rc); in set_qam()
8129 rc = scu_command(dev_addr, &cmd_scu); in set_qam()
8130 if (rc != 0) { in set_qam()
8131 pr_err("error %d\n", rc); in set_qam()
8141 rc = scu_command(dev_addr, &cmd_scu); in set_qam()
8142 if (rc != 0) { in set_qam()
8143 pr_err("error %d\n", rc); in set_qam()
8147 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate, 0); in set_qam()
8148 if (rc != 0) { in set_qam()
8149 pr_err("error %d\n", rc); in set_qam()
8153 rc = set_qam_measurement(demod, channel->constellation, channel->symbolrate); in set_qam()
8154 if (rc != 0) { in set_qam()
8155 pr_err("error %d\n", rc); in set_qam()
8164 rc = set_frequency(demod, channel, tuner_freq_offset); in set_qam()
8165 if (rc != 0) { in set_qam()
8166 pr_err("error %d\n", rc); in set_qam()
8173 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_SYMBOL_FREQ__A, lc_symbol_freq, 0); in set_qam()
8174 if (rc != 0) { in set_qam()
8175 pr_err("error %d\n", rc); in set_qam()
8178 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, iqm_rc_stretch, 0); in set_qam()
8179 if (rc != 0) { in set_qam()
8180 pr_err("error %d\n", rc); in set_qam()
8187 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0); in set_qam()
8188 if (rc != 0) { in set_qam()
8189 pr_err("error %d\n", rc); in set_qam()
8193 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0); in set_qam()
8194 if (rc != 0) { in set_qam()
8195 pr_err("error %d\n", rc); in set_qam()
8198 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0); in set_qam()
8199 if (rc != 0) { in set_qam()
8200 pr_err("error %d\n", rc); in set_qam()
8203 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M, 0); in set_qam()
8204 if (rc != 0) { in set_qam()
8205 pr_err("error %d\n", rc); in set_qam()
8209 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f, 0); in set_qam()
8210 if (rc != 0) { in set_qam()
8211 pr_err("error %d\n", rc); in set_qam()
8215 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SYNC_SEL__A, 3, 0); in set_qam()
8216 if (rc != 0) { in set_qam()
8217 pr_err("error %d\n", rc); in set_qam()
8220 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0); in set_qam()
8221 if (rc != 0) { in set_qam()
8222 pr_err("error %d\n", rc); in set_qam()
8225 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 448, 0); in set_qam()
8226 if (rc != 0) { in set_qam()
8227 pr_err("error %d\n", rc); in set_qam()
8230 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0); in set_qam()
8231 if (rc != 0) { in set_qam()
8232 pr_err("error %d\n", rc); in set_qam()
8235 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, 4, 0); in set_qam()
8236 if (rc != 0) { in set_qam()
8237 pr_err("error %d\n", rc); in set_qam()
8240 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, 0x10, 0); in set_qam()
8241 if (rc != 0) { in set_qam()
8242 pr_err("error %d\n", rc); in set_qam()
8245 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, 11, 0); in set_qam()
8246 if (rc != 0) { in set_qam()
8247 pr_err("error %d\n", rc); in set_qam()
8251 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0); in set_qam()
8252 if (rc != 0) { in set_qam()
8253 pr_err("error %d\n", rc); in set_qam()
8256 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE, 0); in set_qam()
8257 if (rc != 0) { in set_qam()
8258 pr_err("error %d\n", rc); in set_qam()
8262 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE, 0); in set_qam()
8263 if (rc != 0) { in set_qam()
8264 pr_err("error %d\n", rc); in set_qam()
8268 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE, 0); in set_qam()
8269 if (rc != 0) { in set_qam()
8270 pr_err("error %d\n", rc); in set_qam()
8273 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE, 0); in set_qam()
8274 if (rc != 0) { in set_qam()
8275 pr_err("error %d\n", rc); in set_qam()
8278 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0); in set_qam()
8279 if (rc != 0) { in set_qam()
8280 pr_err("error %d\n", rc); in set_qam()
8288 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0); in set_qam()
8289 if (rc != 0) { in set_qam()
8290 pr_err("error %d\n", rc); in set_qam()
8293 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x04, 0); in set_qam()
8294 if (rc != 0) { in set_qam()
8295 pr_err("error %d\n", rc); in set_qam()
8298 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0); in set_qam()
8299 if (rc != 0) { in set_qam()
8300 pr_err("error %d\n", rc); in set_qam()
8306 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0); in set_qam()
8307 if (rc != 0) { in set_qam()
8308 pr_err("error %d\n", rc); in set_qam()
8311 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x05, 0); in set_qam()
8312 if (rc != 0) { in set_qam()
8313 pr_err("error %d\n", rc); in set_qam()
8316 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, 0x06, 0); in set_qam()
8317 if (rc != 0) { in set_qam()
8318 pr_err("error %d\n", rc); in set_qam()
8327 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, QAM_LC_MODE__PRE, 0); in set_qam()
8328 if (rc != 0) { in set_qam()
8329 pr_err("error %d\n", rc); in set_qam()
8332 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_RATE_LIMIT__A, 3, 0); in set_qam()
8333 if (rc != 0) { in set_qam()
8334 pr_err("error %d\n", rc); in set_qam()
8337 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORP__A, 4, 0); in set_qam()
8338 if (rc != 0) { in set_qam()
8339 pr_err("error %d\n", rc); in set_qam()
8342 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORI__A, 4, 0); in set_qam()
8343 if (rc != 0) { in set_qam()
8344 pr_err("error %d\n", rc); in set_qam()
8347 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, 7, 0); in set_qam()
8348 if (rc != 0) { in set_qam()
8349 pr_err("error %d\n", rc); in set_qam()
8352 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB0__A, 1, 0); in set_qam()
8353 if (rc != 0) { in set_qam()
8354 pr_err("error %d\n", rc); in set_qam()
8357 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB1__A, 1, 0); in set_qam()
8358 if (rc != 0) { in set_qam()
8359 pr_err("error %d\n", rc); in set_qam()
8362 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB2__A, 1, 0); in set_qam()
8363 if (rc != 0) { in set_qam()
8364 pr_err("error %d\n", rc); in set_qam()
8367 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB3__A, 1, 0); in set_qam()
8368 if (rc != 0) { in set_qam()
8369 pr_err("error %d\n", rc); in set_qam()
8372 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB4__A, 2, 0); in set_qam()
8373 if (rc != 0) { in set_qam()
8374 pr_err("error %d\n", rc); in set_qam()
8377 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB5__A, 2, 0); in set_qam()
8378 if (rc != 0) { in set_qam()
8379 pr_err("error %d\n", rc); in set_qam()
8382 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB6__A, 2, 0); in set_qam()
8383 if (rc != 0) { in set_qam()
8384 pr_err("error %d\n", rc); in set_qam()
8387 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB8__A, 2, 0); in set_qam()
8388 if (rc != 0) { in set_qam()
8389 pr_err("error %d\n", rc); in set_qam()
8392 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB9__A, 2, 0); in set_qam()
8393 if (rc != 0) { in set_qam()
8394 pr_err("error %d\n", rc); in set_qam()
8397 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB10__A, 2, 0); in set_qam()
8398 if (rc != 0) { in set_qam()
8399 pr_err("error %d\n", rc); in set_qam()
8402 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB12__A, 2, 0); in set_qam()
8403 if (rc != 0) { in set_qam()
8404 pr_err("error %d\n", rc); in set_qam()
8407 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB15__A, 3, 0); in set_qam()
8408 if (rc != 0) { in set_qam()
8409 pr_err("error %d\n", rc); in set_qam()
8412 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB16__A, 3, 0); in set_qam()
8413 if (rc != 0) { in set_qam()
8414 pr_err("error %d\n", rc); in set_qam()
8417 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB20__A, 4, 0); in set_qam()
8418 if (rc != 0) { in set_qam()
8419 pr_err("error %d\n", rc); in set_qam()
8422 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB25__A, 4, 0); in set_qam()
8423 if (rc != 0) { in set_qam()
8424 pr_err("error %d\n", rc); in set_qam()
8428 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, 1, 0); in set_qam()
8429 if (rc != 0) { in set_qam()
8430 pr_err("error %d\n", rc); in set_qam()
8433 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, 1, 0); in set_qam()
8434 if (rc != 0) { in set_qam()
8435 pr_err("error %d\n", rc); in set_qam()
8438 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_ADJ_SEL__A, 1, 0); in set_qam()
8439 if (rc != 0) { in set_qam()
8440 pr_err("error %d\n", rc); in set_qam()
8443 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 0, 0); in set_qam()
8444 if (rc != 0) { in set_qam()
8445 pr_err("error %d\n", rc); in set_qam()
8448 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0); in set_qam()
8449 if (rc != 0) { in set_qam()
8450 pr_err("error %d\n", rc); in set_qam()
8457 rc = set_iqm_af(demod, true); in set_qam()
8458 if (rc != 0) { in set_qam()
8459 pr_err("error %d\n", rc); in set_qam()
8462 rc = adc_synchronization(demod); in set_qam()
8463 if (rc != 0) { in set_qam()
8464 pr_err("error %d\n", rc); in set_qam()
8468 rc = init_agc(demod); in set_qam()
8469 if (rc != 0) { in set_qam()
8470 pr_err("error %d\n", rc); in set_qam()
8473 rc = set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false); in set_qam()
8474 if (rc != 0) { in set_qam()
8475 pr_err("error %d\n", rc); in set_qam()
8478 rc = set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false); in set_qam()
8479 if (rc != 0) { in set_qam()
8480 pr_err("error %d\n", rc); in set_qam()
8489 rc = ctrl_set_cfg_afe_gain(demod, &qam_pga_cfg); in set_qam()
8490 if (rc != 0) { in set_qam()
8491 pr_err("error %d\n", rc); in set_qam()
8495 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg)); in set_qam()
8496 if (rc != 0) { in set_qam()
8497 pr_err("error %d\n", rc); in set_qam()
8504 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), … in set_qam()
8505 if (rc != 0) { in set_qam()
8506 pr_err("error %d\n", rc); in set_qam()
8509 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), … in set_qam()
8510 if (rc != 0) { in set_qam()
8511 pr_err("error %d\n", rc); in set_qam()
8517 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_tap… in set_qam()
8518 if (rc != 0) { in set_qam()
8519 pr_err("error %d\n", rc); in set_qam()
8522 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_tap… in set_qam()
8523 if (rc != 0) { in set_qam()
8524 pr_err("error %d\n", rc); in set_qam()
8529 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_t… in set_qam()
8530 if (rc != 0) { in set_qam()
8531 pr_err("error %d\n", rc); in set_qam()
8534 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_t… in set_qam()
8535 if (rc != 0) { in set_qam()
8536 pr_err("error %d\n", rc); in set_qam()
8544 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), … in set_qam()
8545 if (rc != 0) { in set_qam()
8546 pr_err("error %d\n", rc); in set_qam()
8549 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), … in set_qam()
8550 if (rc != 0) { in set_qam()
8551 pr_err("error %d\n", rc); in set_qam()
8559 rc = set_qam16(demod); in set_qam()
8560 if (rc != 0) { in set_qam()
8561 pr_err("error %d\n", rc); in set_qam()
8566 rc = set_qam32(demod); in set_qam()
8567 if (rc != 0) { in set_qam()
8568 pr_err("error %d\n", rc); in set_qam()
8573 rc = set_qam64(demod); in set_qam()
8574 if (rc != 0) { in set_qam()
8575 pr_err("error %d\n", rc); in set_qam()
8580 rc = set_qam128(demod); in set_qam()
8581 if (rc != 0) { in set_qam()
8582 pr_err("error %d\n", rc); in set_qam()
8587 rc = set_qam256(demod); in set_qam()
8588 if (rc != 0) { in set_qam()
8589 pr_err("error %d\n", rc); in set_qam()
8599 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0); in set_qam()
8600 if (rc != 0) { in set_qam()
8601 pr_err("error %d\n", rc); in set_qam()
8606 rc = set_mpegtei_handling(demod); in set_qam()
8607 if (rc != 0) { in set_qam()
8608 pr_err("error %d\n", rc); in set_qam()
8611 rc = bit_reverse_mpeg_output(demod); in set_qam()
8612 if (rc != 0) { in set_qam()
8613 pr_err("error %d\n", rc); in set_qam()
8616 rc = set_mpeg_start_width(demod); in set_qam()
8617 if (rc != 0) { in set_qam()
8618 pr_err("error %d\n", rc); in set_qam()
8629 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); in set_qam()
8630 if (rc != 0) { in set_qam()
8631 pr_err("error %d\n", rc); in set_qam()
8646 rc = scu_command(dev_addr, &cmd_scu); in set_qam()
8647 if (rc != 0) { in set_qam()
8648 pr_err("error %d\n", rc); in set_qam()
8653 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0); in set_qam()
8654 if (rc != 0) { in set_qam()
8655 pr_err("error %d\n", rc); in set_qam()
8658 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE, 0); in set_qam()
8659 if (rc != 0) { in set_qam()
8660 pr_err("error %d\n", rc); in set_qam()
8663 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0); in set_qam()
8664 if (rc != 0) { in set_qam()
8665 pr_err("error %d\n", rc); in set_qam()
8671 return rc; in set_qam()
8681 int rc; in qam_flip_spec() local
8692 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0); in qam_flip_spec()
8693 if (rc != 0) { in qam_flip_spec()
8694 pr_err("error %d\n", rc); in qam_flip_spec()
8697 …rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~(SCU_RAM_QAM_CTL_ENA_AC… in qam_flip_spec()
8698 if (rc != 0) { in qam_flip_spec()
8699 pr_err("error %d\n", rc); in qam_flip_spec()
8704 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF__A, 0, 0); in qam_flip_spec()
8705 if (rc != 0) { in qam_flip_spec()
8706 pr_err("error %d\n", rc); in qam_flip_spec()
8709 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF1__A, 0, 0); in qam_flip_spec()
8710 if (rc != 0) { in qam_flip_spec()
8711 pr_err("error %d\n", rc); in qam_flip_spec()
8715 rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, &iqm_fs_rate_ofs, 0); in qam_flip_spec()
8716 if (rc != 0) { in qam_flip_spec()
8717 pr_err("error %d\n", rc); in qam_flip_spec()
8720 rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_LO__A, &iqm_fs_rate_lo, 0); in qam_flip_spec()
8721 if (rc != 0) { in qam_flip_spec()
8722 pr_err("error %d\n", rc); in qam_flip_spec()
8730 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0); in qam_flip_spec()
8731 if (rc != 0) { in qam_flip_spec()
8732 pr_err("error %d\n", rc); in qam_flip_spec()
8736 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0); in qam_flip_spec()
8737 if (rc != 0) { in qam_flip_spec()
8738 pr_err("error %d\n", rc); in qam_flip_spec()
8741 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0); in qam_flip_spec()
8742 if (rc != 0) { in qam_flip_spec()
8743 pr_err("error %d\n", rc); in qam_flip_spec()
8748 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CI__A, 0, 0); in qam_flip_spec()
8749 if (rc != 0) { in qam_flip_spec()
8750 pr_err("error %d\n", rc); in qam_flip_spec()
8753 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_EP__A, 0, 0); in qam_flip_spec()
8754 if (rc != 0) { in qam_flip_spec()
8755 pr_err("error %d\n", rc); in qam_flip_spec()
8758 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_LA_FACTOR__A, 0, 0); in qam_flip_spec()
8759 if (rc != 0) { in qam_flip_spec()
8760 pr_err("error %d\n", rc); in qam_flip_spec()
8765 rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0); in qam_flip_spec()
8766 if (rc != 0) { in qam_flip_spec()
8767 pr_err("error %d\n", rc); in qam_flip_spec()
8774 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0); in qam_flip_spec()
8775 if (rc != 0) { in qam_flip_spec()
8776 pr_err("error %d\n", rc); in qam_flip_spec()
8781 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0); in qam_flip_spec()
8782 if (rc != 0) { in qam_flip_spec()
8783 pr_err("error %d\n", rc); in qam_flip_spec()
8786 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0); in qam_flip_spec()
8787 if (rc != 0) { in qam_flip_spec()
8788 pr_err("error %d\n", rc); in qam_flip_spec()
8793 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data, 0); in qam_flip_spec()
8794 if (rc != 0) { in qam_flip_spec()
8795 pr_err("error %d\n", rc); in qam_flip_spec()
8798 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0); in qam_flip_spec()
8799 if (rc != 0) { in qam_flip_spec()
8800 pr_err("error %d\n", rc); in qam_flip_spec()
8806 rc = drxj_dap_read_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data, 0); in qam_flip_spec()
8807 if (rc != 0) { in qam_flip_spec()
8808 pr_err("error %d\n", rc); in qam_flip_spec()
8811 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0); in qam_flip_spec()
8812 if (rc != 0) { in qam_flip_spec()
8813 pr_err("error %d\n", rc); in qam_flip_spec()
8819 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0); in qam_flip_spec()
8820 if (rc != 0) { in qam_flip_spec()
8821 pr_err("error %d\n", rc); in qam_flip_spec()
8824 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0); in qam_flip_spec()
8825 if (rc != 0) { in qam_flip_spec()
8826 pr_err("error %d\n", rc); in qam_flip_spec()
8830 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4, 0); in qam_flip_spec()
8831 if (rc != 0) { in qam_flip_spec()
8832 pr_err("error %d\n", rc); in qam_flip_spec()
8838 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE__A, &fsm_state, 0); in qam_flip_spec()
8839 if (rc != 0) { in qam_flip_spec()
8840 pr_err("error %d\n", rc); in qam_flip_spec()
8844 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, (qam_ctl_ena | 0x0016), 0); in qam_flip_spec()
8845 if (rc != 0) { in qam_flip_spec()
8846 pr_err("error %d\n", rc); in qam_flip_spec()
8852 return rc; in qam_flip_spec()
8878 int rc; in qam64auto() local
8890 rc = ctrl_lock_status(demod, lock_status); in qam64auto()
8891 if (rc != 0) { in qam64auto()
8892 pr_err("error %d\n", rc); in qam64auto()
8899 rc = ctrl_get_qam_sig_quality(demod); in qam64auto()
8900 if (rc != 0) { in qam64auto()
8901 pr_err("error %d\n", rc); in qam64auto()
8916 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); in qam64auto()
8917 if (rc != 0) { in qam64auto()
8918 pr_err("error %d\n", rc); in qam64auto()
8921 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); in qam64auto()
8922 if (rc != 0) { in qam64auto()
8923 pr_err("error %d\n", rc); in qam64auto()
8934 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); in qam64auto()
8935 if (rc != 0) { in qam64auto()
8936 pr_err("error %d\n", rc); in qam64auto()
8939 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0); in qam64auto()
8940 if (rc != 0) { in qam64auto()
8941 pr_err("error %d\n", rc); in qam64auto()
8946 rc = qam_flip_spec(demod, channel); in qam64auto()
8947 if (rc != 0) { in qam64auto()
8948 pr_err("error %d\n", rc); in qam64auto()
8968 rc = ctrl_get_qam_sig_quality(demod); in qam64auto()
8969 if (rc != 0) { in qam64auto()
8970 pr_err("error %d\n", rc); in qam64auto()
8974 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); in qam64auto()
8975 if (rc != 0) { in qam64auto()
8976 pr_err("error %d\n", rc); in qam64auto()
8979 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); in qam64auto()
8980 if (rc != 0) { in qam64auto()
8981 pr_err("error %d\n", rc); in qam64auto()
9005 return rc; in qam64auto()
9026 int rc; in qam256auto() local
9037 rc = ctrl_lock_status(demod, lock_status); in qam256auto()
9038 if (rc != 0) { in qam256auto()
9039 pr_err("error %d\n", rc); in qam256auto()
9045 rc = ctrl_get_qam_sig_quality(demod); in qam256auto()
9046 if (rc != 0) { in qam256auto()
9047 pr_err("error %d\n", rc); in qam256auto()
9063 rc = qam_flip_spec(demod, channel); in qam256auto()
9064 if (rc != 0) { in qam256auto()
9065 pr_err("error %d\n", rc); in qam256auto()
9089 return rc; in qam256auto()
9104 int rc; in set_qam_channel() local
9128 rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL); in set_qam_channel()
9129 if (rc != 0) { in set_qam_channel()
9130 pr_err("error %d\n", rc); in set_qam_channel()
9135 rc = qam64auto(demod, channel, tuner_freq_offset, in set_qam_channel()
9138 rc = qam256auto(demod, channel, tuner_freq_offset, in set_qam_channel()
9140 if (rc != 0) { in set_qam_channel()
9141 pr_err("error %d\n", rc); in set_qam_channel()
9158 rc = set_qam(demod, channel, tuner_freq_offset, in set_qam_channel()
9160 if (rc != 0) { in set_qam_channel()
9161 pr_err("error %d\n", rc); in set_qam_channel()
9164 rc = qam256auto(demod, channel, tuner_freq_offset, in set_qam_channel()
9166 if (rc != 0) { in set_qam_channel()
9167 pr_err("error %d\n", rc); in set_qam_channel()
9184 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9187 if (rc != 0) { in set_qam_channel()
9188 pr_err("error %d\n", rc); in set_qam_channel()
9191 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9194 if (rc != 0) { in set_qam_channel()
9195 pr_err("error %d\n", rc); in set_qam_channel()
9198 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9201 if (rc != 0) { in set_qam_channel()
9202 pr_err("error %d\n", rc); in set_qam_channel()
9206 rc = set_qam(demod, channel, tuner_freq_offset, in set_qam_channel()
9208 if (rc != 0) { in set_qam_channel()
9209 pr_err("error %d\n", rc); in set_qam_channel()
9212 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9215 if (rc != 0) { in set_qam_channel()
9216 pr_err("error %d\n", rc); in set_qam_channel()
9220 rc = qam64auto(demod, channel, tuner_freq_offset, in set_qam_channel()
9222 if (rc != 0) { in set_qam_channel()
9223 pr_err("error %d\n", rc); in set_qam_channel()
9239 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9242 if (rc != 0) { in set_qam_channel()
9243 pr_err("error %d\n", rc); in set_qam_channel()
9246 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9249 if (rc != 0) { in set_qam_channel()
9250 pr_err("error %d\n", rc); in set_qam_channel()
9253 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9256 if (rc != 0) { in set_qam_channel()
9257 pr_err("error %d\n", rc); in set_qam_channel()
9261 rc = set_qam(demod, channel, tuner_freq_offset, in set_qam_channel()
9263 if (rc != 0) { in set_qam_channel()
9264 pr_err("error %d\n", rc); in set_qam_channel()
9267 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9270 if (rc != 0) { in set_qam_channel()
9271 pr_err("error %d\n", rc); in set_qam_channel()
9274 rc = qam64auto(demod, channel, tuner_freq_offset, in set_qam_channel()
9276 if (rc != 0) { in set_qam_channel()
9277 pr_err("error %d\n", rc); in set_qam_channel()
9294 return rc; in set_qam_channel()
9311 int rc; in get_qamrs_err_count() local
9323 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors, 0); in get_qamrs_err_count()
9324 if (rc != 0) { in get_qamrs_err_count()
9325 pr_err("error %d\n", rc); in get_qamrs_err_count()
9329 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &nr_symbol_errors, 0); in get_qamrs_err_count()
9330 if (rc != 0) { in get_qamrs_err_count()
9331 pr_err("error %d\n", rc); in get_qamrs_err_count()
9335 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_PACKET_ERRORS__A, &nr_packet_errors, 0); in get_qamrs_err_count()
9336 if (rc != 0) { in get_qamrs_err_count()
9337 pr_err("error %d\n", rc); in get_qamrs_err_count()
9341 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &nr_failures, 0); in get_qamrs_err_count()
9342 if (rc != 0) { in get_qamrs_err_count()
9343 pr_err("error %d\n", rc); in get_qamrs_err_count()
9347 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_COUNT__A, &nr_snc_par_fail_count, 0); in get_qamrs_err_count()
9348 if (rc != 0) { in get_qamrs_err_count()
9349 pr_err("error %d\n", rc); in get_qamrs_err_count()
9365 return rc; in get_qamrs_err_count()
9388 int rc; in get_sig_strength() local
9396 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &if_gain, 0); in get_sig_strength()
9397 if (rc != 0) { in get_sig_strength()
9398 pr_err("error %d\n", rc); in get_sig_strength()
9402 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &rf_gain, 0); in get_sig_strength()
9403 if (rc != 0) { in get_sig_strength()
9404 pr_err("error %d\n", rc); in get_sig_strength()
9447 return rc; in get_sig_strength()
9471 int rc; in ctrl_get_qam_sig_quality() local
9501 rc = get_qamrs_err_count(dev_addr, &measuredrs_errors); in ctrl_get_qam_sig_quality()
9502 if (rc != 0) { in ctrl_get_qam_sig_quality()
9503 pr_err("error %d\n", rc); in ctrl_get_qam_sig_quality()
9507 rc = drxj_dap_read_reg16(dev_addr, QAM_SL_ERR_POWER__A, &qam_sl_err_power, 0); in ctrl_get_qam_sig_quality()
9508 if (rc != 0) { in ctrl_get_qam_sig_quality()
9509 pr_err("error %d\n", rc); in ctrl_get_qam_sig_quality()
9513 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, &fec_oc_period, 0); in ctrl_get_qam_sig_quality()
9514 if (rc != 0) { in ctrl_get_qam_sig_quality()
9515 pr_err("error %d\n", rc); in ctrl_get_qam_sig_quality()
9566 rc = drxj_dap_read_reg16(dev_addr, QAM_VD_NR_QSYM_ERRORS__A, &qsym_err_vd, 0); in ctrl_get_qam_sig_quality()
9567 if (rc != 0) { in ctrl_get_qam_sig_quality()
9568 pr_err("error %d\n", rc); in ctrl_get_qam_sig_quality()
9649 rc = get_acc_pkt_err(demod, &sig_quality->packet_error); in ctrl_get_qam_sig_quality()
9650 if (rc != 0) { in ctrl_get_qam_sig_quality()
9651 pr_err("error %d\n", rc); in ctrl_get_qam_sig_quality()
9665 return rc; in ctrl_get_qam_sig_quality()
9757 int rc; in power_down_atv() local
9769 rc = scu_command(dev_addr, &cmd_scu); in power_down_atv()
9770 if (rc != 0) { in power_down_atv()
9771 pr_err("error %d\n", rc); in power_down_atv()
9775 …rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP… in power_down_atv()
9776 if (rc != 0) { in power_down_atv()
9777 pr_err("error %d\n", rc); in power_down_atv()
9781 rc = drxj_dap_write_reg16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0); in power_down_atv()
9782 if (rc != 0) { in power_down_atv()
9783 pr_err("error %d\n", rc); in power_down_atv()
9787 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); in power_down_atv()
9788 if (rc != 0) { in power_down_atv()
9789 pr_err("error %d\n", rc); in power_down_atv()
9792 rc = set_iqm_af(demod, false); in power_down_atv()
9793 if (rc != 0) { in power_down_atv()
9794 pr_err("error %d\n", rc); in power_down_atv()
9798 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); in power_down_atv()
9799 if (rc != 0) { in power_down_atv()
9800 pr_err("error %d\n", rc); in power_down_atv()
9803 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); in power_down_atv()
9804 if (rc != 0) { in power_down_atv()
9805 pr_err("error %d\n", rc); in power_down_atv()
9808 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); in power_down_atv()
9809 if (rc != 0) { in power_down_atv()
9810 pr_err("error %d\n", rc); in power_down_atv()
9813 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); in power_down_atv()
9814 if (rc != 0) { in power_down_atv()
9815 pr_err("error %d\n", rc); in power_down_atv()
9818 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); in power_down_atv()
9819 if (rc != 0) { in power_down_atv()
9820 pr_err("error %d\n", rc); in power_down_atv()
9824 rc = power_down_aud(demod); in power_down_atv()
9825 if (rc != 0) { in power_down_atv()
9826 pr_err("error %d\n", rc); in power_down_atv()
9832 return rc; in power_down_atv()
9847 int rc; in power_down_aud() local
9852 rc = drxj_dap_write_reg16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP, 0); in power_down_aud()
9853 if (rc != 0) { in power_down_aud()
9854 pr_err("error %d\n", rc); in power_down_aud()
9862 return rc; in power_down_aud()
9875 int rc; in set_orx_nsu_aox() local
9879 rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0); in set_orx_nsu_aox()
9880 if (rc != 0) { in set_orx_nsu_aox()
9881 pr_err("error %d\n", rc); in set_orx_nsu_aox()
9888 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0); in set_orx_nsu_aox()
9889 if (rc != 0) { in set_orx_nsu_aox()
9890 pr_err("error %d\n", rc); in set_orx_nsu_aox()
9896 return rc; in set_orx_nsu_aox()
9925 int rc; in ctrl_set_oob() local
9962 rc = scu_command(dev_addr, &scu_cmd); in ctrl_set_oob()
9963 if (rc != 0) { in ctrl_set_oob()
9964 pr_err("error %d\n", rc); in ctrl_set_oob()
9967 rc = set_orx_nsu_aox(demod, false); in ctrl_set_oob()
9968 if (rc != 0) { in ctrl_set_oob()
9969 pr_err("error %d\n", rc); in ctrl_set_oob()
9972 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); in ctrl_set_oob()
9973 if (rc != 0) { in ctrl_set_oob()
9974 pr_err("error %d\n", rc); in ctrl_set_oob()
10004 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); in ctrl_set_oob()
10005 if (rc != 0) { in ctrl_set_oob()
10006 pr_err("error %d\n", rc); in ctrl_set_oob()
10014 rc = scu_command(dev_addr, &scu_cmd); in ctrl_set_oob()
10015 if (rc != 0) { in ctrl_set_oob()
10016 pr_err("error %d\n", rc); in ctrl_set_oob()
10027 rc = scu_command(dev_addr, &scu_cmd); in ctrl_set_oob()
10028 if (rc != 0) { in ctrl_set_oob()
10029 pr_err("error %d\n", rc); in ctrl_set_oob()
10103 rc = scu_command(dev_addr, &scu_cmd); in ctrl_set_oob()
10104 if (rc != 0) { in ctrl_set_oob()
10105 pr_err("error %d\n", rc); in ctrl_set_oob()
10109 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); in ctrl_set_oob()
10110 if (rc != 0) { in ctrl_set_oob()
10111 pr_err("error %d\n", rc); in ctrl_set_oob()
10114 …rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_… in ctrl_set_oob()
10115 if (rc != 0) { in ctrl_set_oob()
10116 pr_err("error %d\n", rc); in ctrl_set_oob()
10119 …rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_… in ctrl_set_oob()
10120 if (rc != 0) { in ctrl_set_oob()
10121 pr_err("error %d\n", rc); in ctrl_set_oob()
10124 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in ctrl_set_oob()
10125 if (rc != 0) { in ctrl_set_oob()
10126 pr_err("error %d\n", rc); in ctrl_set_oob()
10130 rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0); in ctrl_set_oob()
10131 if (rc != 0) { in ctrl_set_oob()
10132 pr_err("error %d\n", rc); in ctrl_set_oob()
10135 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0); in ctrl_set_oob()
10136 if (rc != 0) { in ctrl_set_oob()
10137 pr_err("error %d\n", rc); in ctrl_set_oob()
10140 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0); in ctrl_set_oob()
10141 if (rc != 0) { in ctrl_set_oob()
10142 pr_err("error %d\n", rc); in ctrl_set_oob()
10147 rc = drxj_dap_write_reg16(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0); in ctrl_set_oob()
10148 if (rc != 0) { in ctrl_set_oob()
10149 pr_err("error %d\n", rc); in ctrl_set_oob()
10154 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0); in ctrl_set_oob()
10155 if (rc != 0) { in ctrl_set_oob()
10156 pr_err("error %d\n", rc); in ctrl_set_oob()
10161 …rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_S… in ctrl_set_oob()
10162 if (rc != 0) { in ctrl_set_oob()
10163 pr_err("error %d\n", rc); in ctrl_set_oob()
10166 …rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048… in ctrl_set_oob()
10167 if (rc != 0) { in ctrl_set_oob()
10168 pr_err("error %d\n", rc); in ctrl_set_oob()
10173 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0); in ctrl_set_oob()
10174 if (rc != 0) { in ctrl_set_oob()
10175 pr_err("error %d\n", rc); in ctrl_set_oob()
10178 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0); in ctrl_set_oob()
10179 if (rc != 0) { in ctrl_set_oob()
10180 pr_err("error %d\n", rc); in ctrl_set_oob()
10183 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0); in ctrl_set_oob()
10184 if (rc != 0) { in ctrl_set_oob()
10185 pr_err("error %d\n", rc); in ctrl_set_oob()
10188 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0); in ctrl_set_oob()
10189 if (rc != 0) { in ctrl_set_oob()
10190 pr_err("error %d\n", rc); in ctrl_set_oob()
10195 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0); in ctrl_set_oob()
10196 if (rc != 0) { in ctrl_set_oob()
10197 pr_err("error %d\n", rc); in ctrl_set_oob()
10200 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10201 if (rc != 0) { in ctrl_set_oob()
10202 pr_err("error %d\n", rc); in ctrl_set_oob()
10205 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0); in ctrl_set_oob()
10206 if (rc != 0) { in ctrl_set_oob()
10207 pr_err("error %d\n", rc); in ctrl_set_oob()
10210 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10211 if (rc != 0) { in ctrl_set_oob()
10212 pr_err("error %d\n", rc); in ctrl_set_oob()
10215 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0); in ctrl_set_oob()
10216 if (rc != 0) { in ctrl_set_oob()
10217 pr_err("error %d\n", rc); in ctrl_set_oob()
10222 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0); in ctrl_set_oob()
10223 if (rc != 0) { in ctrl_set_oob()
10224 pr_err("error %d\n", rc); in ctrl_set_oob()
10227 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10228 if (rc != 0) { in ctrl_set_oob()
10229 pr_err("error %d\n", rc); in ctrl_set_oob()
10232 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0); in ctrl_set_oob()
10233 if (rc != 0) { in ctrl_set_oob()
10234 pr_err("error %d\n", rc); in ctrl_set_oob()
10237 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10238 if (rc != 0) { in ctrl_set_oob()
10239 pr_err("error %d\n", rc); in ctrl_set_oob()
10242 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0); in ctrl_set_oob()
10243 if (rc != 0) { in ctrl_set_oob()
10244 pr_err("error %d\n", rc); in ctrl_set_oob()
10249 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0); in ctrl_set_oob()
10250 if (rc != 0) { in ctrl_set_oob()
10251 pr_err("error %d\n", rc); in ctrl_set_oob()
10254 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10255 if (rc != 0) { in ctrl_set_oob()
10256 pr_err("error %d\n", rc); in ctrl_set_oob()
10259 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0); in ctrl_set_oob()
10260 if (rc != 0) { in ctrl_set_oob()
10261 pr_err("error %d\n", rc); in ctrl_set_oob()
10264 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10265 if (rc != 0) { in ctrl_set_oob()
10266 pr_err("error %d\n", rc); in ctrl_set_oob()
10269 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0); in ctrl_set_oob()
10270 if (rc != 0) { in ctrl_set_oob()
10271 pr_err("error %d\n", rc); in ctrl_set_oob()
10276 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0); in ctrl_set_oob()
10277 if (rc != 0) { in ctrl_set_oob()
10278 pr_err("error %d\n", rc); in ctrl_set_oob()
10281 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10282 if (rc != 0) { in ctrl_set_oob()
10283 pr_err("error %d\n", rc); in ctrl_set_oob()
10286 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0); in ctrl_set_oob()
10287 if (rc != 0) { in ctrl_set_oob()
10288 pr_err("error %d\n", rc); in ctrl_set_oob()
10291 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10292 if (rc != 0) { in ctrl_set_oob()
10293 pr_err("error %d\n", rc); in ctrl_set_oob()
10296 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0); in ctrl_set_oob()
10297 if (rc != 0) { in ctrl_set_oob()
10298 pr_err("error %d\n", rc); in ctrl_set_oob()
10303 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0); in ctrl_set_oob()
10304 if (rc != 0) { in ctrl_set_oob()
10305 pr_err("error %d\n", rc); in ctrl_set_oob()
10308 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10309 if (rc != 0) { in ctrl_set_oob()
10310 pr_err("error %d\n", rc); in ctrl_set_oob()
10313 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0); in ctrl_set_oob()
10314 if (rc != 0) { in ctrl_set_oob()
10315 pr_err("error %d\n", rc); in ctrl_set_oob()
10318 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10319 if (rc != 0) { in ctrl_set_oob()
10320 pr_err("error %d\n", rc); in ctrl_set_oob()
10323 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0); in ctrl_set_oob()
10324 if (rc != 0) { in ctrl_set_oob()
10325 pr_err("error %d\n", rc); in ctrl_set_oob()
10330 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0); in ctrl_set_oob()
10331 if (rc != 0) { in ctrl_set_oob()
10332 pr_err("error %d\n", rc); in ctrl_set_oob()
10335 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10336 if (rc != 0) { in ctrl_set_oob()
10337 pr_err("error %d\n", rc); in ctrl_set_oob()
10340 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0); in ctrl_set_oob()
10341 if (rc != 0) { in ctrl_set_oob()
10342 pr_err("error %d\n", rc); in ctrl_set_oob()
10345 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0); in ctrl_set_oob()
10346 if (rc != 0) { in ctrl_set_oob()
10347 pr_err("error %d\n", rc); in ctrl_set_oob()
10350 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0); in ctrl_set_oob()
10351 if (rc != 0) { in ctrl_set_oob()
10352 pr_err("error %d\n", rc); in ctrl_set_oob()
10357 …rc = drxdap_fasi_write_block(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)… in ctrl_set_oob()
10358 if (rc != 0) { in ctrl_set_oob()
10359 pr_err("error %d\n", rc); in ctrl_set_oob()
10362 rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0); in ctrl_set_oob()
10363 if (rc != 0) { in ctrl_set_oob()
10364 pr_err("error %d\n", rc); in ctrl_set_oob()
10370 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0); in ctrl_set_oob()
10371 if (rc != 0) { in ctrl_set_oob()
10372 pr_err("error %d\n", rc); in ctrl_set_oob()
10375 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0); in ctrl_set_oob()
10376 if (rc != 0) { in ctrl_set_oob()
10377 pr_err("error %d\n", rc); in ctrl_set_oob()
10381 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0); in ctrl_set_oob()
10382 if (rc != 0) { in ctrl_set_oob()
10383 pr_err("error %d\n", rc); in ctrl_set_oob()
10386 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0); in ctrl_set_oob()
10387 if (rc != 0) { in ctrl_set_oob()
10388 pr_err("error %d\n", rc); in ctrl_set_oob()
10399 rc = scu_command(dev_addr, &scu_cmd); in ctrl_set_oob()
10400 if (rc != 0) { in ctrl_set_oob()
10401 pr_err("error %d\n", rc); in ctrl_set_oob()
10405 rc = set_orx_nsu_aox(demod, true); in ctrl_set_oob()
10406 if (rc != 0) { in ctrl_set_oob()
10407 pr_err("error %d\n", rc); in ctrl_set_oob()
10410 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0); in ctrl_set_oob()
10411 if (rc != 0) { in ctrl_set_oob()
10412 pr_err("error %d\n", rc); in ctrl_set_oob()
10420 return rc; in ctrl_set_oob()
10448 int rc; in ctrl_set_channel() local
10511 rc = ctrl_set_uio_cfg(demod, &uio_cfg); in ctrl_set_channel()
10512 if (rc != 0) { in ctrl_set_channel()
10513 pr_err("error %d\n", rc); in ctrl_set_channel()
10606 rc = ctrl_uio_write(demod, &uio1); in ctrl_set_channel()
10607 if (rc != 0) { in ctrl_set_channel()
10608 pr_err("error %d\n", rc); in ctrl_set_channel()
10613 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); in ctrl_set_channel()
10614 if (rc != 0) { in ctrl_set_channel()
10615 pr_err("error %d\n", rc); in ctrl_set_channel()
10628 rc = set_vsb(demod); in ctrl_set_channel()
10629 if (rc != 0) { in ctrl_set_channel()
10630 pr_err("error %d\n", rc); in ctrl_set_channel()
10633 rc = set_frequency(demod, channel, tuner_freq_offset); in ctrl_set_channel()
10634 if (rc != 0) { in ctrl_set_channel()
10635 pr_err("error %d\n", rc); in ctrl_set_channel()
10643 rc = set_qam_channel(demod, channel, tuner_freq_offset); in ctrl_set_channel()
10644 if (rc != 0) { in ctrl_set_channel()
10645 pr_err("error %d\n", rc); in ctrl_set_channel()
10660 return rc; in ctrl_set_channel()
10687 int rc; in ctrl_sig_quality() local
10691 rc = get_sig_strength(demod, &strength); in ctrl_sig_quality()
10692 if (rc < 0) { in ctrl_sig_quality()
10693 pr_err("error getting signal strength %d\n", rc); in ctrl_sig_quality()
10703 rc = get_acc_pkt_err(demod, &pkt); in ctrl_sig_quality()
10704 if (rc != 0) { in ctrl_sig_quality()
10705 pr_err("error %d\n", rc); in ctrl_sig_quality()
10718 rc = get_vsb_post_rs_pck_err(dev_addr, &err, &pkt); in ctrl_sig_quality()
10719 if (rc != 0) { in ctrl_sig_quality()
10720 pr_err("error %d getting UCB\n", rc); in ctrl_sig_quality()
10730 rc = get_vs_bpre_viterbi_ber(dev_addr, &ber, &cnt); in ctrl_sig_quality()
10731 if (rc != 0) { in ctrl_sig_quality()
10732 pr_err("error %d getting pre-ber\n", rc); in ctrl_sig_quality()
10741 rc = get_vs_bpost_viterbi_ber(dev_addr, &ber, &cnt); in ctrl_sig_quality()
10742 if (rc != 0) { in ctrl_sig_quality()
10743 pr_err("error %d getting post-ber\n", rc); in ctrl_sig_quality()
10751 rc = get_vsbmer(dev_addr, &mer); in ctrl_sig_quality()
10752 if (rc != 0) { in ctrl_sig_quality()
10753 pr_err("error %d getting MER\n", rc); in ctrl_sig_quality()
10765 rc = ctrl_get_qam_sig_quality(demod); in ctrl_sig_quality()
10766 if (rc != 0) { in ctrl_sig_quality()
10767 pr_err("error %d\n", rc); in ctrl_sig_quality()
10778 return rc; in ctrl_sig_quality()
10803 int rc; in ctrl_lock_status() local
10842 rc = scu_command(dev_addr, &cmd_scu); in ctrl_lock_status()
10843 if (rc != 0) { in ctrl_lock_status()
10844 pr_err("error %d\n", rc); in ctrl_lock_status()
10866 return rc; in ctrl_lock_status()
10885 int rc; in ctrl_set_standard() local
10903 rc = power_down_qam(demod, false); in ctrl_set_standard()
10904 if (rc != 0) { in ctrl_set_standard()
10905 pr_err("error %d\n", rc); in ctrl_set_standard()
10911 rc = power_down_vsb(demod, false); in ctrl_set_standard()
10912 if (rc != 0) { in ctrl_set_standard()
10913 pr_err("error %d\n", rc); in ctrl_set_standard()
10938 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); in ctrl_set_standard()
10939 if (rc != 0) { in ctrl_set_standard()
10940 pr_err("error %d\n", rc); in ctrl_set_standard()
10947 rc = set_vsb_leak_n_gain(demod); in ctrl_set_standard()
10948 if (rc != 0) { in ctrl_set_standard()
10949 pr_err("error %d\n", rc); in ctrl_set_standard()
10963 return rc; in ctrl_set_standard()
11045 int rc; in ctrl_power_mode() local
11082 rc = power_up_device(demod); in ctrl_power_mode()
11083 if (rc != 0) { in ctrl_power_mode()
11084 pr_err("error %d\n", rc); in ctrl_power_mode()
11110 rc = power_down_qam(demod, true); in ctrl_power_mode()
11111 if (rc != 0) { in ctrl_power_mode()
11112 pr_err("error %d\n", rc); in ctrl_power_mode()
11117 rc = power_down_vsb(demod, true); in ctrl_power_mode()
11118 if (rc != 0) { in ctrl_power_mode()
11119 pr_err("error %d\n", rc); in ctrl_power_mode()
11130 rc = power_down_atv(demod, ext_attr->standard, true); in ctrl_power_mode()
11131 if (rc != 0) { in ctrl_power_mode()
11132 pr_err("error %d\n", rc); in ctrl_power_mode()
11147 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0); in ctrl_power_mode()
11148 if (rc != 0) { in ctrl_power_mode()
11149 pr_err("error %d\n", rc); in ctrl_power_mode()
11152 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0); in ctrl_power_mode()
11153 if (rc != 0) { in ctrl_power_mode()
11154 pr_err("error %d\n", rc); in ctrl_power_mode()
11160 rc = init_hi(demod); in ctrl_power_mode()
11161 if (rc != 0) { in ctrl_power_mode()
11162 pr_err("error %d\n", rc); in ctrl_power_mode()
11167 rc = hi_cfg_command(demod); in ctrl_power_mode()
11168 if (rc != 0) { in ctrl_power_mode()
11169 pr_err("error %d\n", rc); in ctrl_power_mode()
11179 return rc; in ctrl_power_mode()
11202 int rc; in ctrl_set_cfg_pre_saw() local
11219 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0); in ctrl_set_cfg_pre_saw()
11220 if (rc != 0) { in ctrl_set_cfg_pre_saw()
11221 pr_err("error %d\n", rc); in ctrl_set_cfg_pre_saw()
11244 return rc; in ctrl_set_cfg_pre_saw()
11265 int rc; in ctrl_set_cfg_afe_gain() local
11300 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, gain, 0); in ctrl_set_cfg_afe_gain()
11301 if (rc != 0) { in ctrl_set_cfg_afe_gain()
11302 pr_err("error %d\n", rc); in ctrl_set_cfg_afe_gain()
11325 return rc; in ctrl_set_cfg_afe_gain()
11358 int rc; in drxj_open() local
11377 rc = ctrl_power_mode(demod, &power_mode); in drxj_open()
11378 if (rc != 0) { in drxj_open()
11379 pr_err("error %d\n", rc); in drxj_open()
11383 rc = -EINVAL; in drxj_open()
11389 rc = get_device_capabilities(demod); in drxj_open()
11390 if (rc != 0) { in drxj_open()
11391 pr_err("error %d\n", rc); in drxj_open()
11403 …rc = drxj_dap_write_reg16(dev_addr, SIO_CC_SOFT_RST__A, (0x04 | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SO… in drxj_open()
11404 if (rc != 0) { in drxj_open()
11405 pr_err("error %d\n", rc); in drxj_open()
11408 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0); in drxj_open()
11409 if (rc != 0) { in drxj_open()
11410 pr_err("error %d\n", rc); in drxj_open()
11417 …rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_… in drxj_open()
11418 if (rc != 0) { in drxj_open()
11419 pr_err("error %d\n", rc); in drxj_open()
11423 rc = set_iqm_af(demod, false); in drxj_open()
11424 if (rc != 0) { in drxj_open()
11425 pr_err("error %d\n", rc); in drxj_open()
11428 rc = set_orx_nsu_aox(demod, false); in drxj_open()
11429 if (rc != 0) { in drxj_open()
11430 pr_err("error %d\n", rc); in drxj_open()
11434 rc = init_hi(demod); in drxj_open()
11435 if (rc != 0) { in drxj_open()
11436 pr_err("error %d\n", rc); in drxj_open()
11444 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); in drxj_open()
11445 if (rc != 0) { in drxj_open()
11446 pr_err("error %d\n", rc); in drxj_open()
11450 rc = power_down_aud(demod); in drxj_open()
11451 if (rc != 0) { in drxj_open()
11452 pr_err("error %d\n", rc); in drxj_open()
11456 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP, 0); in drxj_open()
11457 if (rc != 0) { in drxj_open()
11458 pr_err("error %d\n", rc); in drxj_open()
11474 rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_UPLOAD); in drxj_open()
11475 if (rc != 0) { in drxj_open()
11476 pr_err("error %d while uploading the firmware\n", rc); in drxj_open()
11480 rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_VERIFY); in drxj_open()
11481 if (rc != 0) { in drxj_open()
11483 rc); in drxj_open()
11491 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); in drxj_open()
11492 if (rc != 0) { in drxj_open()
11493 pr_err("error %d\n", rc); in drxj_open()
11504 rc = smart_ant_init(demod); in drxj_open()
11505 if (rc != 0) { in drxj_open()
11506 pr_err("error %d\n", rc); in drxj_open()
11529 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16)(driver_version >> 16), 0); in drxj_open()
11530 if (rc != 0) { in drxj_open()
11531 pr_err("error %d\n", rc); in drxj_open()
11534 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_LO__A, (u16)(driver_version & 0xFFFF), 0); in drxj_open()
11535 if (rc != 0) { in drxj_open()
11536 pr_err("error %d\n", rc); in drxj_open()
11540 rc = ctrl_set_oob(demod, NULL); in drxj_open()
11541 if (rc != 0) { in drxj_open()
11542 pr_err("error %d\n", rc); in drxj_open()
11554 return rc; in drxj_open()
11567 int rc; in drxj_close() local
11578 rc = ctrl_power_mode(demod, &power_mode); in drxj_close()
11579 if (rc != 0) { in drxj_close()
11580 pr_err("error %d\n", rc); in drxj_close()
11584 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); in drxj_close()
11585 if (rc != 0) { in drxj_close()
11586 pr_err("error %d\n", rc); in drxj_close()
11590 rc = ctrl_power_mode(demod, &power_mode); in drxj_close()
11591 if (rc != 0) { in drxj_close()
11592 pr_err("error %d\n", rc); in drxj_close()
11602 return rc; in drxj_close()
11747 int rc; in drx_ctrl_u_code() local
11765 rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent); in drx_ctrl_u_code()
11766 if (rc < 0) { in drx_ctrl_u_code()
11768 return rc; in drx_ctrl_u_code()
11773 rc = -EINVAL; in drx_ctrl_u_code()
11793 rc = -EINVAL; in drx_ctrl_u_code()
11799 rc = drx_check_firmware(demod, (u8 *)mc_data_init, size); in drx_ctrl_u_code()
11800 if (rc) in drx_ctrl_u_code()
11835 rc = -EINVAL; in drx_ctrl_u_code()
11852 rc = -EIO; in drx_ctrl_u_code()
11911 return rc; in drx_ctrl_u_code()
12226 int rc = 0; in drx39xxj_init() local
12231 rc = drxj_open(demod); in drx39xxj_init()
12232 if (rc != 0) in drx39xxj_init()
12233 pr_err("drx39xxj_init(): DRX open failed rc=%d!\n", rc); in drx39xxj_init()
12237 return rc; in drx39xxj_init()