Lines Matching refs:dib8000_read_word
196 static u16 dib8000_read_word(struct dib8000_state *state, u16 reg) in dib8000_read_word() function
400 u16 nud = dib8000_read_word(state, 298); in dib8000_set_acquisition_mode()
413 smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1); in dib8000_set_output_mode()
469 u16 tmp, sync_wait = dib8000_read_word(state, 273) & 0xfff0; in dib8000_set_diversity_in()
497 tmp = dib8000_read_word(state, 903); in dib8000_set_diversity_in()
509 reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3, in dib8000_set_power_mode()
513 reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00; in dib8000_set_power_mode()
515 reg_1280 = (dib8000_read_word(state, 1280) & 0x707f) | 0x8f80; in dib8000_set_power_mode()
549 u16 reg, reg_907 = dib8000_read_word(state, 907); in dib8000_set_adc_state()
550 u16 reg_908 = dib8000_read_word(state, 908); in dib8000_set_adc_state()
559 reg = dib8000_read_word(state, 1925); in dib8000_set_adc_state()
565 reg = dib8000_read_word(state, 1925); in dib8000_set_adc_state()
570 reg = dib8000_read_word(state, 921) & ~((0x3 << 14) in dib8000_set_adc_state()
581 reg = dib8000_read_word(state, 1925); in dib8000_set_adc_state()
733 reg = dib8000_read_word(state, 1857); in dib8000_reset_pll()
736 reg = dib8000_read_word(state, 1858); /* Force clk out pll /2 */ in dib8000_reset_pll()
749 u16 reg_1857, reg_1856 = dib8000_read_word(state, 1856); in dib8000_update_pll()
764 reg_1857 = dib8000_read_word(state, 1857); in dib8000_update_pll()
786 while (((dib8000_read_word(state, 1856)>>15)&0x1) != 1) in dib8000_update_pll()
790 reg_1856 = dib8000_read_word(state, 1856); in dib8000_update_pll()
803 dib8000_write_word(state, 902, dib8000_read_word(state, 902) | (1<<3)); /* bypass PLL */ in dib8000_update_pll()
838 st->cfg.gpio_dir = dib8000_read_word(st, 1029); in dib8000_cfg_gpio()
843 st->cfg.gpio_val = dib8000_read_word(st, 1030); in dib8000_cfg_gpio()
1124 dib8000_write_word(state, 1285, dib8000_read_word(state, 1285) & ~(1 << 1)); in dib8000_reset()
1134 dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); in dib8000_reset()
1156 dyn_gain = dib8000_read_word(state, 390); in dib8000_update_lna()
1209 reg = dib8000_read_word(state, 922) & (0x3 << 2); in dib8000_set_agc_config()
1226 (dib8000_read_word(state, 923) & 0xffe3) | in dib8000_set_agc_config()
1247 agc = dib8000_read_word(state, 390); in dib8000_agc_soft_split()
1261 dib8000_write_word(state, 107, (dib8000_read_word(state, 107) & 0xff00) | split_offset); in dib8000_agc_soft_split()
1282 reg = dib8000_read_word(state, 1947)&0xff00; in dib8000_agc_startup()
1290 reg = dib8000_read_word(state, 1920); in dib8000_agc_startup()
1351 reg = dib8000_read_word(state, 1798) & in dib8096p_host_bus_drive()
1357 reg = dib8000_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8)); in dib8096p_host_bus_drive()
1362 reg = dib8000_read_word(state, 1800) & in dib8096p_host_bus_drive()
1368 reg = dib8000_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8)); in dib8096p_host_bus_drive()
1373 reg = dib8000_read_word(state, 1802) & in dib8096p_host_bus_drive()
1444 reg_1287 = dib8000_read_word(state, 1287); in dib8096p_enMpegMux()
1480 u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 7); in dib8096p_setDibTxMux()
1503 u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 4); in dib8096p_setHostBusMux()
1540 reg_1287 = dib8000_read_word(state, 1287); in dib8096p_set_diversity_in()
1572 smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1); in dib8096p_set_output_mode()
1573 outreg = dib8000_read_word(state, 1286) & in dib8096p_set_output_mode()
1682 n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1; in dib8096p_tuner_write_serpar()
1703 n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1; in dib8096p_tuner_read_serpar()
1712 n_empty = dib8000_read_word(state, 1984)&0x1; in dib8096p_tuner_read_serpar()
1718 read_word = dib8000_read_word(state, 1987); in dib8096p_tuner_read_serpar()
1747 word = dib8000_read_word(state, apb_address); in dib8096p_rw_on_apb()
1848 i = ((dib8000_read_word(state, 921) >> 12)&0x3); in dib8096p_tuner_xfer()
1849 word = dib8000_read_word(state, 924+i); in dib8096p_tuner_xfer()
1859 word = (dib8000_read_word(state, 921) & in dib8096p_tuner_xfer()
1898 en_cur_state = dib8000_read_word(state, 1922); in dib8096p_tuner_sleep()
1947 val = dib8000_read_word(state, 403); in dib8090p_get_dc_power()
1950 val = dib8000_read_word(state, 404); in dib8090p_get_dc_power()
2182 reg_1 = dib8000_read_word(state, 1); in dib8000_set_subchannel_prbs()
2279 dib8000_write_word(state, 219, dib8000_read_word(state, 219) | 0x1); /* adp_pass =1 */ in dib8000_set_sb_channel()
2280 …dib8000_write_word(state, 190, dib8000_read_word(state, 190) | (0x1 << 14)); /* pha3_force_pha_shi… in dib8000_set_sb_channel()
2282 dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); /* adp_pass =0 */ in dib8000_set_sb_channel()
2283 …dib8000_write_word(state, 190, dib8000_read_word(state, 190) & 0xbfff); /* pha3_force_pha_shift = … in dib8000_set_sb_channel()
2291 dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200); in dib8000_set_sb_channel()
2319 dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); /* P_cspu_win_cut = 0 */ in dib8000_set_sb_channel()
2361 tmp = dib8000_read_word(state, 1); in dib8000_set_isdbt_common_channel()
2364 …dib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) | ((c->isdbt_partial_recep… in dib8000_set_isdbt_common_channel()
2381 dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200); in dib8000_set_isdbt_common_channel()
2507 …dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x1fff) | (0 << 13) | (1 << 15)); /* P… in dib8000_autosearch_start()
2508 dib8000_write_word(state, 1, (dib8000_read_word(state, 1) & 0xfffc) | 0); /* P_guard = 0 */ in dib8000_autosearch_start()
2512 …dib8000_write_word(state, 10, (dib8000_read_word(state, 10) & 0x200) | (16 << 4) | (0 << 0)); /* P… in dib8000_autosearch_start()
2527 …dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (0 << 8)); /* P_corm_alpha… in dib8000_autosearch_start()
2529 …dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (9 << 8)); /* P_corm_alpha… in dib8000_autosearch_start()
2536 …dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (1 << 13)); /* P_restart… in dib8000_autosearch_start()
2537 …dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (0 << 13)); /* P_restart… in dib8000_autosearch_start()
2538 …dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x7ff) | (0 << 15) | (1 << 13)); /* P_… in dib8000_autosearch_start()
2574 value = dib8000_read_word(state, 0); in dib8000_autosearch_start()
2576 dib8000_read_word(state, 1284); /* reset the INT. n_irq_pending */ in dib8000_autosearch_start()
2590 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); in dib8000_autosearch_start()
2597 …dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); /* P_mode = 1 t… in dib8000_autosearch_start()
2606 …dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); /* P_mode = 1 */ in dib8000_autosearch_start()
2629 value = dib8000_read_word(state, 0); in dib8000_autosearch_start()
2631 dib8000_read_word(state, 1284); /* reset the INT. n_irq_pending */ in dib8000_autosearch_start()
2640 u16 irq_pending = dib8000_read_word(state, 1284); in dib8000_autosearch_irq()
2667 tmp = dib8000_read_word(state, 771); in dib8000_viterbi_state()
2733 i = dib8000_read_word(state, 26) & 1; /* P_dds_invspec */ in dib8000_set_frequency_offset()
2738 dib8000_write_word(state, 26, dib8000_read_word(state, 26) | 1); in dib8000_set_frequency_offset()
2845 dib8000_write_word(state, 273, (dib8000_read_word(state, 273) & 0x000f) | (sync_wait << 4)); in dib8000_set_sync_wait()
2890 return dib8000_read_word(state, 570); in dib8000_read_lock()
2891 return dib8000_read_word(state, 568); in dib8000_read_lock()
2899 reg = dib8000_read_word(state, 274) & 0xfff0; in dib8090p_init_sdram()
2904 reg = dib8000_read_word(state, 1280); in dib8090p_init_sdram()
3035 dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60); in dib8000_tune()
3043 state->agc1_max = dib8000_read_word(state, 108); in dib8000_tune()
3044 state->agc1_min = dib8000_read_word(state, 109); in dib8000_tune()
3045 state->agc2_max = dib8000_read_word(state, 110); in dib8000_tune()
3046 state->agc2_min = dib8000_read_word(state, 111); in dib8000_tune()
3047 agc1 = dib8000_read_word(state, 388); in dib8000_tune()
3048 agc2 = dib8000_read_word(state, 389); in dib8000_tune()
3101 corm[2] = (dib8000_read_word(state, 596) << 16) | (dib8000_read_word(state, 597)); in dib8000_tune()
3102 corm[1] = (dib8000_read_word(state, 598) << 16) | (dib8000_read_word(state, 599)); in dib8000_tune()
3103 corm[0] = (dib8000_read_word(state, 600) << 16) | (dib8000_read_word(state, 601)); in dib8000_tune()
3105 corm[2] = (dib8000_read_word(state, 594) << 16) | (dib8000_read_word(state, 595)); in dib8000_tune()
3106 corm[1] = (dib8000_read_word(state, 596) << 16) | (dib8000_read_word(state, 597)); in dib8000_tune()
3107 corm[0] = (dib8000_read_word(state, 598) << 16) | (dib8000_read_word(state, 599)); in dib8000_tune()
3141 state->found_guard = dib8000_read_word(state, 572) & 0x3; in dib8000_tune()
3143 state->found_guard = dib8000_read_word(state, 570) & 0x3; in dib8000_tune()
3169 locks = (dib8000_read_word(state, 180) >> 6) & 0x3f; /* P_coff_winlen ? */ in dib8000_tune()
3181 …*timeout = dib8000_get_timeout(state, (20 * ((dib8000_read_word(state, 188)>>5)&0x1f)), SYMBOL_DEP… in dib8000_tune()
3236 …if ((state->revision == 0x8090) || ((dib8000_read_word(state, 1291) >> 9) & 0x1)) { /* fe capable … in dib8000_tune()
3434 c->isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1; in dib8000_get_frontend()
3437 val = dib8000_read_word(state, 572); in dib8000_get_frontend()
3439 val = dib8000_read_word(state, 570); in dib8000_get_frontend()
3476 val = dib8000_read_word(state, 505); in dib8000_get_frontend()
3483 val = dib8000_read_word(state, 493 + i) & 0x0f; in dib8000_get_frontend()
3495 val = dib8000_read_word(state, 499 + i) & 0x3; in dib8000_get_frontend()
3504 val = dib8000_read_word(state, 481 + i); in dib8000_get_frontend()
3533 val = dib8000_read_word(state, 487 + i); in dib8000_get_frontend()
3768 lock = dib8000_read_word(state, 554); /* Viterbi Layer A */ in dib8000_read_status()
3772 lock = dib8000_read_word(state, 555); /* Viterbi Layer B */ in dib8000_read_status()
3776 lock = dib8000_read_word(state, 556); /* Viterbi Layer C */ in dib8000_read_status()
3791 *ber = (dib8000_read_word(state, 562) << 16) | in dib8000_read_ber()
3792 dib8000_read_word(state, 563); in dib8000_read_ber()
3794 *ber = (dib8000_read_word(state, 560) << 16) | in dib8000_read_ber()
3795 dib8000_read_word(state, 561); in dib8000_read_ber()
3805 *unc = dib8000_read_word(state, 567); in dib8000_read_unc_blocks()
3807 *unc = dib8000_read_word(state, 565); in dib8000_read_unc_blocks()
3826 val = 65535 - dib8000_read_word(state, 390); in dib8000_read_signal_strength()
3841 val = dib8000_read_word(state, 542); in dib8000_get_snr()
3843 val = dib8000_read_word(state, 544); in dib8000_get_snr()
3851 val = dib8000_read_word(state, 543); in dib8000_get_snr()
3853 val = dib8000_read_word(state, 545); in dib8000_get_snr()
4211 val = dib8000_read_word(state, per_layer_regs[i].ber); in dib8000_get_stats()
4220 val = dib8000_read_word(state, per_layer_regs[i].per); in dib8000_get_stats()
4372 u16 val = dib8000_read_word(st, 299) & 0xffef; in dib8000_pid_filter_ctrl()
4468 …dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); /* ber_rs_len … in dib8000_init()