Lines Matching +full:default +full:- +full:state
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Linux-DVB Driver for DiBcom's DiB7000M and
4 * first generation DiB7000P-demodulator-family.
6 * Copyright (C) 2005-7 DiBcom (http://www.dibcom.fr/)
22 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
76 static u16 dib7000m_read_word(struct dib7000m_state *state, u16 reg) in dib7000m_read_word() argument
80 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib7000m_read_word()
85 state->i2c_write_buffer[0] = (reg >> 8) | 0x80; in dib7000m_read_word()
86 state->i2c_write_buffer[1] = reg & 0xff; in dib7000m_read_word()
88 memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); in dib7000m_read_word()
89 state->msg[0].addr = state->i2c_addr >> 1; in dib7000m_read_word()
90 state->msg[0].flags = 0; in dib7000m_read_word()
91 state->msg[0].buf = state->i2c_write_buffer; in dib7000m_read_word()
92 state->msg[0].len = 2; in dib7000m_read_word()
93 state->msg[1].addr = state->i2c_addr >> 1; in dib7000m_read_word()
94 state->msg[1].flags = I2C_M_RD; in dib7000m_read_word()
95 state->msg[1].buf = state->i2c_read_buffer; in dib7000m_read_word()
96 state->msg[1].len = 2; in dib7000m_read_word()
98 if (i2c_transfer(state->i2c_adap, state->msg, 2) != 2) in dib7000m_read_word()
101 ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1]; in dib7000m_read_word()
102 mutex_unlock(&state->i2c_buffer_lock); in dib7000m_read_word()
107 static int dib7000m_write_word(struct dib7000m_state *state, u16 reg, u16 val) in dib7000m_write_word() argument
111 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib7000m_write_word()
113 return -EINVAL; in dib7000m_write_word()
116 state->i2c_write_buffer[0] = (reg >> 8) & 0xff; in dib7000m_write_word()
117 state->i2c_write_buffer[1] = reg & 0xff; in dib7000m_write_word()
118 state->i2c_write_buffer[2] = (val >> 8) & 0xff; in dib7000m_write_word()
119 state->i2c_write_buffer[3] = val & 0xff; in dib7000m_write_word()
121 memset(&state->msg[0], 0, sizeof(struct i2c_msg)); in dib7000m_write_word()
122 state->msg[0].addr = state->i2c_addr >> 1; in dib7000m_write_word()
123 state->msg[0].flags = 0; in dib7000m_write_word()
124 state->msg[0].buf = state->i2c_write_buffer; in dib7000m_write_word()
125 state->msg[0].len = 4; in dib7000m_write_word()
127 ret = (i2c_transfer(state->i2c_adap, state->msg, 1) != 1 ? in dib7000m_write_word()
128 -EREMOTEIO : 0); in dib7000m_write_word()
129 mutex_unlock(&state->i2c_buffer_lock); in dib7000m_write_word()
132 static void dib7000m_write_tab(struct dib7000m_state *state, u16 *buf) in dib7000m_write_tab() argument
140 if (state->reg_offs && (r >= 112 && r <= 331)) // compensate for 7000MC in dib7000m_write_tab()
144 dib7000m_write_word(state, r, *n++); in dib7000m_write_tab()
146 } while (--l); in dib7000m_write_tab()
151 static int dib7000m_set_output_mode(struct dib7000m_state *state, int mode) in dib7000m_set_output_mode() argument
155 sram = 0x0005; /* by default SRAM output is disabled */ in dib7000m_set_output_mode()
159 smo_mode = (dib7000m_read_word(state, 294 + state->reg_offs) & 0x0010) | (1 << 1); in dib7000m_set_output_mode()
161 dprintk("setting output mode for demod %p to %d\n", &state->demod, mode); in dib7000m_set_output_mode()
174 if (state->cfg.hostbus_diversity) in dib7000m_set_output_mode()
187 default: in dib7000m_set_output_mode()
188 dprintk("Unhandled output_mode passed to be set for demod %p\n", &state->demod); in dib7000m_set_output_mode()
192 if (state->cfg.output_mpeg2_in_188_bytes) in dib7000m_set_output_mode()
195 ret |= dib7000m_write_word(state, 294 + state->reg_offs, smo_mode); in dib7000m_set_output_mode()
196 ret |= dib7000m_write_word(state, 295 + state->reg_offs, fifo_threshold); /* synchronous fread */ in dib7000m_set_output_mode()
197 ret |= dib7000m_write_word(state, 1795, outreg); in dib7000m_set_output_mode()
198 ret |= dib7000m_write_word(state, 1805, sram); in dib7000m_set_output_mode()
200 if (state->revision == 0x4003) { in dib7000m_set_output_mode()
201 u16 clk_cfg1 = dib7000m_read_word(state, 909) & 0xfffd; in dib7000m_set_output_mode()
204 dib7000m_write_word(state, 909, clk_cfg1); in dib7000m_set_output_mode()
209 static void dib7000m_set_power_mode(struct dib7000m_state *state, enum dib7000m_power_mode mode) in dib7000m_set_power_mode() argument
211 /* by default everything is going to be powered off */ in dib7000m_set_power_mode()
222 /* just leave power on the control-interfaces: GPIO and (I2C or SDIO or SRAM) */ in dib7000m_set_power_mode()
245 if (!state->cfg.mobile_mode) in dib7000m_set_power_mode()
249 if (state->revision != 0x4000) in dib7000m_set_power_mode()
252 if (state->revision == 0x4003) in dib7000m_set_power_mode()
255 dib7000m_write_word(state, 903 + offset, reg_903); in dib7000m_set_power_mode()
256 dib7000m_write_word(state, 904 + offset, reg_904); in dib7000m_set_power_mode()
257 dib7000m_write_word(state, 905 + offset, reg_905); in dib7000m_set_power_mode()
258 dib7000m_write_word(state, 906 + offset, reg_906); in dib7000m_set_power_mode()
261 static int dib7000m_set_adc_state(struct dib7000m_state *state, enum dibx000_adc_states no) in dib7000m_set_adc_state() argument
264 u16 reg_913 = dib7000m_read_word(state, 913), in dib7000m_set_adc_state()
265 reg_914 = dib7000m_read_word(state, 914); in dib7000m_set_adc_state()
270 ret |= dib7000m_write_word(state, 914, reg_914); in dib7000m_set_adc_state()
279 if (state->revision == 0x4000) { // workaround for PA/MA in dib7000m_set_adc_state()
280 // power-up ADC in dib7000m_set_adc_state()
281 dib7000m_write_word(state, 913, 0); in dib7000m_set_adc_state()
282 dib7000m_write_word(state, 914, reg_914 & 0x3); in dib7000m_set_adc_state()
283 // power-down bandgag in dib7000m_set_adc_state()
284 dib7000m_write_word(state, 913, (1 << 15)); in dib7000m_set_adc_state()
285 dib7000m_write_word(state, 914, reg_914 & 0x3); in dib7000m_set_adc_state()
305 default: in dib7000m_set_adc_state()
310 ret |= dib7000m_write_word(state, 913, reg_913); in dib7000m_set_adc_state()
311 ret |= dib7000m_write_word(state, 914, reg_914); in dib7000m_set_adc_state()
316 static int dib7000m_set_bandwidth(struct dib7000m_state *state, u32 bw) in dib7000m_set_bandwidth() argument
324 state->current_bandwidth = bw; in dib7000m_set_bandwidth()
326 if (state->timf == 0) { in dib7000m_set_bandwidth()
327 dprintk("using default timf\n"); in dib7000m_set_bandwidth()
328 timf = state->timf_default; in dib7000m_set_bandwidth()
331 timf = state->timf; in dib7000m_set_bandwidth()
336 dib7000m_write_word(state, 23, (u16) ((timf >> 16) & 0xffff)); in dib7000m_set_bandwidth()
337 dib7000m_write_word(state, 24, (u16) ((timf ) & 0xffff)); in dib7000m_set_bandwidth()
344 struct dib7000m_state *state = demod->demodulator_priv; in dib7000m_set_diversity_in() local
346 if (state->div_force_off) { in dib7000m_set_diversity_in()
347 dprintk("diversity combination deactivated - forced by COFDM parameters\n"); in dib7000m_set_diversity_in()
350 state->div_state = (u8)onoff; in dib7000m_set_diversity_in()
353 dib7000m_write_word(state, 263 + state->reg_offs, 6); in dib7000m_set_diversity_in()
354 dib7000m_write_word(state, 264 + state->reg_offs, 6); in dib7000m_set_diversity_in()
355 …dib7000m_write_word(state, 266 + state->reg_offs, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0… in dib7000m_set_diversity_in()
357 dib7000m_write_word(state, 263 + state->reg_offs, 1); in dib7000m_set_diversity_in()
358 dib7000m_write_word(state, 264 + state->reg_offs, 0); in dib7000m_set_diversity_in()
359 dib7000m_write_word(state, 266 + state->reg_offs, 0); in dib7000m_set_diversity_in()
365 static int dib7000m_sad_calib(struct dib7000m_state *state) in dib7000m_sad_calib() argument
369 // dib7000m_write_word(state, 928, (3 << 14) | (1 << 12) | (524 << 0)); // sampling clock of the SA… in dib7000m_sad_calib()
370 dib7000m_write_word(state, 929, (0 << 1) | (0 << 0)); in dib7000m_sad_calib()
371 dib7000m_write_word(state, 930, 776); // 0.625*3.3 / 4096 in dib7000m_sad_calib()
374 dib7000m_write_word(state, 929, (1 << 0)); in dib7000m_sad_calib()
375 dib7000m_write_word(state, 929, (0 << 0)); in dib7000m_sad_calib()
382 static void dib7000m_reset_pll_common(struct dib7000m_state *state, const struct dibx000_bandwidth_… in dib7000m_reset_pll_common() argument
384 dib7000m_write_word(state, 18, (u16) (((bw->internal*1000) >> 16) & 0xffff)); in dib7000m_reset_pll_common()
385 dib7000m_write_word(state, 19, (u16) ( (bw->internal*1000) & 0xffff)); in dib7000m_reset_pll_common()
386 dib7000m_write_word(state, 21, (u16) ( (bw->ifreq >> 16) & 0xffff)); in dib7000m_reset_pll_common()
387 dib7000m_write_word(state, 22, (u16) ( bw->ifreq & 0xffff)); in dib7000m_reset_pll_common()
389 dib7000m_write_word(state, 928, bw->sad_cfg); in dib7000m_reset_pll_common()
392 static void dib7000m_reset_pll(struct dib7000m_state *state) in dib7000m_reset_pll() argument
394 const struct dibx000_bandwidth_config *bw = state->cfg.bw; in dib7000m_reset_pll()
397 /* default */ in dib7000m_reset_pll()
398 reg_907 = (bw->pll_bypass << 15) | (bw->modulo << 7) | in dib7000m_reset_pll()
399 (bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) | in dib7000m_reset_pll()
400 (bw->enable_refdiv << 1) | (0 << 0); in dib7000m_reset_pll()
401 reg_910 = (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset; in dib7000m_reset_pll()
403 …// for this oscillator frequency should be 30 MHz for the Master (default values in the board_para… in dib7000m_reset_pll()
405 if (!state->cfg.quartz_direct) { in dib7000m_reset_pll()
408 // if the previous front-end is baseband, its output frequency is 15 MHz (prev freq divided by 2) in dib7000m_reset_pll()
409 if(state->cfg.input_clk_is_div_2) in dib7000m_reset_pll()
411 …else // otherwise the previous front-end puts out its input (default 30MHz) - no extra division ne… in dib7000m_reset_pll()
414 reg_907 |= (bw->pll_ratio & 0x3f) << 9; in dib7000m_reset_pll()
415 reg_910 |= (bw->pll_prediv << 5); in dib7000m_reset_pll()
418 dib7000m_write_word(state, 910, reg_910); // pll cfg in dib7000m_reset_pll()
419 dib7000m_write_word(state, 907, reg_907); // clk cfg0 in dib7000m_reset_pll()
420 dib7000m_write_word(state, 908, 0x0006); // clk_cfg1 in dib7000m_reset_pll()
422 dib7000m_reset_pll_common(state, bw); in dib7000m_reset_pll()
425 static void dib7000mc_reset_pll(struct dib7000m_state *state) in dib7000mc_reset_pll() argument
427 const struct dibx000_bandwidth_config *bw = state->cfg.bw; in dib7000mc_reset_pll()
431 dib7000m_write_word(state, 907, (bw->pll_prediv << 8) | (bw->pll_ratio << 0)); in dib7000mc_reset_pll()
434 //dib7000m_write_word(state, 908, (1 << 14) | (3 << 12) |(0 << 11) | in dib7000mc_reset_pll()
436 (bw->IO_CLK_en_core << 10) | (bw->bypclk_div << 5) | (bw->enable_refdiv << 4) | in dib7000mc_reset_pll()
437 (1 << 3) | (bw->pll_range << 1) | (bw->pll_reset << 0); in dib7000mc_reset_pll()
438 dib7000m_write_word(state, 908, clk_cfg1); in dib7000mc_reset_pll()
439 clk_cfg1 = (clk_cfg1 & 0xfff7) | (bw->pll_bypass << 3); in dib7000mc_reset_pll()
440 dib7000m_write_word(state, 908, clk_cfg1); in dib7000mc_reset_pll()
443 dib7000m_write_word(state, 910, (1 << 12) | (2 << 10) | (bw->modulo << 8) | (bw->ADClkSrc << 7)); in dib7000mc_reset_pll()
445 dib7000m_reset_pll_common(state, bw); in dib7000mc_reset_pll()
451 dib7000m_write_word(st, 773, st->cfg.gpio_dir); in dib7000m_reset_gpio()
452 dib7000m_write_word(st, 774, st->cfg.gpio_val); in dib7000m_reset_gpio()
456 dib7000m_write_word(st, 775, st->cfg.gpio_pwm_pos); in dib7000m_reset_gpio()
458 dib7000m_write_word(st, 780, st->cfg.pwm_freq_div); in dib7000m_reset_gpio()
539 /* set ADC level to -16 */
541 (1 << 13) - 825 - 117,
542 (1 << 13) - 837 - 117,
543 (1 << 13) - 811 - 117,
544 (1 << 13) - 766 - 117,
545 (1 << 13) - 737 - 117,
546 (1 << 13) - 693 - 117,
547 (1 << 13) - 648 - 117,
548 (1 << 13) - 619 - 117,
549 (1 << 13) - 575 - 117,
550 (1 << 13) - 531 - 117,
551 (1 << 13) - 501 - 117,
563 static int dib7000m_demod_reset(struct dib7000m_state *state) in dib7000m_demod_reset() argument
565 dib7000m_set_power_mode(state, DIB7000M_POWER_ALL); in dib7000m_demod_reset()
567 /* always leave the VBG voltage on - it consumes almost nothing but takes a long time to start */ in dib7000m_demod_reset()
568 dib7000m_set_adc_state(state, DIBX000_VBG_ENABLE); in dib7000m_demod_reset()
571 dib7000m_write_word(state, 898, 0xffff); in dib7000m_demod_reset()
572 dib7000m_write_word(state, 899, 0xffff); in dib7000m_demod_reset()
573 dib7000m_write_word(state, 900, 0xff0f); in dib7000m_demod_reset()
574 dib7000m_write_word(state, 901, 0xfffc); in dib7000m_demod_reset()
576 dib7000m_write_word(state, 898, 0); in dib7000m_demod_reset()
577 dib7000m_write_word(state, 899, 0); in dib7000m_demod_reset()
578 dib7000m_write_word(state, 900, 0); in dib7000m_demod_reset()
579 dib7000m_write_word(state, 901, 0); in dib7000m_demod_reset()
581 if (state->revision == 0x4000) in dib7000m_demod_reset()
582 dib7000m_reset_pll(state); in dib7000m_demod_reset()
584 dib7000mc_reset_pll(state); in dib7000m_demod_reset()
586 if (dib7000m_reset_gpio(state) != 0) in dib7000m_demod_reset()
589 if (dib7000m_set_output_mode(state, OUTMODE_HIGH_Z) != 0) in dib7000m_demod_reset()
593 dib7000m_write_word(state, 1794, dib7000m_read_word(state, 1794) & ~(1 << 1) ); in dib7000m_demod_reset()
595 dib7000m_set_bandwidth(state, 8000); in dib7000m_demod_reset()
597 dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_ON); in dib7000m_demod_reset()
598 dib7000m_sad_calib(state); in dib7000m_demod_reset()
599 dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_OFF); in dib7000m_demod_reset()
601 if (state->cfg.dvbt_mode) in dib7000m_demod_reset()
602 dib7000m_write_word(state, 1796, 0x0); // select DVB-T output in dib7000m_demod_reset()
604 if (state->cfg.mobile_mode) in dib7000m_demod_reset()
605 dib7000m_write_word(state, 261 + state->reg_offs, 2); in dib7000m_demod_reset()
607 dib7000m_write_word(state, 224 + state->reg_offs, 1); in dib7000m_demod_reset()
610 if(state->cfg.tuner_is_baseband) in dib7000m_demod_reset()
611 dib7000m_write_word(state, 36, 0x0755); in dib7000m_demod_reset()
613 dib7000m_write_word(state, 36, 0x1f55); in dib7000m_demod_reset()
616 if (state->revision == 0x4000) in dib7000m_demod_reset()
617 dib7000m_write_word(state, 909, (3 << 10) | (1 << 6)); in dib7000m_demod_reset()
619 dib7000m_write_word(state, 909, (3 << 4) | 1); in dib7000m_demod_reset()
621 dib7000m_write_tab(state, dib7000m_defaults_common); in dib7000m_demod_reset()
622 dib7000m_write_tab(state, dib7000m_defaults); in dib7000m_demod_reset()
624 dib7000m_set_power_mode(state, DIB7000M_POWER_INTERFACE_ONLY); in dib7000m_demod_reset()
626 state->internal_clk = state->cfg.bw->internal; in dib7000m_demod_reset()
631 static void dib7000m_restart_agc(struct dib7000m_state *state) in dib7000m_restart_agc() argument
634 dib7000m_write_word(state, 898, 0x0c00); in dib7000m_restart_agc()
635 dib7000m_write_word(state, 898, 0x0000); in dib7000m_restart_agc()
638 static int dib7000m_agc_soft_split(struct dib7000m_state *state) in dib7000m_agc_soft_split() argument
642 …if(!state->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split.… in dib7000m_agc_soft_split()
646 agc = dib7000m_read_word(state, 390); in dib7000m_agc_soft_split()
648 if (agc > state->current_agc->split.min_thres) in dib7000m_agc_soft_split()
649 split_offset = state->current_agc->split.min; in dib7000m_agc_soft_split()
650 else if (agc < state->current_agc->split.max_thres) in dib7000m_agc_soft_split()
651 split_offset = state->current_agc->split.max; in dib7000m_agc_soft_split()
653 split_offset = state->current_agc->split.max * in dib7000m_agc_soft_split()
654 (agc - state->current_agc->split.min_thres) / in dib7000m_agc_soft_split()
655 (state->current_agc->split.max_thres - state->current_agc->split.min_thres); in dib7000m_agc_soft_split()
660 return dib7000m_write_word(state, 103, (dib7000m_read_word(state, 103) & 0xff00) | split_offset); in dib7000m_agc_soft_split()
663 static int dib7000m_update_lna(struct dib7000m_state *state) in dib7000m_update_lna() argument
667 if (state->cfg.update_lna) { in dib7000m_update_lna()
668 // read dyn_gain here (because it is demod-dependent and not fe) in dib7000m_update_lna()
669 dyn_gain = dib7000m_read_word(state, 390); in dib7000m_update_lna()
671 if (state->cfg.update_lna(&state->demod,dyn_gain)) { // LNA has changed in dib7000m_update_lna()
672 dib7000m_restart_agc(state); in dib7000m_update_lna()
679 static int dib7000m_set_agc_config(struct dib7000m_state *state, u8 band) in dib7000m_set_agc_config() argument
683 if (state->current_band == band && state->current_agc != NULL) in dib7000m_set_agc_config()
685 state->current_band = band; in dib7000m_set_agc_config()
687 for (i = 0; i < state->cfg.agc_config_count; i++) in dib7000m_set_agc_config()
688 if (state->cfg.agc[i].band_caps & band) { in dib7000m_set_agc_config()
689 agc = &state->cfg.agc[i]; in dib7000m_set_agc_config()
695 return -EINVAL; in dib7000m_set_agc_config()
698 state->current_agc = agc; in dib7000m_set_agc_config()
701 dib7000m_write_word(state, 72 , agc->setup); in dib7000m_set_agc_config()
702 dib7000m_write_word(state, 73 , agc->inv_gain); in dib7000m_set_agc_config()
703 dib7000m_write_word(state, 74 , agc->time_stabiliz); in dib7000m_set_agc_config()
704 dib7000m_write_word(state, 97 , (agc->alpha_level << 12) | agc->thlock); in dib7000m_set_agc_config()
707 dib7000m_write_word(state, 98, (agc->alpha_mant << 5) | agc->alpha_exp); in dib7000m_set_agc_config()
708 dib7000m_write_word(state, 99, (agc->beta_mant << 6) | agc->beta_exp); in dib7000m_set_agc_config()
711 …state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, ag… in dib7000m_set_agc_config()
714 if (state->wbd_ref != 0) in dib7000m_set_agc_config()
715 dib7000m_write_word(state, 102, state->wbd_ref); in dib7000m_set_agc_config()
716 else // use default in dib7000m_set_agc_config()
717 dib7000m_write_word(state, 102, agc->wbd_ref); in dib7000m_set_agc_config()
719 dib7000m_write_word(state, 103, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8) ); in dib7000m_set_agc_config()
720 dib7000m_write_word(state, 104, agc->agc1_max); in dib7000m_set_agc_config()
721 dib7000m_write_word(state, 105, agc->agc1_min); in dib7000m_set_agc_config()
722 dib7000m_write_word(state, 106, agc->agc2_max); in dib7000m_set_agc_config()
723 dib7000m_write_word(state, 107, agc->agc2_min); in dib7000m_set_agc_config()
724 dib7000m_write_word(state, 108, (agc->agc1_pt1 << 8) | agc->agc1_pt2 ); in dib7000m_set_agc_config()
725 dib7000m_write_word(state, 109, (agc->agc1_slope1 << 8) | agc->agc1_slope2); in dib7000m_set_agc_config()
726 dib7000m_write_word(state, 110, (agc->agc2_pt1 << 8) | agc->agc2_pt2); in dib7000m_set_agc_config()
727 dib7000m_write_word(state, 111, (agc->agc2_slope1 << 8) | agc->agc2_slope2); in dib7000m_set_agc_config()
729 if (state->revision > 0x4000) { // settings for the MC in dib7000m_set_agc_config()
730 dib7000m_write_word(state, 71, agc->agc1_pt3); in dib7000m_set_agc_config()
732 // (dib7000m_read_word(state, 929) & 0xffe3) | (agc->wbd_inv << 4) | (agc->wbd_sel << 2), agc->wb… in dib7000m_set_agc_config()
733 …dib7000m_write_word(state, 929, (dib7000m_read_word(state, 929) & 0xffe3) | (agc->wbd_inv << 4) | … in dib7000m_set_agc_config()
735 // wrong default values in dib7000m_set_agc_config()
738 dib7000m_write_word(state, 88 + i, b[i]); in dib7000m_set_agc_config()
743 static void dib7000m_update_timf(struct dib7000m_state *state) in dib7000m_update_timf() argument
745 u32 timf = (dib7000m_read_word(state, 436) << 16) | dib7000m_read_word(state, 437); in dib7000m_update_timf()
746 state->timf = timf * 160 / (state->current_bandwidth / 50); in dib7000m_update_timf()
747 dib7000m_write_word(state, 23, (u16) (timf >> 16)); in dib7000m_update_timf()
748 dib7000m_write_word(state, 24, (u16) (timf & 0xffff)); in dib7000m_update_timf()
749 dprintk("updated timf_frequency: %d (default: %d)\n", state->timf, state->timf_default); in dib7000m_update_timf()
754 struct dtv_frontend_properties *ch = &demod->dtv_property_cache; in dib7000m_agc_startup()
755 struct dib7000m_state *state = demod->demodulator_priv; in dib7000m_agc_startup() local
756 u16 cfg_72 = dib7000m_read_word(state, 72); in dib7000m_agc_startup()
757 int ret = -1; in dib7000m_agc_startup()
758 u8 *agc_state = &state->agc_state; in dib7000m_agc_startup()
761 switch (state->agc_state) { in dib7000m_agc_startup()
763 // set power-up level: interf+analog+AGC in dib7000m_agc_startup()
764 dib7000m_set_power_mode(state, DIB7000M_POWER_INTERF_ANALOG_AGC); in dib7000m_agc_startup()
765 dib7000m_set_adc_state(state, DIBX000_ADC_ON); in dib7000m_agc_startup()
767 if (dib7000m_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency/1000)) != 0) in dib7000m_agc_startup()
768 return -1; in dib7000m_agc_startup()
776 if (state->cfg.agc_control) in dib7000m_agc_startup()
777 state->cfg.agc_control(&state->demod, 1); in dib7000m_agc_startup()
779 dib7000m_write_word(state, 75, 32768); in dib7000m_agc_startup()
780 if (!state->current_agc->perform_agc_softsplit) { in dib7000m_agc_startup()
781 /* we are using the wbd - so slow AGC startup */ in dib7000m_agc_startup()
782 dib7000m_write_word(state, 103, 1 << 8); /* force 0 split on WBD and restart AGC */ in dib7000m_agc_startup()
786 /* default AGC startup */ in dib7000m_agc_startup()
792 dib7000m_restart_agc(state); in dib7000m_agc_startup()
796 dib7000m_write_word(state, 72, cfg_72 | (1 << 4)); /* freeze AGC loop */ in dib7000m_agc_startup()
797 dib7000m_write_word(state, 103, 2 << 9); /* fast split search 0.25kHz */ in dib7000m_agc_startup()
803 agc_split = (u8)dib7000m_read_word(state, 392); /* store the split value for the next time */ in dib7000m_agc_startup()
804 dib7000m_write_word(state, 75, dib7000m_read_word(state, 390)); /* set AGC gain start value */ in dib7000m_agc_startup()
806 dib7000m_write_word(state, 72, cfg_72 & ~(1 << 4)); /* std AGC loop */ in dib7000m_agc_startup()
807 …dib7000m_write_word(state, 103, (state->current_agc->wbd_alpha << 9) | agc_split); /* standard spl… in dib7000m_agc_startup()
809 dib7000m_restart_agc(state); in dib7000m_agc_startup()
821 if (dib7000m_update_lna(state)) in dib7000m_agc_startup()
829 dib7000m_agc_soft_split(state); in dib7000m_agc_startup()
831 if (state->cfg.agc_control) in dib7000m_agc_startup()
832 state->cfg.agc_control(&state->demod, 0); in dib7000m_agc_startup()
837 default: in dib7000m_agc_startup()
843 static void dib7000m_set_channel(struct dib7000m_state *state, struct dtv_frontend_properties *ch, in dib7000m_set_channel() argument
848 dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz)); in dib7000m_set_channel()
852 switch (ch->transmission_mode) { in dib7000m_set_channel()
855 default: in dib7000m_set_channel()
858 switch (ch->guard_interval) { in dib7000m_set_channel()
862 default: in dib7000m_set_channel()
865 switch (ch->modulation) { in dib7000m_set_channel()
868 default: in dib7000m_set_channel()
874 default: in dib7000m_set_channel()
877 dib7000m_write_word(state, 0, value); in dib7000m_set_channel()
878 dib7000m_write_word(state, 5, (seq << 4)); in dib7000m_set_channel()
884 if (ch->hierarchy == 1) in dib7000m_set_channel()
888 switch ((ch->hierarchy == 0 || 1 == 1) ? ch->code_rate_HP : ch->code_rate_LP) { in dib7000m_set_channel()
893 default: in dib7000m_set_channel()
896 dib7000m_write_word(state, 267 + state->reg_offs, value); in dib7000m_set_channel()
901 dib7000m_write_word(state, 26, (6 << 12) | (6 << 8) | 0x80); in dib7000m_set_channel()
904 dib7000m_write_word(state, 29, (0 << 14) | (4 << 10) | (1 << 9) | (3 << 5) | (1 << 4) | (0x3)); in dib7000m_set_channel()
907 dib7000m_write_word(state, 32, (0 << 4) | 0x3); in dib7000m_set_channel()
910 dib7000m_write_word(state, 33, (0 << 4) | 0x5); in dib7000m_set_channel()
913 switch (ch->transmission_mode) { in dib7000m_set_channel()
917 default: value = 64; break; in dib7000m_set_channel()
919 switch (ch->guard_interval) { in dib7000m_set_channel()
923 default: in dib7000m_set_channel()
926 …state->div_sync_wait = (value * 3) / 2 + 32; // add 50% SFN margin + compensate for one DVSY-fifo … in dib7000m_set_channel()
928 /* deactivate the possibility of diversity reception if extended interleave - not for 7000MC */ in dib7000m_set_channel()
930 if (1 == 1 || state->revision > 0x4000) in dib7000m_set_channel()
931 state->div_force_off = 0; in dib7000m_set_channel()
933 state->div_force_off = 1; in dib7000m_set_channel()
934 dib7000m_set_diversity_in(&state->demod, state->div_state); in dib7000m_set_channel()
937 switch (ch->modulation) { in dib7000m_set_channel()
940 est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */ in dib7000m_set_channel()
942 est[3] = 0xfff8; /* P_adp_noise_ext -0.001 */ in dib7000m_set_channel()
946 est[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */ in dib7000m_set_channel()
948 est[3] = 0xfff0; /* P_adp_noise_ext -0.002 */ in dib7000m_set_channel()
950 default: in dib7000m_set_channel()
952 est[1] = 0xffae; /* P_adp_noise_cnt -0.01 */ in dib7000m_set_channel()
954 est[3] = 0xfff8; /* P_adp_noise_ext -0.002 */ in dib7000m_set_channel()
958 dib7000m_write_word(state, 214 + value + state->reg_offs, est[value]); in dib7000m_set_channel()
960 // set power-up level: autosearch in dib7000m_set_channel()
961 dib7000m_set_power_mode(state, DIB7000M_POWER_COR4_DINTLV_ICIRM_EQUAL_CFROD); in dib7000m_set_channel()
966 struct dtv_frontend_properties *ch = &demod->dtv_property_cache; in dib7000m_autosearch_start()
967 struct dib7000m_state *state = demod->demodulator_priv; in dib7000m_autosearch_start() local
981 dib7000m_set_channel(state, &schan, 7); in dib7000m_autosearch_start()
990 value = 30 * state->internal_clk * factor; in dib7000m_autosearch_start()
991 ret |= dib7000m_write_word(state, 6, (u16) ((value >> 16) & 0xffff)); // lock0 wait time in dib7000m_autosearch_start()
992 ret |= dib7000m_write_word(state, 7, (u16) (value & 0xffff)); // lock0 wait time in dib7000m_autosearch_start()
993 value = 100 * state->internal_clk * factor; in dib7000m_autosearch_start()
994 ret |= dib7000m_write_word(state, 8, (u16) ((value >> 16) & 0xffff)); // lock1 wait time in dib7000m_autosearch_start()
995 ret |= dib7000m_write_word(state, 9, (u16) (value & 0xffff)); // lock1 wait time in dib7000m_autosearch_start()
996 value = 500 * state->internal_clk * factor; in dib7000m_autosearch_start()
997 ret |= dib7000m_write_word(state, 10, (u16) ((value >> 16) & 0xffff)); // lock2 wait time in dib7000m_autosearch_start()
998 ret |= dib7000m_write_word(state, 11, (u16) (value & 0xffff)); // lock2 wait time in dib7000m_autosearch_start()
1001 value = dib7000m_read_word(state, 0); in dib7000m_autosearch_start()
1002 ret |= dib7000m_write_word(state, 0, (u16) (value | (1 << 9))); in dib7000m_autosearch_start()
1005 if (state->revision == 0x4000) in dib7000m_autosearch_start()
1006 dib7000m_write_word(state, 1793, 0); in dib7000m_autosearch_start()
1008 dib7000m_read_word(state, 537); in dib7000m_autosearch_start()
1010 ret |= dib7000m_write_word(state, 0, (u16) value); in dib7000m_autosearch_start()
1015 static int dib7000m_autosearch_irq(struct dib7000m_state *state, u16 reg) in dib7000m_autosearch_irq() argument
1017 u16 irq_pending = dib7000m_read_word(state, reg); in dib7000m_autosearch_irq()
1033 struct dib7000m_state *state = demod->demodulator_priv; in dib7000m_autosearch_is_irq() local
1034 if (state->revision == 0x4000) in dib7000m_autosearch_is_irq()
1035 return dib7000m_autosearch_irq(state, 1793); in dib7000m_autosearch_is_irq()
1037 return dib7000m_autosearch_irq(state, 537); in dib7000m_autosearch_is_irq()
1042 struct dtv_frontend_properties *ch = &demod->dtv_property_cache; in dib7000m_tune()
1043 struct dib7000m_state *state = demod->demodulator_priv; in dib7000m_tune() local
1047 // we are already tuned - just resuming from suspend in dib7000m_tune()
1048 dib7000m_set_channel(state, ch, 0); in dib7000m_tune()
1051 ret |= dib7000m_write_word(state, 898, 0x4000); in dib7000m_tune()
1052 ret |= dib7000m_write_word(state, 898, 0x0000); in dib7000m_tune()
1055 dib7000m_set_power_mode(state, DIB7000M_POWER_COR4_CRY_ESRAM_MOUT_NUD); in dib7000m_tune()
1057 …ret |= dib7000m_write_word(state, 29, (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x… in dib7000m_tune()
1059 // never achieved a lock before - wait for timfreq to update in dib7000m_tune()
1060 if (state->timf == 0) in dib7000m_tune()
1063 //dump_reg(state); in dib7000m_tune()
1066 switch (ch->transmission_mode) { in dib7000m_tune()
1069 default: in dib7000m_tune()
1072 ret |= dib7000m_write_word(state, 26, value); in dib7000m_tune()
1076 switch (ch->transmission_mode) { in dib7000m_tune()
1079 default: in dib7000m_tune()
1082 ret |= dib7000m_write_word(state, 32, value); in dib7000m_tune()
1086 switch (ch->transmission_mode) { in dib7000m_tune()
1089 default: in dib7000m_tune()
1092 ret |= dib7000m_write_word(state, 33, value); in dib7000m_tune()
1094 // we achieved a lock - it's time to update the timf freq in dib7000m_tune()
1095 if ((dib7000m_read_word(state, 535) >> 6) & 0x1) in dib7000m_tune()
1096 dib7000m_update_timf(state); in dib7000m_tune()
1098 dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(ch->bandwidth_hz)); in dib7000m_tune()
1104 struct dib7000m_state *state = demod->demodulator_priv; in dib7000m_wakeup() local
1106 dib7000m_set_power_mode(state, DIB7000M_POWER_ALL); in dib7000m_wakeup()
1108 if (dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0) in dib7000m_wakeup()
1116 struct dib7000m_state *st = demod->demodulator_priv; in dib7000m_sleep()
1123 static int dib7000m_identify(struct dib7000m_state *state) in dib7000m_identify() argument
1127 if ((value = dib7000m_read_word(state, 896)) != 0x01b3) { in dib7000m_identify()
1129 return -EREMOTEIO; in dib7000m_identify()
1132 state->revision = dib7000m_read_word(state, 897); in dib7000m_identify()
1133 if (state->revision != 0x4000 && in dib7000m_identify()
1134 state->revision != 0x4001 && in dib7000m_identify()
1135 state->revision != 0x4002 && in dib7000m_identify()
1136 state->revision != 0x4003) { in dib7000m_identify()
1138 return -EREMOTEIO; in dib7000m_identify()
1142 if (state->revision == 0x4000 && dib7000m_read_word(state, 769) == 0x4000) { in dib7000m_identify()
1144 return -EREMOTEIO; in dib7000m_identify()
1147 switch (state->revision) { in dib7000m_identify()
1149 case 0x4001: state->reg_offs = 1; dprintk("found DiB7000HC\n"); break; in dib7000m_identify()
1150 case 0x4002: state->reg_offs = 1; dprintk("found DiB7000MC\n"); break; in dib7000m_identify()
1151 case 0x4003: state->reg_offs = 1; dprintk("found DiB9000\n"); break; in dib7000m_identify()
1161 struct dib7000m_state *state = fe->demodulator_priv; in dib7000m_get_frontend() local
1162 u16 tps = dib7000m_read_word(state,480); in dib7000m_get_frontend()
1164 fep->inversion = INVERSION_AUTO; in dib7000m_get_frontend()
1166 fep->bandwidth_hz = BANDWIDTH_TO_HZ(state->current_bandwidth); in dib7000m_get_frontend()
1169 case 0: fep->transmission_mode = TRANSMISSION_MODE_2K; break; in dib7000m_get_frontend()
1170 case 1: fep->transmission_mode = TRANSMISSION_MODE_8K; break; in dib7000m_get_frontend()
1171 /* case 2: fep->transmission_mode = TRANSMISSION_MODE_4K; break; */ in dib7000m_get_frontend()
1175 case 0: fep->guard_interval = GUARD_INTERVAL_1_32; break; in dib7000m_get_frontend()
1176 case 1: fep->guard_interval = GUARD_INTERVAL_1_16; break; in dib7000m_get_frontend()
1177 case 2: fep->guard_interval = GUARD_INTERVAL_1_8; break; in dib7000m_get_frontend()
1178 case 3: fep->guard_interval = GUARD_INTERVAL_1_4; break; in dib7000m_get_frontend()
1182 case 0: fep->modulation = QPSK; break; in dib7000m_get_frontend()
1183 case 1: fep->modulation = QAM_16; break; in dib7000m_get_frontend()
1185 default: fep->modulation = QAM_64; break; in dib7000m_get_frontend()
1191 fep->hierarchy = HIERARCHY_NONE; in dib7000m_get_frontend()
1193 case 1: fep->code_rate_HP = FEC_1_2; break; in dib7000m_get_frontend()
1194 case 2: fep->code_rate_HP = FEC_2_3; break; in dib7000m_get_frontend()
1195 case 3: fep->code_rate_HP = FEC_3_4; break; in dib7000m_get_frontend()
1196 case 5: fep->code_rate_HP = FEC_5_6; break; in dib7000m_get_frontend()
1198 default: fep->code_rate_HP = FEC_7_8; break; in dib7000m_get_frontend()
1203 case 1: fep->code_rate_LP = FEC_1_2; break; in dib7000m_get_frontend()
1204 case 2: fep->code_rate_LP = FEC_2_3; break; in dib7000m_get_frontend()
1205 case 3: fep->code_rate_LP = FEC_3_4; break; in dib7000m_get_frontend()
1206 case 5: fep->code_rate_LP = FEC_5_6; break; in dib7000m_get_frontend()
1208 default: fep->code_rate_LP = FEC_7_8; break; in dib7000m_get_frontend()
1211 /* native interleaver: (dib7000m_read_word(state, 481) >> 5) & 0x1 */ in dib7000m_get_frontend()
1218 struct dtv_frontend_properties *fep = &fe->dtv_property_cache; in dib7000m_set_frontend()
1219 struct dib7000m_state *state = fe->demodulator_priv; in dib7000m_set_frontend() local
1222 dib7000m_set_output_mode(state, OUTMODE_HIGH_Z); in dib7000m_set_frontend()
1224 dib7000m_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->bandwidth_hz)); in dib7000m_set_frontend()
1226 if (fe->ops.tuner_ops.set_params) in dib7000m_set_frontend()
1227 fe->ops.tuner_ops.set_params(fe); in dib7000m_set_frontend()
1230 state->agc_state = 0; in dib7000m_set_frontend()
1233 if (time != -1) in dib7000m_set_frontend()
1235 } while (time != -1); in dib7000m_set_frontend()
1237 if (fep->transmission_mode == TRANSMISSION_MODE_AUTO || in dib7000m_set_frontend()
1238 fep->guard_interval == GUARD_INTERVAL_AUTO || in dib7000m_set_frontend()
1239 fep->modulation == QAM_AUTO || in dib7000m_set_frontend()
1240 fep->code_rate_HP == FEC_AUTO) { in dib7000m_set_frontend()
1247 } while (found == 0 && i--); in dib7000m_set_frontend()
1259 dib7000m_set_output_mode(state, OUTMODE_MPEG2_FIFO); in dib7000m_set_frontend()
1265 struct dib7000m_state *state = fe->demodulator_priv; in dib7000m_read_status() local
1266 u16 lock = dib7000m_read_word(state, 535); in dib7000m_read_status()
1286 struct dib7000m_state *state = fe->demodulator_priv; in dib7000m_read_ber() local
1287 *ber = (dib7000m_read_word(state, 526) << 16) | dib7000m_read_word(state, 527); in dib7000m_read_ber()
1293 struct dib7000m_state *state = fe->demodulator_priv; in dib7000m_read_unc_blocks() local
1294 *unc = dib7000m_read_word(state, 534); in dib7000m_read_unc_blocks()
1300 struct dib7000m_state *state = fe->demodulator_priv; in dib7000m_read_signal_strength() local
1301 u16 val = dib7000m_read_word(state, 390); in dib7000m_read_signal_strength()
1302 *strength = 65535 - val; in dib7000m_read_signal_strength()
1314 tune->min_delay_ms = 1000; in dib7000m_fe_get_tune_settings()
1320 struct dib7000m_state *st = demod->demodulator_priv; in dib7000m_release()
1321 dibx000_exit_i2c_master(&st->i2c_master); in dib7000m_release()
1327 struct dib7000m_state *st = demod->demodulator_priv; in dib7000m_get_i2c_master()
1328 return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating); in dib7000m_get_i2c_master()
1334 struct dib7000m_state *state = fe->demodulator_priv; in dib7000m_pid_filter_ctrl() local
1335 u16 val = dib7000m_read_word(state, 294 + state->reg_offs) & 0xffef; in dib7000m_pid_filter_ctrl()
1338 return dib7000m_write_word(state, 294 + state->reg_offs, val); in dib7000m_pid_filter_ctrl()
1344 struct dib7000m_state *state = fe->demodulator_priv; in dib7000m_pid_filter() local
1346 return dib7000m_write_word(state, 300 + state->reg_offs + id, in dib7000m_pid_filter()
1360 for (k = no_of_demods-1; k >= 0; k--) {
1370 return -EIO;
1374 /* start diversity to pull_down div_str - just for i2c-enumeration */
1377 dib7000m_write_word(&st, 1796, 0x0); // select DVB-T output
1392 /* deactivate div - it was just for i2c-enumeration */
1410 memcpy(&st->cfg, cfg, sizeof(struct dib7000m_config)); in dib7000m_attach()
1411 st->i2c_adap = i2c_adap; in dib7000m_attach()
1412 st->i2c_addr = i2c_addr; in dib7000m_attach()
1414 demod = &st->demod; in dib7000m_attach()
1415 demod->demodulator_priv = st; in dib7000m_attach()
1416 memcpy(&st->demod.ops, &dib7000m_ops, sizeof(struct dvb_frontend_ops)); in dib7000m_attach()
1417 mutex_init(&st->i2c_buffer_lock); in dib7000m_attach()
1419 st->timf_default = cfg->bw->timf; in dib7000m_attach()
1424 if (st->revision == 0x4000) in dib7000m_attach()
1425 dibx000_init_i2c_master(&st->i2c_master, DIB7000, st->i2c_adap, st->i2c_addr); in dib7000m_attach()
1427 dibx000_init_i2c_master(&st->i2c_master, DIB7000MC, st->i2c_adap, st->i2c_addr); in dib7000m_attach()