Lines Matching +full:default +full:- +full:state
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for DiBcom DiB3000MC/P-demodulator.
5 * Copyright (C) 2004-7 DiBcom (http://www.dibcom.fr/)
6 * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@posteo.de)
23 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
27 MODULE_PARM_DESC(buggy_sfn_workaround, "Enable work-around for buggy SFNs (default: 0)");
53 static u16 dib3000mc_read_word(struct dib3000mc_state *state, u16 reg) in dib3000mc_read_word() argument
56 { .addr = state->i2c_addr >> 1, .flags = 0, .len = 2 }, in dib3000mc_read_word()
57 { .addr = state->i2c_addr >> 1, .flags = I2C_M_RD, .len = 2 }, in dib3000mc_read_word()
74 if (i2c_transfer(state->i2c_adap, msg, 2) != 2) in dib3000mc_read_word()
83 static int dib3000mc_write_word(struct dib3000mc_state *state, u16 reg, u16 val) in dib3000mc_write_word() argument
86 .addr = state->i2c_addr >> 1, .flags = 0, .len = 4 in dib3000mc_write_word()
93 return -ENOMEM; in dib3000mc_write_word()
102 rc = i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0; in dib3000mc_write_word()
108 static int dib3000mc_identify(struct dib3000mc_state *state) in dib3000mc_identify() argument
111 if ((value = dib3000mc_read_word(state, 1025)) != 0x01b3) { in dib3000mc_identify()
112 dprintk("-E- DiB3000MC/P: wrong Vendor ID (read=0x%x)\n",value); in dib3000mc_identify()
113 return -EREMOTEIO; in dib3000mc_identify()
116 value = dib3000mc_read_word(state, 1026); in dib3000mc_identify()
118 dprintk("-E- DiB3000MC/P: wrong Device ID (%x)\n",value); in dib3000mc_identify()
119 return -EREMOTEIO; in dib3000mc_identify()
121 state->dev_id = value; in dib3000mc_identify()
123 dprintk("-I- found DiB3000MC/P: %x\n",state->dev_id); in dib3000mc_identify()
128 static int dib3000mc_set_timing(struct dib3000mc_state *state, s16 nfft, u32 bw, u8 update_offset) in dib3000mc_set_timing() argument
132 if (state->timf == 0) { in dib3000mc_set_timing()
133 timf = 1384402; // default value for 8MHz in dib3000mc_set_timing()
137 timf = state->timf; in dib3000mc_set_timing()
142 s16 tim_offs = dib3000mc_read_word(state, 416); in dib3000mc_set_timing()
145 tim_offs -= 0x4000; in dib3000mc_set_timing()
151 state->timf = timf / (bw / 1000); in dib3000mc_set_timing()
156 dib3000mc_write_word(state, 23, (u16) (timf >> 16)); in dib3000mc_set_timing()
157 dib3000mc_write_word(state, 24, (u16) (timf ) & 0xffff); in dib3000mc_set_timing()
162 static int dib3000mc_setup_pwm_state(struct dib3000mc_state *state) in dib3000mc_setup_pwm_state() argument
164 u16 reg_51, reg_52 = state->cfg->agc->setup & 0xfefb; in dib3000mc_setup_pwm_state()
165 if (state->cfg->pwm3_inversion) { in dib3000mc_setup_pwm_state()
172 dib3000mc_write_word(state, 51, reg_51); in dib3000mc_setup_pwm_state()
173 dib3000mc_write_word(state, 52, reg_52); in dib3000mc_setup_pwm_state()
175 if (state->cfg->use_pwm3) in dib3000mc_setup_pwm_state()
176 dib3000mc_write_word(state, 245, (1 << 3) | (1 << 0)); in dib3000mc_setup_pwm_state()
178 dib3000mc_write_word(state, 245, 0); in dib3000mc_setup_pwm_state()
180 dib3000mc_write_word(state, 1040, 0x3); in dib3000mc_setup_pwm_state()
184 static int dib3000mc_set_output_mode(struct dib3000mc_state *state, int mode) in dib3000mc_set_output_mode() argument
191 u16 smo_reg = dib3000mc_read_word(state, 206) & 0x0010; /* keep the pid_parse bit */ in dib3000mc_set_output_mode()
193 dprintk("-I- Setting output mode for demod %p to %d\n", in dib3000mc_set_output_mode()
194 &state->demod, mode); in dib3000mc_set_output_mode()
227 default: in dib3000mc_set_output_mode()
228 dprintk("Unhandled output_mode passed to be set for demod %p\n",&state->demod); in dib3000mc_set_output_mode()
233 if ((state->cfg->output_mpeg2_in_188_bytes)) in dib3000mc_set_output_mode()
236 outreg = dib3000mc_read_word(state, 244) & 0x07FF; in dib3000mc_set_output_mode()
238 ret |= dib3000mc_write_word(state, 244, outreg); in dib3000mc_set_output_mode()
239 ret |= dib3000mc_write_word(state, 206, smo_reg); /*smo_ mode*/ in dib3000mc_set_output_mode()
240 ret |= dib3000mc_write_word(state, 207, fifo_threshold); /* synchronous fread */ in dib3000mc_set_output_mode()
241 ret |= dib3000mc_write_word(state, 1040, elecout); /* P_out_cfg */ in dib3000mc_set_output_mode()
245 static int dib3000mc_set_bandwidth(struct dib3000mc_state *state, u32 bw) in dib3000mc_set_bandwidth() argument
273 default: return -EINVAL; in dib3000mc_set_bandwidth()
277 dib3000mc_write_word(state, reg, bw_cfg[reg - 6]); in dib3000mc_set_bandwidth()
278 dib3000mc_write_word(state, 12, 0x0000); in dib3000mc_set_bandwidth()
279 dib3000mc_write_word(state, 13, 0x03e8); in dib3000mc_set_bandwidth()
280 dib3000mc_write_word(state, 14, 0x0000); in dib3000mc_set_bandwidth()
281 dib3000mc_write_word(state, 15, 0x03f2); in dib3000mc_set_bandwidth()
282 dib3000mc_write_word(state, 16, 0x0001); in dib3000mc_set_bandwidth()
283 dib3000mc_write_word(state, 17, 0xb0d0); in dib3000mc_set_bandwidth()
285 dib3000mc_write_word(state, 18, 0x0393); in dib3000mc_set_bandwidth()
286 dib3000mc_write_word(state, 19, 0x8700); in dib3000mc_set_bandwidth()
289 dib3000mc_write_word(state, reg, imp_bw_cfg[reg - 55]); in dib3000mc_set_bandwidth()
292 dib3000mc_set_timing(state, TRANSMISSION_MODE_2K, bw, 0); in dib3000mc_set_bandwidth()
305 static void dib3000mc_set_impulse_noise(struct dib3000mc_state *state, u8 mode, s16 nfft) in dib3000mc_set_impulse_noise() argument
309 dib3000mc_write_word(state, i, impulse_noise_val[i-58]); in dib3000mc_set_impulse_noise()
312 dib3000mc_write_word(state, 58, 0x3b); in dib3000mc_set_impulse_noise()
313 dib3000mc_write_word(state, 84, 0x00); in dib3000mc_set_impulse_noise()
314 dib3000mc_write_word(state, 85, 0x8200); in dib3000mc_set_impulse_noise()
317 dib3000mc_write_word(state, 34, 0x1294); in dib3000mc_set_impulse_noise()
318 dib3000mc_write_word(state, 35, 0x1ff8); in dib3000mc_set_impulse_noise()
320 dib3000mc_write_word(state, 55, dib3000mc_read_word(state, 55) | (1 << 10)); in dib3000mc_set_impulse_noise()
325 struct dib3000mc_state *state = demod->demodulator_priv; in dib3000mc_init() local
326 struct dibx000_agc_config *agc = state->cfg->agc; in dib3000mc_init()
329 dib3000mc_write_word(state, 1027, 0x8000); in dib3000mc_init()
330 dib3000mc_write_word(state, 1027, 0x0000); in dib3000mc_init()
333 dib3000mc_write_word(state, 140, 0x0000); in dib3000mc_init()
334 dib3000mc_write_word(state, 1031, 0); in dib3000mc_init()
336 if (state->cfg->mobile_mode) { in dib3000mc_init()
337 dib3000mc_write_word(state, 139, 0x0000); in dib3000mc_init()
338 dib3000mc_write_word(state, 141, 0x0000); in dib3000mc_init()
339 dib3000mc_write_word(state, 175, 0x0002); in dib3000mc_init()
340 dib3000mc_write_word(state, 1032, 0x0000); in dib3000mc_init()
342 dib3000mc_write_word(state, 139, 0x0001); in dib3000mc_init()
343 dib3000mc_write_word(state, 141, 0x0000); in dib3000mc_init()
344 dib3000mc_write_word(state, 175, 0x0000); in dib3000mc_init()
345 dib3000mc_write_word(state, 1032, 0x012C); in dib3000mc_init()
347 dib3000mc_write_word(state, 1033, 0x0000); in dib3000mc_init()
350 dib3000mc_write_word(state, 1037, 0x3130); in dib3000mc_init()
355 dib3000mc_write_word(state, 33, (5 << 0)); in dib3000mc_init()
356 dib3000mc_write_word(state, 88, (1 << 10) | (0x10 << 0)); in dib3000mc_init()
360 dib3000mc_write_word(state, 99, (1 << 9) | (0x20 << 0)); in dib3000mc_init()
362 if (state->cfg->phase_noise_mode == 0) in dib3000mc_init()
363 dib3000mc_write_word(state, 111, 0x00); in dib3000mc_init()
365 dib3000mc_write_word(state, 111, 0x02); in dib3000mc_init()
368 dib3000mc_write_word(state, 50, 0x8000); in dib3000mc_init()
371 dib3000mc_setup_pwm_state(state); in dib3000mc_init()
374 dib3000mc_write_word(state, 53, 0x87); in dib3000mc_init()
376 dib3000mc_write_word(state, 54, 0x87); in dib3000mc_init()
379 dib3000mc_write_word(state, 36, state->cfg->max_time); in dib3000mc_init()
380 …dib3000mc_write_word(state, 37, (state->cfg->agc_command1 << 13) | (state->cfg->agc_command2 << 12… in dib3000mc_init()
381 dib3000mc_write_word(state, 38, state->cfg->pwm3_value); in dib3000mc_init()
382 dib3000mc_write_word(state, 39, state->cfg->ln_adc_level); in dib3000mc_init()
385 dib3000mc_write_word(state, 40, 0x0179); in dib3000mc_init()
386 dib3000mc_write_word(state, 41, 0x03f0); in dib3000mc_init()
388 dib3000mc_write_word(state, 42, agc->agc1_max); in dib3000mc_init()
389 dib3000mc_write_word(state, 43, agc->agc1_min); in dib3000mc_init()
390 dib3000mc_write_word(state, 44, agc->agc2_max); in dib3000mc_init()
391 dib3000mc_write_word(state, 45, agc->agc2_min); in dib3000mc_init()
392 dib3000mc_write_word(state, 46, (agc->agc1_pt1 << 8) | agc->agc1_pt2); in dib3000mc_init()
393 dib3000mc_write_word(state, 47, (agc->agc1_slope1 << 8) | agc->agc1_slope2); in dib3000mc_init()
394 dib3000mc_write_word(state, 48, (agc->agc2_pt1 << 8) | agc->agc2_pt2); in dib3000mc_init()
395 dib3000mc_write_word(state, 49, (agc->agc2_slope1 << 8) | agc->agc2_slope2); in dib3000mc_init()
399 dib3000mc_write_word(state, 110, 3277); in dib3000mc_init()
401 dib3000mc_write_word(state, 26, 0x6680); in dib3000mc_init()
403 dib3000mc_write_word(state, 1, 4); in dib3000mc_init()
405 dib3000mc_write_word(state, 2, 4); in dib3000mc_init()
407 dib3000mc_write_word(state, 3, 0x1000); in dib3000mc_init()
409 dib3000mc_write_word(state, 5, 1); in dib3000mc_init()
411 dib3000mc_set_bandwidth(state, 8000); in dib3000mc_init()
414 dib3000mc_write_word(state, 4, 0x814); in dib3000mc_init()
416 dib3000mc_write_word(state, 21, (1 << 9) | 0x164); in dib3000mc_init()
417 dib3000mc_write_word(state, 22, 0x463d); in dib3000mc_init()
421 dib3000mc_write_word(state, 120, 0x200f); in dib3000mc_init()
423 dib3000mc_write_word(state, 134, 0); in dib3000mc_init()
426 dib3000mc_write_word(state, 195, 0x10); in dib3000mc_init()
429 dib3000mc_write_word(state, 180, 0x2FF0); in dib3000mc_init()
432 dib3000mc_set_impulse_noise(state, 0, TRANSMISSION_MODE_8K); in dib3000mc_init()
434 // output mode set-up in dib3000mc_init()
435 dib3000mc_set_output_mode(state, OUTMODE_HIGH_Z); in dib3000mc_init()
437 /* close the i2c-gate */ in dib3000mc_init()
438 dib3000mc_write_word(state, 769, (1 << 7) ); in dib3000mc_init()
445 struct dib3000mc_state *state = demod->demodulator_priv; in dib3000mc_sleep() local
447 dib3000mc_write_word(state, 1031, 0xFFFF); in dib3000mc_sleep()
448 dib3000mc_write_word(state, 1032, 0xFFFF); in dib3000mc_sleep()
449 dib3000mc_write_word(state, 1033, 0xFFF0); in dib3000mc_sleep()
454 static void dib3000mc_set_adp_cfg(struct dib3000mc_state *state, s16 qam) in dib3000mc_set_adp_cfg() argument
469 dib3000mc_write_word(state, reg, cfg[reg - 129]); in dib3000mc_set_adp_cfg()
472 static void dib3000mc_set_channel_cfg(struct dib3000mc_state *state, in dib3000mc_set_channel_cfg() argument
476 u32 bw = BANDWIDTH_TO_KHZ(ch->bandwidth_hz); in dib3000mc_set_channel_cfg()
478 dib3000mc_set_bandwidth(state, bw); in dib3000mc_set_channel_cfg()
479 dib3000mc_set_timing(state, ch->transmission_mode, bw, 0); in dib3000mc_set_channel_cfg()
482 dib3000mc_write_word(state, 100, (16 << 6) + 9); in dib3000mc_set_channel_cfg()
485 dib3000mc_write_word(state, 100, (11 << 6) + 6); in dib3000mc_set_channel_cfg()
487 dib3000mc_write_word(state, 100, (16 << 6) + 9); in dib3000mc_set_channel_cfg()
490 dib3000mc_write_word(state, 1027, 0x0800); in dib3000mc_set_channel_cfg()
491 dib3000mc_write_word(state, 1027, 0x0000); in dib3000mc_set_channel_cfg()
493 //Default cfg isi offset adp in dib3000mc_set_channel_cfg()
494 dib3000mc_write_word(state, 26, 0x6680); in dib3000mc_set_channel_cfg()
495 dib3000mc_write_word(state, 29, 0x1273); in dib3000mc_set_channel_cfg()
496 dib3000mc_write_word(state, 33, 5); in dib3000mc_set_channel_cfg()
497 dib3000mc_set_adp_cfg(state, QAM_16); in dib3000mc_set_channel_cfg()
498 dib3000mc_write_word(state, 133, 15564); in dib3000mc_set_channel_cfg()
500 dib3000mc_write_word(state, 12 , 0x0); in dib3000mc_set_channel_cfg()
501 dib3000mc_write_word(state, 13 , 0x3e8); in dib3000mc_set_channel_cfg()
502 dib3000mc_write_word(state, 14 , 0x0); in dib3000mc_set_channel_cfg()
503 dib3000mc_write_word(state, 15 , 0x3f2); in dib3000mc_set_channel_cfg()
505 dib3000mc_write_word(state, 93,0); in dib3000mc_set_channel_cfg()
506 dib3000mc_write_word(state, 94,0); in dib3000mc_set_channel_cfg()
507 dib3000mc_write_word(state, 95,0); in dib3000mc_set_channel_cfg()
508 dib3000mc_write_word(state, 96,0); in dib3000mc_set_channel_cfg()
509 dib3000mc_write_word(state, 97,0); in dib3000mc_set_channel_cfg()
510 dib3000mc_write_word(state, 98,0); in dib3000mc_set_channel_cfg()
512 dib3000mc_set_impulse_noise(state, 0, ch->transmission_mode); in dib3000mc_set_channel_cfg()
515 switch (ch->transmission_mode) { in dib3000mc_set_channel_cfg()
517 default: in dib3000mc_set_channel_cfg()
520 switch (ch->guard_interval) { in dib3000mc_set_channel_cfg()
524 default: in dib3000mc_set_channel_cfg()
527 switch (ch->modulation) { in dib3000mc_set_channel_cfg()
530 default: in dib3000mc_set_channel_cfg()
536 default: in dib3000mc_set_channel_cfg()
539 dib3000mc_write_word(state, 0, value); in dib3000mc_set_channel_cfg()
540 dib3000mc_write_word(state, 5, (1 << 8) | ((seq & 0xf) << 4)); in dib3000mc_set_channel_cfg()
543 if (ch->hierarchy == 1) in dib3000mc_set_channel_cfg()
547 switch ((ch->hierarchy == 0 || 1 == 1) ? ch->code_rate_HP : ch->code_rate_LP) { in dib3000mc_set_channel_cfg()
552 default: in dib3000mc_set_channel_cfg()
555 dib3000mc_write_word(state, 181, value); in dib3000mc_set_channel_cfg()
558 switch (ch->transmission_mode) { in dib3000mc_set_channel_cfg()
561 default: value = 64; break; in dib3000mc_set_channel_cfg()
563 switch (ch->guard_interval) { in dib3000mc_set_channel_cfg()
567 default: in dib3000mc_set_channel_cfg()
571 value |= dib3000mc_read_word(state, 180) & 0x000f; in dib3000mc_set_channel_cfg()
572 dib3000mc_write_word(state, 180, value); in dib3000mc_set_channel_cfg()
575 value = dib3000mc_read_word(state, 0); in dib3000mc_set_channel_cfg()
576 dib3000mc_write_word(state, 0, value | (1 << 9)); in dib3000mc_set_channel_cfg()
577 dib3000mc_write_word(state, 0, value); in dib3000mc_set_channel_cfg()
581 dib3000mc_set_impulse_noise(state, state->cfg->impulse_noise_mode, ch->transmission_mode); in dib3000mc_set_channel_cfg()
586 struct dtv_frontend_properties *chan = &demod->dtv_property_cache; in dib3000mc_autosearch_start()
587 struct dib3000mc_state *state = demod->demodulator_priv; in dib3000mc_autosearch_start() local
604 dib3000mc_set_channel_cfg(state, &schan, 11); in dib3000mc_autosearch_start()
606 reg = dib3000mc_read_word(state, 0); in dib3000mc_autosearch_start()
607 dib3000mc_write_word(state, 0, reg | (1 << 8)); in dib3000mc_autosearch_start()
608 dib3000mc_read_word(state, 511); in dib3000mc_autosearch_start()
609 dib3000mc_write_word(state, 0, reg); in dib3000mc_autosearch_start()
616 struct dib3000mc_state *state = demod->demodulator_priv; in dib3000mc_autosearch_is_irq() local
617 u16 irq_pending = dib3000mc_read_word(state, 511); in dib3000mc_autosearch_is_irq()
630 struct dtv_frontend_properties *ch = &demod->dtv_property_cache; in dib3000mc_tune()
631 struct dib3000mc_state *state = demod->demodulator_priv; in dib3000mc_tune() local
634 dib3000mc_set_channel_cfg(state, ch, 0); in dib3000mc_tune()
637 if (state->sfn_workaround_active) { in dib3000mc_tune()
639 dib3000mc_write_word(state, 29, 0x1273); in dib3000mc_tune()
640 dib3000mc_write_word(state, 108, 0x4000); // P_pha3_force_pha_shift in dib3000mc_tune()
642 dib3000mc_write_word(state, 29, 0x1073); in dib3000mc_tune()
643 dib3000mc_write_word(state, 108, 0x0000); // P_pha3_force_pha_shift in dib3000mc_tune()
646 dib3000mc_set_adp_cfg(state, (u8)ch->modulation); in dib3000mc_tune()
647 if (ch->transmission_mode == TRANSMISSION_MODE_8K) { in dib3000mc_tune()
648 dib3000mc_write_word(state, 26, 38528); in dib3000mc_tune()
649 dib3000mc_write_word(state, 33, 8); in dib3000mc_tune()
651 dib3000mc_write_word(state, 26, 30336); in dib3000mc_tune()
652 dib3000mc_write_word(state, 33, 6); in dib3000mc_tune()
655 if (dib3000mc_read_word(state, 509) & 0x80) in dib3000mc_tune()
656 dib3000mc_set_timing(state, ch->transmission_mode, in dib3000mc_tune()
657 BANDWIDTH_TO_KHZ(ch->bandwidth_hz), 1); in dib3000mc_tune()
664 struct dib3000mc_state *st = demod->demodulator_priv; in dib3000mc_get_tuner_i2c_master()
665 return dibx000_get_i2c_adapter(&st->i2c_master, DIBX000_I2C_INTERFACE_TUNER, gating); in dib3000mc_get_tuner_i2c_master()
673 struct dib3000mc_state *state = fe->demodulator_priv; in dib3000mc_get_frontend() local
674 u16 tps = dib3000mc_read_word(state,458); in dib3000mc_get_frontend()
676 fep->inversion = INVERSION_AUTO; in dib3000mc_get_frontend()
678 fep->bandwidth_hz = state->current_bandwidth; in dib3000mc_get_frontend()
681 case 0: fep->transmission_mode = TRANSMISSION_MODE_2K; break; in dib3000mc_get_frontend()
682 case 1: fep->transmission_mode = TRANSMISSION_MODE_8K; break; in dib3000mc_get_frontend()
686 case 0: fep->guard_interval = GUARD_INTERVAL_1_32; break; in dib3000mc_get_frontend()
687 case 1: fep->guard_interval = GUARD_INTERVAL_1_16; break; in dib3000mc_get_frontend()
688 case 2: fep->guard_interval = GUARD_INTERVAL_1_8; break; in dib3000mc_get_frontend()
689 case 3: fep->guard_interval = GUARD_INTERVAL_1_4; break; in dib3000mc_get_frontend()
693 case 0: fep->modulation = QPSK; break; in dib3000mc_get_frontend()
694 case 1: fep->modulation = QAM_16; break; in dib3000mc_get_frontend()
696 default: fep->modulation = QAM_64; break; in dib3000mc_get_frontend()
702 fep->hierarchy = HIERARCHY_NONE; in dib3000mc_get_frontend()
704 case 1: fep->code_rate_HP = FEC_1_2; break; in dib3000mc_get_frontend()
705 case 2: fep->code_rate_HP = FEC_2_3; break; in dib3000mc_get_frontend()
706 case 3: fep->code_rate_HP = FEC_3_4; break; in dib3000mc_get_frontend()
707 case 5: fep->code_rate_HP = FEC_5_6; break; in dib3000mc_get_frontend()
709 default: fep->code_rate_HP = FEC_7_8; break; in dib3000mc_get_frontend()
714 case 1: fep->code_rate_LP = FEC_1_2; break; in dib3000mc_get_frontend()
715 case 2: fep->code_rate_LP = FEC_2_3; break; in dib3000mc_get_frontend()
716 case 3: fep->code_rate_LP = FEC_3_4; break; in dib3000mc_get_frontend()
717 case 5: fep->code_rate_LP = FEC_5_6; break; in dib3000mc_get_frontend()
719 default: fep->code_rate_LP = FEC_7_8; break; in dib3000mc_get_frontend()
727 struct dtv_frontend_properties *fep = &fe->dtv_property_cache; in dib3000mc_set_frontend()
728 struct dib3000mc_state *state = fe->demodulator_priv; in dib3000mc_set_frontend() local
731 dib3000mc_set_output_mode(state, OUTMODE_HIGH_Z); in dib3000mc_set_frontend()
733 state->current_bandwidth = fep->bandwidth_hz; in dib3000mc_set_frontend()
734 dib3000mc_set_bandwidth(state, BANDWIDTH_TO_KHZ(fep->bandwidth_hz)); in dib3000mc_set_frontend()
737 state->sfn_workaround_active = buggy_sfn_workaround; in dib3000mc_set_frontend()
739 if (fe->ops.tuner_ops.set_params) { in dib3000mc_set_frontend()
740 fe->ops.tuner_ops.set_params(fe); in dib3000mc_set_frontend()
744 if (fep->transmission_mode == TRANSMISSION_MODE_AUTO || in dib3000mc_set_frontend()
745 fep->guard_interval == GUARD_INTERVAL_AUTO || in dib3000mc_set_frontend()
746 fep->modulation == QAM_AUTO || in dib3000mc_set_frontend()
747 fep->code_rate_HP == FEC_AUTO) { in dib3000mc_set_frontend()
754 } while (found == 0 && i--); in dib3000mc_set_frontend()
766 dib3000mc_set_output_mode(state, OUTMODE_MPEG2_FIFO); in dib3000mc_set_frontend()
772 struct dib3000mc_state *state = fe->demodulator_priv; in dib3000mc_read_status() local
773 u16 lock = dib3000mc_read_word(state, 509); in dib3000mc_read_status()
793 struct dib3000mc_state *state = fe->demodulator_priv; in dib3000mc_read_ber() local
794 *ber = (dib3000mc_read_word(state, 500) << 16) | dib3000mc_read_word(state, 501); in dib3000mc_read_ber()
800 struct dib3000mc_state *state = fe->demodulator_priv; in dib3000mc_read_unc_blocks() local
801 *unc = dib3000mc_read_word(state, 508); in dib3000mc_read_unc_blocks()
807 struct dib3000mc_state *state = fe->demodulator_priv; in dib3000mc_read_signal_strength() local
808 u16 val = dib3000mc_read_word(state, 392); in dib3000mc_read_signal_strength()
809 *strength = 65535 - val; in dib3000mc_read_signal_strength()
821 tune->min_delay_ms = 1000; in dib3000mc_fe_get_tune_settings()
827 struct dib3000mc_state *state = fe->demodulator_priv; in dib3000mc_release() local
828 dibx000_exit_i2c_master(&state->i2c_master); in dib3000mc_release()
829 kfree(state); in dib3000mc_release()
834 struct dib3000mc_state *state = fe->demodulator_priv; in dib3000mc_pid_control() local
835 dib3000mc_write_word(state, 212 + index, onoff ? (1 << 13) | pid : 0); in dib3000mc_pid_control()
842 struct dib3000mc_state *state = fe->demodulator_priv; in dib3000mc_pid_parse() local
843 u16 tmp = dib3000mc_read_word(state, 206) & ~(1 << 4); in dib3000mc_pid_parse()
845 return dib3000mc_write_word(state, 206, tmp); in dib3000mc_pid_parse()
851 struct dib3000mc_state *state = fe->demodulator_priv; in dib3000mc_set_config() local
852 state->cfg = cfg; in dib3000mc_set_config()
866 return -ENOMEM; in dib3000mc_i2c_enumeration()
868 dmcst->i2c_adap = i2c; in dib3000mc_i2c_enumeration()
870 for (k = no_of_demods-1; k >= 0; k--) { in dib3000mc_i2c_enumeration()
871 dmcst->cfg = &cfg[k]; in dib3000mc_i2c_enumeration()
875 dmcst->i2c_addr = new_addr; in dib3000mc_i2c_enumeration()
877 dmcst->i2c_addr = default_addr; in dib3000mc_i2c_enumeration()
879 dprintk("-E- DiB3000P/MC #%d: not identified\n", k); in dib3000mc_i2c_enumeration()
881 return -ENODEV; in dib3000mc_i2c_enumeration()
889 dmcst->i2c_addr = new_addr; in dib3000mc_i2c_enumeration()
893 dmcst->cfg = &cfg[k]; in dib3000mc_i2c_enumeration()
894 dmcst->i2c_addr = DIB3000MC_I2C_ADDRESS[k]; in dib3000mc_i2c_enumeration()
896 dib3000mc_write_word(dmcst, 1024, dmcst->i2c_addr << 3); in dib3000mc_i2c_enumeration()
917 st->cfg = cfg; in dib3000mc_attach()
918 st->i2c_adap = i2c_adap; in dib3000mc_attach()
919 st->i2c_addr = i2c_addr; in dib3000mc_attach()
921 demod = &st->demod; in dib3000mc_attach()
922 demod->demodulator_priv = st; in dib3000mc_attach()
923 memcpy(&st->demod.ops, &dib3000mc_ops, sizeof(struct dvb_frontend_ops)); in dib3000mc_attach()
928 dibx000_init_i2c_master(&st->i2c_master, DIB3000MC, st->i2c_adap, st->i2c_addr); in dib3000mc_attach()