Lines Matching +full:0 +full:x00000
28 return 0; in flexcop_sram_init()
55 return 0; in flexcop_sram_set_dest()
75 #if 0
81 for (i = 0; i < len; i++) {
82 command = bank | addr | 0x04000000 | (*buf << 0x10);
86 while (((read_reg_dw(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {
91 if (retries == 0)
94 write_reg_dw(adapter, 0x700, command);
106 for (i = 0; i < len; i++) {
107 command = bank | addr | 0x04008000;
111 while (((read_reg_dw(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {
116 if (retries == 0)
119 write_reg_dw(adapter, 0x700, command);
123 while (((read_reg_dw(adapter, 0x700) & 0x80000000) != 0) && (retries > 0)) {
128 if (retries == 0)
131 value = read_reg_dw(adapter, 0x700) >> 0x10;
133 *buf = (value & 0xff);
144 bank = 0;
146 if (adapter->dw_sram_type == 0x20000) {
147 bank = (addr & 0x18000) << 0x0d;
150 if (adapter->dw_sram_type == 0x00000) {
151 if ((addr >> 0x0f) == 0)
152 bank = 0x20000000;
154 bank = 0x10000000;
156 flex_sram_write(adapter, bank, addr & 0x7fff, buf, len);
162 bank = 0;
164 if (adapter->dw_sram_type == 0x20000) {
165 bank = (addr & 0x18000) << 0x0d;
168 if (adapter->dw_sram_type == 0x00000) {
169 if ((addr >> 0x0f) == 0)
170 bank = 0x20000000;
172 bank = 0x10000000;
174 flex_sram_read(adapter, bank, addr & 0x7fff, buf, len);
180 while (len != 0) {
185 if ((addr >> 0x0f) != ((addr + len - 1) >> 0x0f)) {
186 length = (((addr >> 0x0f) + 1) << 0x0f) - addr;
199 while (len != 0) {
205 if ((addr >> 0x0f) != ((addr + len - 1) >> 0x0f)) {
206 length = (((addr >> 0x0f) + 1) << 0x0f) - addr;
218 write_reg_dw(adapter, 0x71c,
219 (mask | (~0x30000 & read_reg_dw(adapter, 0x71c))));
225 tmp = read_reg_dw(adapter, 0x71c);
226 write_reg_dw(adapter, 0x71c, 1);
228 if (read_reg_dw(adapter, 0x71c) != 0) {
229 write_reg_dw(adapter, 0x71c, tmp);
230 adapter->dw_sram_type = tmp & 0x30000;
233 adapter->dw_sram_type = 0x10000;
246 tmp2 = 0xa5;
247 tmp1 = 0x4f;
252 tmp2 = 0;
258 dprintk("%s: wrote 0xa5, read 0x%2x\n", __func__, tmp2);
260 if (tmp2 != 0xa5)
261 return 0;
263 tmp2 = 0x5a;
264 tmp1 = 0xf4;
269 tmp2 = 0;
275 dprintk("%s: wrote 0x5a, read 0x%2x\n", __func__, tmp2);
277 if (tmp2 != 0x5a)
278 return 0;
284 if (adapter->dw_sram_type == 0x10000)
286 if (adapter->dw_sram_type == 0x00000)
288 if (adapter->dw_sram_type == 0x20000)
294 - for 128K there are 4x32K chips at bank 0,1,2,3.
296 - for 32K there is one 32K chip at bank 0.
299 by bits 28-29 of the 0x700 register.
301 bank 0 covers addresses 0x00000-0x07fff
302 bank 1 covers addresses 0x08000-0x0ffff
303 bank 2 covers addresses 0x10000-0x17fff
304 bank 3 covers addresses 0x18000-0x1ffff */
313 write_reg_dw(adapter, 0x71c, 1);
314 tmp3 = read_reg_dw(adapter, 0x71c);
316 write_reg_dw(adapter, 0x71c, tmp2);
320 if (tmp3 != 0) {
321 sram_set_size(adapter, 0x10000);
323 write_reg_dw(adapter, 0x208, tmp);
328 if (sram_test_location(adapter, 0x20000, 0x18000) != 0) {
329 sram_set_size(adapter, 0x20000);
331 write_reg_dw(adapter, 0x208, tmp);
336 if (sram_test_location(adapter, 0x00000, 0x10000) != 0) {
337 sram_set_size(adapter, 0x00000);
339 write_reg_dw(adapter, 0x208, tmp);
344 if (sram_test_location(adapter, 0x10000, 0x00000) != 0) {
345 sram_set_size(adapter, 0x10000);
347 write_reg_dw(adapter, 0x208, tmp);
352 sram_set_size(adapter, 0x10000);
354 write_reg_dw(adapter, 0x208, tmp);
356 return 0;