1 // SPDX-License-Identifier: GPL-2.0
3  *  Support for Versatile FPGA-based IRQ controllers
10 #include <linux/irqchip/versatile-fpga.h>
35  * struct fpga_irq_data - irq data container for the FPGA IRQ controller
39  * @valid: mask for valid IRQs on this controller
45 	u32 valid;  member
57 	u32 mask = 1 << d->hwirq;  in fpga_irq_mask()
59 	writel(mask, f->base + IRQ_ENABLE_CLEAR);  in fpga_irq_mask()
65 	u32 mask = 1 << d->hwirq;  in fpga_irq_unmask()
67 	writel(mask, f->base + IRQ_ENABLE_SET);  in fpga_irq_unmask()
78 	status = readl(f->base + IRQ_STATUS);  in fpga_irq_handle()
85 		unsigned int irq = ffs(status) - 1;  in fpga_irq_handle()
88 		generic_handle_irq(irq_find_mapping(f->domain, irq));  in fpga_irq_handle()
96  * Handle each interrupt in a single FPGA IRQ controller.  Returns non-zero
106 	while ((status  = readl(f->base + IRQ_STATUS))) {  in handle_one_fpga()
107 		irq = ffs(status) - 1;  in handle_one_fpga()
108 		handle_domain_irq(f->domain, irq, regs);  in handle_one_fpga()
132 	struct fpga_irq_data *f = d->host_data;  in fpga_irqdomain_map()
135 	if (!(f->valid & BIT(hwirq)))  in fpga_irqdomain_map()
136 		return -EPERM;  in fpga_irqdomain_map()
138 	irq_set_chip_and_handler(irq, &f->chip,  in fpga_irqdomain_map()
150 			  int parent_irq, u32 valid, struct device_node *node)  in fpga_irq_init()  argument
160 	f->base = base;  in fpga_irq_init()
161 	f->chip.name = name;  in fpga_irq_init()
162 	f->chip.irq_ack = fpga_irq_mask;  in fpga_irq_init()
163 	f->chip.irq_mask = fpga_irq_mask;  in fpga_irq_init()
164 	f->chip.irq_unmask = fpga_irq_unmask;  in fpga_irq_init()
165 	f->valid = valid;  in fpga_irq_init()
167 	if (parent_irq != -1) {  in fpga_irq_init()
173 	f->domain = irq_domain_add_simple(node, fls(valid), irq_start,  in fpga_irq_init()
176 	/* This will allocate all valid descriptors in the linear case */  in fpga_irq_init()
177 	for (i = 0; i < fls(valid); i++)  in fpga_irq_init()
178 		if (valid & BIT(i)) {  in fpga_irq_init()
180 				irq_create_mapping(f->domain, i);  in fpga_irq_init()
181 			f->used_irqs++;  in fpga_irq_init()
185 		fpga_irq_id, name, base, f->used_irqs);  in fpga_irq_init()
186 	if (parent_irq != -1)  in fpga_irq_init()
204 		return -ENODEV;  in fpga_irq_of_init()
209 	if (of_property_read_u32(node, "clear-mask", &clear_mask))  in fpga_irq_of_init()
212 	if (of_property_read_u32(node, "valid-mask", &valid_mask))  in fpga_irq_of_init()
222 		parent_irq = -1;  in fpga_irq_of_init()
225 	fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node);  in fpga_irq_of_init()
229 	 * pass-thru to the primary controller for IRQs 20 and 22-31 which need  in fpga_irq_of_init()
232 	if (of_device_is_compatible(node, "arm,versatile-sic"))  in fpga_irq_of_init()
237 IRQCHIP_DECLARE(arm_fpga, "arm,versatile-fpga-irq", fpga_irq_of_init);
238 IRQCHIP_DECLARE(arm_fpga_sic, "arm,versatile-sic", fpga_irq_of_init);
239 IRQCHIP_DECLARE(ox810se_rps, "oxsemi,ox810se-rps-irq", fpga_irq_of_init);