Lines Matching +full:irqs +full:- +full:reserved
1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/irq/irq-nvic.c
5 * Copyright (C) 2008 ARM Limited, All Rights Reserved.
9 * ARMv7-M CPUs (Cortex-M3/M4)
33 * Each bank handles 32 irqs. Only the 16th (= last) bank handles only
34 * 16 irqs.
36 #define NVIC_MAX_IRQ ((NVIC_MAX_BANKS - 1) * 32 + 16)
76 unsigned int irqs, i, ret, numbanks; in nvic_of_init() local
85 return -ENOMEM; in nvic_of_init()
88 irqs = numbanks * 32; in nvic_of_init()
89 if (irqs > NVIC_MAX_IRQ) in nvic_of_init()
90 irqs = NVIC_MAX_IRQ; in nvic_of_init()
93 irq_domain_add_linear(node, irqs, &nvic_irq_domain_ops, NULL); in nvic_of_init()
97 return -ENOMEM; in nvic_of_init()
113 gc->reg_base = nvic_base + 4 * i; in nvic_of_init()
114 gc->chip_types[0].regs.enable = NVIC_ISER; in nvic_of_init()
115 gc->chip_types[0].regs.disable = NVIC_ICER; in nvic_of_init()
116 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg; in nvic_of_init()
117 gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg; in nvic_of_init()
118 /* This is a no-op as end of interrupt is signaled by the in nvic_of_init()
121 gc->chip_types[0].chip.irq_eoi = irq_gc_noop; in nvic_of_init()
124 writel_relaxed(~0, gc->reg_base + NVIC_ICER); in nvic_of_init()
128 for (i = 0; i < irqs; i += 4) in nvic_of_init()
133 IRQCHIP_DECLARE(armv7m_nvic, "arm,armv7m-nvic", nvic_of_init);