162 static inline unsigned int gic_irq(struct irq_data *d)  in gic_irq()  function
183 	u32 mask = 1 << (gic_irq(d) % 32);  in gic_poke_irq()
184 	writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);  in gic_poke_irq()
189 	u32 mask = 1 << (gic_irq(d) % 32);  in gic_peek_irq()
190 	return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);  in gic_peek_irq()
220 	u32 hwirq = gic_irq(d);  in gic_eoi_irq()
230 	u32 hwirq = gic_irq(d);  in gic_eoimode1_eoi_irq()
294 	unsigned int gicirq = gic_irq(d);  in gic_set_type()
319 	if (cascading_gic_irq(d) || gic_irq(d) < 16)  in gic_irq_set_vcpu_affinity()
378 	unsigned int cascade_irq, gic_irq;  in gic_handle_cascade_irq()  local
385 	gic_irq = (status & GICC_IAR_INT_ID_MASK);  in gic_handle_cascade_irq()
386 	if (gic_irq == GICC_INT_SPURIOUS)  in gic_handle_cascade_irq()
389 	cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);  in gic_handle_cascade_irq()
390 	if (unlikely(gic_irq < 32 || gic_irq > 1020)) {  in gic_handle_cascade_irq()
783 	void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + gic_irq(d);  in gic_set_affinity()