1 // SPDX-License-Identifier: GPL-2.0-only
5  * Interrupt architecture for the GIC:
16  * Note that IRQs 0-31 are special - they are local to each CPU.
18  * registers are banked per-cpu for these sources.
40 #include <linux/irqchip/arm-gic.h>
48 #include "irq-gic-common.h"
111  * The GIC mapping of CPU interfaces does not necessarily match
113  * by the GIC itself.
137 		return raw_cpu_read(*base->percpu_base);  in __get_base()
139 	return base->common_base;  in __get_base()
142 #define gic_data_dist_base(d)	__get_base(&(d)->dist_base)
143 #define gic_data_cpu_base(d)	__get_base(&(d)->cpu_base)
145 #define gic_data_dist_base(d)	((d)->dist_base.common_base)
146 #define gic_data_cpu_base(d)	((d)->cpu_base.common_base)
164 	return d->hwirq;  in gic_irq()
261 		return -EINVAL;  in gic_irq_set_irqchip_state()
285 		return -EINVAL;  in gic_irq_get_irqchip_state()
299 		return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0;  in gic_set_type()
304 		return -EINVAL;  in gic_set_type()
309 		pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16);  in gic_set_type()
318 	/* Only interrupts on the primary GIC can be forwarded to a vcpu. */  in gic_irq_set_vcpu_affinity()
320 		return -EINVAL;  in gic_irq_set_vcpu_affinity()
337 	struct gic_chip_data *gic = &gic_data[0];  in gic_handle_irq()  local
338 	void __iomem *cpu_base = gic_data_cpu_base(gic);  in gic_handle_irq()
353 		 * is read after we've read the ACK register on the GIC.  in gic_handle_irq()
361 			 * The GIC encodes the source CPU in GICC_IAR,  in gic_handle_irq()
370 		handle_domain_irq(gic->domain, irqnr, regs);  in gic_handle_irq()
389 	cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);  in gic_handle_cascade_irq()
421 static u8 gic_get_cpumask(struct gic_chip_data *gic)  in gic_get_cpumask()  argument
423 	void __iomem *base = gic_data_dist_base(gic);  in gic_get_cpumask()
435 		pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");  in gic_get_cpumask()
446 static void gic_cpu_if_up(struct gic_chip_data *gic)  in gic_cpu_if_up()  argument
448 	void __iomem *cpu_base = gic_data_cpu_base(gic);  in gic_cpu_if_up()
453 	if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key))  in gic_cpu_if_up()
470 static void gic_dist_init(struct gic_chip_data *gic)  in gic_dist_init()  argument
474 	unsigned int gic_irqs = gic->gic_irqs;  in gic_dist_init()
475 	void __iomem *base = gic_data_dist_base(gic);  in gic_dist_init()
482 	cpumask = gic_get_cpumask(gic);  in gic_dist_init()
493 static int gic_cpu_init(struct gic_chip_data *gic)  in gic_cpu_init()  argument
495 	void __iomem *dist_base = gic_data_dist_base(gic);  in gic_cpu_init()
496 	void __iomem *base = gic_data_cpu_base(gic);  in gic_cpu_init()
501 	 * Setting up the CPU map is only relevant for the primary GIC  in gic_cpu_init()
505 	if (gic == &gic_data[0]) {  in gic_cpu_init()
507 		 * Get what the GIC says our CPU mask is.  in gic_cpu_init()
510 			return -EINVAL;  in gic_cpu_init()
513 		cpu_mask = gic_get_cpumask(gic);  in gic_cpu_init()
528 	gic_cpu_if_up(gic);  in gic_cpu_init()
539 		return -EINVAL;  in gic_cpu_if_down()
551  * Saves the GIC distributor registers during suspend or idle.  Must be called
552  * with interrupts disabled but before powering down the GIC.  After calling
553  * this function, no interrupts will be delivered by the GIC, and another
554  * platform-specific wakeup source must be enabled.
556 void gic_dist_save(struct gic_chip_data *gic)  in gic_dist_save()  argument
562 	if (WARN_ON(!gic))  in gic_dist_save()
565 	gic_irqs = gic->gic_irqs;  in gic_dist_save()
566 	dist_base = gic_data_dist_base(gic);  in gic_dist_save()
572 		gic->saved_spi_conf[i] =  in gic_dist_save()
576 		gic->saved_spi_target[i] =  in gic_dist_save()
580 		gic->saved_spi_enable[i] =  in gic_dist_save()
584 		gic->saved_spi_active[i] =  in gic_dist_save()
589  * Restores the GIC distributor registers during resume or when coming out of
591  * that occurred while the GIC was suspended is still present, it will be
593  * the GIC and need to be handled by the platform-specific wakeup source.
595 void gic_dist_restore(struct gic_chip_data *gic)  in gic_dist_restore()  argument
601 	if (WARN_ON(!gic))  in gic_dist_restore()
604 	gic_irqs = gic->gic_irqs;  in gic_dist_restore()
605 	dist_base = gic_data_dist_base(gic);  in gic_dist_restore()
613 		writel_relaxed(gic->saved_spi_conf[i],  in gic_dist_restore()
621 		writel_relaxed(gic->saved_spi_target[i],  in gic_dist_restore()
627 		writel_relaxed(gic->saved_spi_enable[i],  in gic_dist_restore()
634 		writel_relaxed(gic->saved_spi_active[i],  in gic_dist_restore()
641 void gic_cpu_save(struct gic_chip_data *gic)  in gic_cpu_save()  argument
648 	if (WARN_ON(!gic))  in gic_cpu_save()
651 	dist_base = gic_data_dist_base(gic);  in gic_cpu_save()
652 	cpu_base = gic_data_cpu_base(gic);  in gic_cpu_save()
657 	ptr = raw_cpu_ptr(gic->saved_ppi_enable);  in gic_cpu_save()
661 	ptr = raw_cpu_ptr(gic->saved_ppi_active);  in gic_cpu_save()
665 	ptr = raw_cpu_ptr(gic->saved_ppi_conf);  in gic_cpu_save()
671 void gic_cpu_restore(struct gic_chip_data *gic)  in gic_cpu_restore()  argument
678 	if (WARN_ON(!gic))  in gic_cpu_restore()
681 	dist_base = gic_data_dist_base(gic);  in gic_cpu_restore()
682 	cpu_base = gic_data_cpu_base(gic);  in gic_cpu_restore()
687 	ptr = raw_cpu_ptr(gic->saved_ppi_enable);  in gic_cpu_restore()
694 	ptr = raw_cpu_ptr(gic->saved_ppi_active);  in gic_cpu_restore()
701 	ptr = raw_cpu_ptr(gic->saved_ppi_conf);  in gic_cpu_restore()
710 	gic_cpu_if_up(gic);  in gic_cpu_restore()
743 static int gic_pm_init(struct gic_chip_data *gic)  in gic_pm_init()  argument
745 	gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,  in gic_pm_init()
747 	if (WARN_ON(!gic->saved_ppi_enable))  in gic_pm_init()
748 		return -ENOMEM;  in gic_pm_init()
750 	gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,  in gic_pm_init()
752 	if (WARN_ON(!gic->saved_ppi_active))  in gic_pm_init()
755 	gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,  in gic_pm_init()
757 	if (WARN_ON(!gic->saved_ppi_conf))  in gic_pm_init()
760 	if (gic == &gic_data[0])  in gic_pm_init()
766 	free_percpu(gic->saved_ppi_active);  in gic_pm_init()
768 	free_percpu(gic->saved_ppi_enable);  in gic_pm_init()
770 	return -ENOMEM;  in gic_pm_init()
773 static int gic_pm_init(struct gic_chip_data *gic)  in gic_pm_init()  argument
792 		return -EINVAL;  in gic_set_affinity()
806 		/* Only one CPU? let's do a self-IPI... */  in gic_ipi_send_mask()
807 		writel_relaxed(2 << 24 | d->hwirq,  in gic_ipi_send_mask()
825 	writel_relaxed(map << 16 | d->hwirq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);  in gic_ipi_send_mask()
839 		.fwnode		= gic_data[0].domain->fwnode,  in gic_smp_init()
845 				  "irqchip/arm/gic:starting",  in gic_smp_init()
848 	base_sgi = __irq_domain_alloc_irqs(gic_data[0].domain, -1, 8,  in gic_smp_init()
864  * gic_send_sgi - send a SGI directly to given CPU interface number
878  * gic_get_cpu_id - get the CPU interface ID for the specified CPU
880  * @cpu: the logical CPU number to get the GIC ID for.
883  * or -1 if the CPU number is too large or the interface ID is
891 		return -1;  in gic_get_cpu_id()
893 	if (cpu_bit & (cpu_bit - 1))  in gic_get_cpu_id()
894 		return -1;  in gic_get_cpu_id()
899  * gic_migrate_target - migrate IRQs to another CPU interface
924 	ror_val = (cur_cpu_id - new_cpu_id) & 31;  in gic_migrate_target()
934 	 * We skip DIST_TARGET 0 to 7 as they are read-only.  in gic_migrate_target()
974  * gic_get_sgir_physaddr - get the physical address for the SGI register
993 		pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);  in gic_init_physaddr()
1004 	struct gic_chip_data *gic = d->host_data;  in gic_irq_domain_map()  local
1010 		irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,  in gic_irq_domain_map()
1016 		irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,  in gic_irq_domain_map()
1020 		irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,  in gic_irq_domain_map()
1041 	if (fwspec->param_count == 1 && fwspec->param[0] < 16) {  in gic_irq_domain_translate()
1042 		*hwirq = fwspec->param[0];  in gic_irq_domain_translate()
1047 	if (is_of_node(fwspec->fwnode)) {  in gic_irq_domain_translate()
1048 		if (fwspec->param_count < 3)  in gic_irq_domain_translate()
1049 			return -EINVAL;  in gic_irq_domain_translate()
1051 		switch (fwspec->param[0]) {  in gic_irq_domain_translate()
1053 			*hwirq = fwspec->param[1] + 32;  in gic_irq_domain_translate()
1056 			*hwirq = fwspec->param[1] + 16;  in gic_irq_domain_translate()
1059 			return -EINVAL;  in gic_irq_domain_translate()
1062 		*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;  in gic_irq_domain_translate()
1069 	if (is_fwnode_irqchip(fwspec->fwnode)) {  in gic_irq_domain_translate()
1070 		if(fwspec->param_count != 2)  in gic_irq_domain_translate()
1071 			return -EINVAL;  in gic_irq_domain_translate()
1073 		*hwirq = fwspec->param[0];  in gic_irq_domain_translate()
1074 		*type = fwspec->param[1];  in gic_irq_domain_translate()
1080 	return -EINVAL;  in gic_irq_domain_translate()
1115 static void gic_init_chip(struct gic_chip_data *gic, struct device *dev,  in gic_init_chip()  argument
1119 	gic->chip = gic_chip;  in gic_init_chip()
1120 	gic->chip.name = name;  in gic_init_chip()
1121 	gic->chip.parent_device = dev;  in gic_init_chip()
1124 		gic->chip.irq_mask = gic_eoimode1_mask_irq;  in gic_init_chip()
1125 		gic->chip.irq_eoi = gic_eoimode1_eoi_irq;  in gic_init_chip()
1126 		gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity;  in gic_init_chip()
1129 	if (gic == &gic_data[0]) {  in gic_init_chip()
1130 		gic->chip.irq_set_affinity = gic_set_affinity;  in gic_init_chip()
1131 		gic->chip.ipi_send_mask = gic_ipi_send_mask;  in gic_init_chip()
1135 static int gic_init_bases(struct gic_chip_data *gic,  in gic_init_bases()  argument
1140 	if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {  in gic_init_bases()
1141 		/* Frankein-GIC without banked registers... */  in gic_init_bases()
1144 		gic->dist_base.percpu_base = alloc_percpu(void __iomem *);  in gic_init_bases()
1145 		gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);  in gic_init_bases()
1146 		if (WARN_ON(!gic->dist_base.percpu_base ||  in gic_init_bases()
1147 			    !gic->cpu_base.percpu_base)) {  in gic_init_bases()
1148 			ret = -ENOMEM;  in gic_init_bases()
1155 			unsigned long offset = gic->percpu_offset * core_id;  in gic_init_bases()
1156 			*per_cpu_ptr(gic->dist_base.percpu_base, cpu) =  in gic_init_bases()
1157 				gic->raw_dist_base + offset;  in gic_init_bases()
1158 			*per_cpu_ptr(gic->cpu_base.percpu_base, cpu) =  in gic_init_bases()
1159 				gic->raw_cpu_base + offset;  in gic_init_bases()
1164 		/* Normal, sane GIC... */  in gic_init_bases()
1165 		WARN(gic->percpu_offset,  in gic_init_bases()
1167 		     gic->percpu_offset);  in gic_init_bases()
1168 		gic->dist_base.common_base = gic->raw_dist_base;  in gic_init_bases()
1169 		gic->cpu_base.common_base = gic->raw_cpu_base;  in gic_init_bases()
1174 	 * The GIC only supports up to 1020 interrupt sources.  in gic_init_bases()
1176 	gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;  in gic_init_bases()
1180 	gic->gic_irqs = gic_irqs;  in gic_init_bases()
1183 		gic->domain = irq_domain_create_linear(handle, gic_irqs,  in gic_init_bases()
1185 						       gic);  in gic_init_bases()
1189 		 * No secondary GIC support whatsoever.  in gic_init_bases()
1193 		gic_irqs -= 16; /* calculate # of irqs to allocate */  in gic_init_bases()
1198 			WARN(1, "Cannot allocate irq_descs @ IRQ16, assuming pre-allocated\n");  in gic_init_bases()
1202 		gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base,  in gic_init_bases()
1203 						    16, &gic_irq_domain_ops, gic);  in gic_init_bases()
1206 	if (WARN_ON(!gic->domain)) {  in gic_init_bases()
1207 		ret = -ENODEV;  in gic_init_bases()
1211 	gic_dist_init(gic);  in gic_init_bases()
1212 	ret = gic_cpu_init(gic);  in gic_init_bases()
1216 	ret = gic_pm_init(gic);  in gic_init_bases()
1223 	if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {  in gic_init_bases()
1224 		free_percpu(gic->dist_base.percpu_base);  in gic_init_bases()
1225 		free_percpu(gic->cpu_base.percpu_base);  in gic_init_bases()
1231 static int __init __gic_init_bases(struct gic_chip_data *gic,  in __gic_init_bases()  argument
1237 	if (WARN_ON(!gic || gic->domain))  in __gic_init_bases()
1238 		return -EINVAL;  in __gic_init_bases()
1240 	if (gic == &gic_data[0]) {  in __gic_init_bases()
1243 		 * It will be refined as each CPU probes its ID.  in __gic_init_bases()
1244 		 * This is only necessary for the primary GIC.  in __gic_init_bases()
1251 			pr_info("GIC: Using split EOI/Deactivate mode\n");  in __gic_init_bases()
1254 	if (static_branch_likely(&supports_deactivate_key) && gic == &gic_data[0]) {  in __gic_init_bases()
1256 		gic_init_chip(gic, NULL, name, true);  in __gic_init_bases()
1258 		name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0]));  in __gic_init_bases()
1259 		gic_init_chip(gic, NULL, name, false);  in __gic_init_bases()
1262 	ret = gic_init_bases(gic, handle);  in __gic_init_bases()
1265 	else if (gic == &gic_data[0])  in __gic_init_bases()
1273 	struct gic_chip_data *gic;  in gic_init()  local
1276 	 * Non-DT/ACPI systems won't run a hypervisor, so let's not  in gic_init()
1281 	gic = &gic_data[0];  in gic_init()
1282 	gic->raw_dist_base = dist_base;  in gic_init()
1283 	gic->raw_cpu_base = cpu_base;  in gic_init()
1285 	__gic_init_bases(gic, NULL);  in gic_init()
1288 static void gic_teardown(struct gic_chip_data *gic)  in gic_teardown()  argument
1290 	if (WARN_ON(!gic))  in gic_teardown()
1293 	if (gic->raw_dist_base)  in gic_teardown()
1294 		iounmap(gic->raw_dist_base);  in gic_teardown()
1295 	if (gic->raw_cpu_base)  in gic_teardown()
1296 		iounmap(gic->raw_cpu_base);  in gic_teardown()
1327 			pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n");  in gic_check_eoimode()
1340 			pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n",  in gic_check_eoimode()
1357 		pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n",  in gic_check_eoimode()
1359 		cpuif_res.end = cpuif_res.start + SZ_128K -1;  in gic_check_eoimode()
1376 		 * at its normal offset. Please pass me that bucket.  in gic_check_eoimode()
1380 		pr_warn("GIC: Adjusting CPU interface base to %pa\n",  in gic_check_eoimode()
1387 static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)  in gic_of_setup()  argument
1389 	if (!gic || !node)  in gic_of_setup()
1390 		return -EINVAL;  in gic_of_setup()
1392 	gic->raw_dist_base = of_iomap(node, 0);  in gic_of_setup()
1393 	if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n"))  in gic_of_setup()
1396 	gic->raw_cpu_base = of_iomap(node, 1);  in gic_of_setup()
1397 	if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n"))  in gic_of_setup()
1400 	if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset))  in gic_of_setup()
1401 		gic->percpu_offset = 0;  in gic_of_setup()
1406 	gic_teardown(gic);  in gic_of_setup()
1408 	return -ENOMEM;  in gic_of_setup()
1411 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)  in gic_of_init_child()  argument
1415 	if (!dev || !dev->of_node || !gic || !irq)  in gic_of_init_child()
1416 		return -EINVAL;  in gic_of_init_child()
1418 	*gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL);  in gic_of_init_child()
1419 	if (!*gic)  in gic_of_init_child()
1420 		return -ENOMEM;  in gic_of_init_child()
1422 	gic_init_chip(*gic, dev, dev->of_node->name, false);  in gic_of_init_child()
1424 	ret = gic_of_setup(*gic, dev->of_node);  in gic_of_init_child()
1428 	ret = gic_init_bases(*gic, &dev->of_node->fwnode);  in gic_of_init_child()
1430 		gic_teardown(*gic);  in gic_of_init_child()
1434 	irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic);  in gic_of_init_child()
1466 	struct gic_chip_data *gic;  in gic_of_init()  local
1470 		return -ENODEV;  in gic_of_init()
1473 		return -EINVAL;  in gic_of_init()
1475 	gic = &gic_data[gic_cnt];  in gic_of_init()
1477 	ret = gic_of_setup(gic, node);  in gic_of_init()
1485 	if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))  in gic_of_init()
1488 	ret = __gic_init_bases(gic, &node->fwnode);  in gic_of_init()
1490 		gic_teardown(gic);  in gic_of_init()
1505 		gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain);  in gic_of_init()
1510 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1511 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1512 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1513 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1514 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1515 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1516 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1517 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
1520 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)  in gic_of_init_child()  argument
1522 	return -ENOTSUPP;  in gic_of_init_child()
1547 		return -EINVAL;  in gic_acpi_parse_madt_cpu()
1550 	 * There is no support for non-banked GICv1/2 register in ACPI spec.  in gic_acpi_parse_madt_cpu()
1553 	gic_cpu_base = processor->base_address;  in gic_acpi_parse_madt_cpu()
1555 		return -EINVAL;  in gic_acpi_parse_madt_cpu()
1558 	acpi_data.maint_irq = processor->vgic_interrupt;  in gic_acpi_parse_madt_cpu()
1559 	acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ?  in gic_acpi_parse_madt_cpu()
1561 	acpi_data.vctrl_base = processor->gich_base_address;  in gic_acpi_parse_madt_cpu()
1562 	acpi_data.vcpu_base = processor->gicv_base_address;  in gic_acpi_parse_madt_cpu()
1587 	return (dist->version == ape->driver_data &&  in gic_validate_dist()
1588 		(dist->version != ACPI_MADT_GIC_VERSION_NONE ||  in gic_validate_dist()
1608 	vctrl_res->flags = IORESOURCE_MEM;  in gic_acpi_setup_kvm_info()
1609 	vctrl_res->start = acpi_data.vctrl_base;  in gic_acpi_setup_kvm_info()
1610 	vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1;  in gic_acpi_setup_kvm_info()
1615 	vcpu_res->flags = IORESOURCE_MEM;  in gic_acpi_setup_kvm_info()
1616 	vcpu_res->start = acpi_data.vcpu_base;  in gic_acpi_setup_kvm_info()
1617 	vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;  in gic_acpi_setup_kvm_info()
1635 	struct gic_chip_data *gic = &gic_data[0];  in gic_v2_acpi_init()  local
1643 		return -EINVAL;  in gic_v2_acpi_init()
1646 	gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE);  in gic_v2_acpi_init()
1647 	if (!gic->raw_cpu_base) {  in gic_v2_acpi_init()
1649 		return -ENOMEM;  in gic_v2_acpi_init()
1653 	gic->raw_dist_base = ioremap(dist->base_address,  in gic_v2_acpi_init()
1655 	if (!gic->raw_dist_base) {  in gic_v2_acpi_init()
1657 		gic_teardown(gic);  in gic_v2_acpi_init()
1658 		return -ENOMEM;  in gic_v2_acpi_init()
1670 	 * Initialize GIC instance zero (no multi-GIC support).  in gic_v2_acpi_init()
1672 	domain_handle = irq_domain_alloc_fwnode(&dist->base_address);  in gic_v2_acpi_init()
1675 		gic_teardown(gic);  in gic_v2_acpi_init()
1676 		return -ENOMEM;  in gic_v2_acpi_init()
1679 	ret = __gic_init_bases(gic, domain_handle);  in gic_v2_acpi_init()
1681 		pr_err("Failed to initialise GIC\n");  in gic_v2_acpi_init()
1683 		gic_teardown(gic);  in gic_v2_acpi_init()