Lines Matching +full:ppi +full:- +full:partitions
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
23 #include <linux/irqchip/arm-gic-common.h>
24 #include <linux/irqchip/arm-gic-v3.h>
25 #include <linux/irqchip/irq-partition-percpu.h>
32 #include "irq-gic-common.h"
70 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
74 * When security is enabled, non-secure priority values from the (re)distributor
78 * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure
84 * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
86 * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1
103 /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */
111 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
149 return __get_intid_range(d->hwirq); in get_intid_range()
154 return d->hwirq; in gic_irq()
175 /* SGI+PPI -> SGI_base for this CPU */ in gic_dist_base()
180 /* SPI -> dist_base */ in gic_dist_base()
193 count--; in gic_do_wait_for_rwp()
251 while (--count) { in gic_enable_redist()
272 *index = d->hwirq; in convert_offset_index()
277 * to the PPI range in the registers, so let's adjust the in convert_offset_index()
280 *index = d->hwirq - EPPI_BASE_INTID + 32; in convert_offset_index()
283 *index = d->hwirq - ESPI_BASE_INTID; in convert_offset_index()
312 *index = d->hwirq; in convert_offset_index()
389 if (d->hwirq >= 8192) /* SGI/PPI/SPI only */ in gic_irq_set_irqchip_state()
390 return -EINVAL; in gic_irq_set_irqchip_state()
406 return -EINVAL; in gic_irq_set_irqchip_state()
416 if (d->hwirq >= 8192) /* PPI/SPI only */ in gic_irq_get_irqchip_state()
417 return -EINVAL; in gic_irq_get_irqchip_state()
433 return -EINVAL; in gic_irq_get_irqchip_state()
453 return d->hwirq - 16; in gic_get_ppi_index()
455 return d->hwirq - EPPI_BASE_INTID + 16; in gic_get_ppi_index()
463 struct irq_desc *desc = irq_to_desc(d->irq); in gic_irq_nmi_setup()
466 return -EINVAL; in gic_irq_nmi_setup()
469 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); in gic_irq_nmi_setup()
470 return -EINVAL; in gic_irq_nmi_setup()
478 return -EINVAL; in gic_irq_nmi_setup()
484 /* Setting up PPI as NMI, only switch handler for first NMI */ in gic_irq_nmi_setup()
487 desc->handle_irq = handle_percpu_devid_fasteoi_nmi; in gic_irq_nmi_setup()
490 desc->handle_irq = handle_fasteoi_nmi; in gic_irq_nmi_setup()
500 struct irq_desc *desc = irq_to_desc(d->irq); in gic_irq_nmi_teardown()
506 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); in gic_irq_nmi_teardown()
523 desc->handle_irq = handle_percpu_devid_irq; in gic_irq_nmi_teardown()
525 desc->handle_irq = handle_fasteoi_irq; in gic_irq_nmi_teardown()
560 return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0; in gic_set_type()
565 return -EINVAL; in gic_set_type()
580 pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq); in gic_set_type()
590 return -EINVAL; in gic_irq_set_vcpu_affinity()
698 * setting the highest possible, non-zero priority in PMR. in gic_has_group0()
702 * actual priority in the non-secure range. In the process, it in gic_has_group0()
707 gic_write_pmr(BIT(8 - gic_get_pribits())); in gic_has_group0()
727 * Configure SPIs as non-secure Group-1. This will only matter in gic_dist_init()
776 int ret = -ENODEV; in gic_iterate_rdists()
810 return ret ? -ENODEV : 0; in gic_iterate_rdists()
830 u64 offset = ptr - region->redist_base; in __gic_populate_rdist()
831 raw_spin_lock_init(&gic_data_rdist()->rd_lock); in __gic_populate_rdist()
833 gic_data_rdist()->phys_base = region->phys_base + offset; in __gic_populate_rdist()
837 (int)(region - gic_data.redist_regions), in __gic_populate_rdist()
838 &gic_data_rdist()->phys_base); in __gic_populate_rdist()
852 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", in gic_populate_rdist()
855 return -ENODEV; in gic_populate_rdist()
865 /* RVPEID implies some form of DirectLPI, no matter what the doc says... :-/ */ in __gic_update_rdist_properties()
871 /* Detect non-sensical configurations */ in __gic_update_rdist_properties()
947 * any pre-emptive interrupts from working at all). Writing a zero in gic_cpu_sys_reg_init()
1016 * - The write is ignored. in gic_cpu_sys_reg_init()
1017 * - The RS field is treated as 0. in gic_cpu_sys_reg_init()
1056 /* Configure SGIs/PPIs as non-secure Group-1 */ in gic_cpu_init()
1099 cpu--; in gic_compute_target_list()
1131 if (WARN_ON(d->hwirq >= 16)) in gic_ipi_send_mask()
1145 gic_send_sgi(cluster_id, tlist, d->hwirq); in gic_ipi_send_mask()
1164 /* Register all 8 non-secure SGIs */ in gic_smp_init()
1165 base_sgi = __irq_domain_alloc_irqs(gic_data.domain, -1, 8, in gic_smp_init()
1189 return -EINVAL; in gic_set_affinity()
1192 return -EINVAL; in gic_set_affinity()
1306 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
1314 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
1320 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
1328 return -EPERM; in gic_irq_domain_map()
1329 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
1334 return -EPERM; in gic_irq_domain_map()
1347 if (fwspec->param_count == 1 && fwspec->param[0] < 16) { in gic_irq_domain_translate()
1348 *hwirq = fwspec->param[0]; in gic_irq_domain_translate()
1353 if (is_of_node(fwspec->fwnode)) { in gic_irq_domain_translate()
1354 if (fwspec->param_count < 3) in gic_irq_domain_translate()
1355 return -EINVAL; in gic_irq_domain_translate()
1357 switch (fwspec->param[0]) { in gic_irq_domain_translate()
1359 *hwirq = fwspec->param[1] + 32; in gic_irq_domain_translate()
1361 case 1: /* PPI */ in gic_irq_domain_translate()
1362 *hwirq = fwspec->param[1] + 16; in gic_irq_domain_translate()
1365 *hwirq = fwspec->param[1] + ESPI_BASE_INTID; in gic_irq_domain_translate()
1368 *hwirq = fwspec->param[1] + EPPI_BASE_INTID; in gic_irq_domain_translate()
1371 *hwirq = fwspec->param[1]; in gic_irq_domain_translate()
1374 *hwirq = fwspec->param[1]; in gic_irq_domain_translate()
1375 if (fwspec->param[1] >= 16) in gic_irq_domain_translate()
1376 *hwirq += EPPI_BASE_INTID - 16; in gic_irq_domain_translate()
1381 return -EINVAL; in gic_irq_domain_translate()
1384 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; in gic_irq_domain_translate()
1391 fwspec->param[0] != GIC_IRQ_TYPE_PARTITION); in gic_irq_domain_translate()
1395 if (is_fwnode_irqchip(fwspec->fwnode)) { in gic_irq_domain_translate()
1396 if(fwspec->param_count != 2) in gic_irq_domain_translate()
1397 return -EINVAL; in gic_irq_domain_translate()
1399 *hwirq = fwspec->param[0]; in gic_irq_domain_translate()
1400 *type = fwspec->param[1]; in gic_irq_domain_translate()
1406 return -EINVAL; in gic_irq_domain_translate()
1447 if (fwspec->fwnode != d->fwnode) in gic_irq_domain_select()
1451 if (!is_of_node(fwspec->fwnode)) in gic_irq_domain_select()
1455 * If this is a PPI and we have a 4th (non-null) parameter, in gic_irq_domain_select()
1458 if (fwspec->param_count >= 4 && in gic_irq_domain_select()
1459 fwspec->param[0] == 1 && fwspec->param[3] != 0 && in gic_irq_domain_select()
1461 return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); in gic_irq_domain_select()
1482 return -ENOMEM; in partition_domain_translate()
1484 np = of_find_node_by_phandle(fwspec->param[3]); in partition_domain_translate()
1486 return -EINVAL; in partition_domain_translate()
1488 ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], in partition_domain_translate()
1494 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; in partition_domain_translate()
1508 d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996; in gic_enable_quirk_msm8996()
1517 d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539; in gic_enable_quirk_cavium_38539()
1527 * HIP06 GICD_IIDR clashes with GIC-600 product number (despite in gic_enable_quirk_hip06_07()
1529 * that GIC-600 doesn't have ESPI, so nothing to do in that case. in gic_enable_quirk_hip06_07()
1533 if (d->rdists.gicd_typer & GICD_TYPER_ESPI) { in gic_enable_quirk_hip06_07()
1535 d->rdists.gicd_typer &= ~GENMASK(9, 8); in gic_enable_quirk_hip06_07()
1545 .compatible = "qcom,msm8996-gic-v3",
1564 * - ThunderX: CN88xx
1565 * - OCTEON TX: CN83xx, CN81xx
1566 * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx*
1599 pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n", in gic_enable_nmi_support()
1605 * and if Group 0 interrupts can be delivered to Linux in the non-secure in gic_enable_nmi_support()
1611 * ----------------------------------------------------------- in gic_enable_nmi_support()
1612 * 1 | - | unchanged | unchanged in gic_enable_nmi_support()
1613 * ----------------------------------------------------------- in gic_enable_nmi_support()
1614 * 0 | 1 | non-secure | non-secure in gic_enable_nmi_support()
1615 * ----------------------------------------------------------- in gic_enable_nmi_support()
1616 * 0 | 0 | unchanged | non-secure in gic_enable_nmi_support()
1618 * where non-secure means that the value is right-shifted by one and the in gic_enable_nmi_support()
1619 * MSB bit set, to make it fit in the non-secure priority range. in gic_enable_nmi_support()
1626 * be in the non-secure range, we use a different PMR value to mask IRQs in gic_enable_nmi_support()
1670 pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32); in gic_init_bases()
1689 err = -ENOMEM; in gic_init_bases()
1738 return -ENODEV; in gic_validate_dist_version()
1743 /* Create all possible partitions at boot time */
1751 parts_node = of_get_child_by_name(gic_node, "ppi-partitions"); in gic_populate_ppi_partitions()
1774 part->partition_id = of_node_to_fwnode(child_part); in gic_populate_ppi_partitions()
1776 pr_info("GIC: PPI partition %pOFn[%d] { ", in gic_populate_ppi_partitions()
1803 cpumask_set_cpu(cpu, &part->mask); in gic_populate_ppi_partitions()
1850 if (of_property_read_u32(node, "#redistributor-regions", in gic_of_setup_kvm_info()
1875 return -ENXIO; in gic_of_init()
1884 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) in gic_of_init()
1890 err = -ENOMEM; in gic_of_init()
1902 err = -ENODEV; in gic_of_init()
1908 if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) in gic_of_init()
1914 redist_stride, &node->fwnode); in gic_of_init()
1934 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
1968 redist_base = ioremap(redist->base_address, redist->length); in gic_acpi_parse_madt_redist()
1970 pr_err("Couldn't map GICR region @%llx\n", redist->base_address); in gic_acpi_parse_madt_redist()
1971 return -ENOMEM; in gic_acpi_parse_madt_redist()
1974 gic_acpi_register_redist(redist->base_address, redist_base); in gic_acpi_parse_madt_redist()
1989 if (!(gicc->flags & ACPI_MADT_ENABLED)) in gic_acpi_parse_madt_gicc()
1992 redist_base = ioremap(gicc->gicr_base_address, size); in gic_acpi_parse_madt_gicc()
1994 return -ENOMEM; in gic_acpi_parse_madt_gicc()
1996 gic_acpi_register_redist(gicc->gicr_base_address, redist_base); in gic_acpi_parse_madt_gicc()
2018 return -ENODEV; in gic_acpi_collect_gicr_base()
2038 if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) { in gic_acpi_match_gicc()
2047 if (!(gicc->flags & ACPI_MADT_ENABLED)) in gic_acpi_match_gicc()
2050 return -ENODEV; in gic_acpi_match_gicc()
2086 if (dist->version != ape->driver_data) in acpi_validate_gic_table()
2107 if (!(gicc->flags & ACPI_MADT_ENABLED)) in gic_acpi_parse_virt_madt_gicc()
2110 maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? in gic_acpi_parse_virt_madt_gicc()
2116 acpi_data.maint_irq = gicc->vgic_interrupt; in gic_acpi_parse_virt_madt_gicc()
2118 acpi_data.vcpu_base = gicc->gicv_base_address; in gic_acpi_parse_virt_madt_gicc()
2126 if ((acpi_data.maint_irq != gicc->vgic_interrupt) || in gic_acpi_parse_virt_madt_gicc()
2128 (acpi_data.vcpu_base != gicc->gicv_base_address)) in gic_acpi_parse_virt_madt_gicc()
2129 return -EINVAL; in gic_acpi_parse_virt_madt_gicc()
2170 vcpu->flags = IORESOURCE_MEM; in gic_acpi_setup_kvm_info()
2171 vcpu->start = acpi_data.vcpu_base; in gic_acpi_setup_kvm_info()
2172 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; in gic_acpi_setup_kvm_info()
2190 acpi_data.dist_base = ioremap(dist->base_address, in gic_acpi_init()
2194 return -ENOMEM; in gic_acpi_init()
2207 err = -ENOMEM; in gic_acpi_init()
2215 domain_handle = irq_domain_alloc_fwnode(&dist->base_address); in gic_acpi_init()
2217 err = -ENOMEM; in gic_acpi_init()