Lines Matching +full:synquacer +full:- +full:pre +full:- +full:its
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
14 #include <linux/dma-iommu.h>
34 #include <linux/irqchip/arm-gic-v3.h>
35 #include <linux/irqchip/arm-gic-v4.h>
40 #include "irq-gic-common.h"
63 * Collection structure - just an ID, and a redistributor address to
73 * The ITS_BASER structure - contains memory information, cached
74 * value of BASER register configuration and ITS page size.
86 * The ITS structure - contains most of the infrastructure, with the
87 * top-level MSI domain, the command queue, the collections, and the
116 u32 pre_its_base; /* for Socionext Synquacer */
120 #define is_v4(its) (!!((its)->typer & GITS_TYPER_VLPIS)) argument
121 #define is_v4_1(its) (!!((its)->typer & GITS_TYPER_VMAPP)) argument
122 #define device_ids(its) (FIELD_GET(GITS_TYPER_DEVBITS, (its)->typer) + 1) argument
130 if (gic_rdists->has_rvpeid && \
131 gic_rdists->gicd_typer2 & GICD_TYPER2_VIL) \
132 nvpeid = 1 + (gic_rdists->gicd_typer2 & \
154 * The ITS view of a device - belongs to an ITS, owns an interrupt
155 * translation table, and a list of interrupts. If it some of its
161 struct its_node *its; member
194 #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
195 #define gic_data_rdist_cpu(cpu) (per_cpu_ptr(gic_rdists->rdist, cpu))
196 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
203 static bool require_its_list_vmovp(struct its_vm *vm, struct its_node *its) in require_its_list_vmovp() argument
205 return (gic_rdists->has_rvpeid || vm->vlpi_count[its->list_nr]); in require_its_list_vmovp()
210 struct its_node *its; in get_its_list() local
213 list_for_each_entry(its, &its_nodes, entry) { in get_its_list()
214 if (!is_v4(its)) in get_its_list()
217 if (require_its_list_vmovp(vm, its)) in get_its_list()
218 __set_bit(its->list_nr, &its_list); in get_its_list()
227 return d->hwirq - its_dev->event_map.lpi_base; in its_get_event_id()
233 struct its_node *its = its_dev->its; in dev_event_to_col() local
235 return its->collections + its_dev->event_map.col_map[event]; in dev_event_to_col()
241 if (WARN_ON_ONCE(event >= its_dev->event_map.nr_lpis)) in dev_event_to_vlpi_map()
244 return &its_dev->event_map.vlpi_maps[event]; in dev_event_to_vlpi_map()
261 raw_spin_lock_irqsave(&vpe->vpe_lock, *flags); in vpe_to_cpuid_lock()
262 return vpe->col_idx; in vpe_to_cpuid_lock()
267 raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags); in vpe_to_cpuid_unlock()
276 cpu = vpe_to_cpuid_lock(map->vpe, flags); in irq_to_cpuid_lock()
280 cpu = its_dev->event_map.col_map[its_get_event_id(d)]; in irq_to_cpuid_lock()
293 vpe_to_cpuid_unlock(map->vpe, flags); in irq_to_cpuid_unlock()
298 if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0))) in valid_col()
304 static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe) in valid_vpe() argument
306 if (valid_col(its->collections + vpe->col_idx)) in valid_vpe()
313 * ITS command descriptors - parameters to be encoded in a command
412 * The ITS command block, which is what the ITS actually parses.
441 its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0); in its_encode_cmd()
446 its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32); in its_encode_devid()
451 its_mask_encode(&cmd->raw_cmd[1], id, 31, 0); in its_encode_event_id()
456 its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32); in its_encode_phys_id()
461 its_mask_encode(&cmd->raw_cmd[1], size, 4, 0); in its_encode_size()
466 its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8); in its_encode_itt()
471 its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63); in its_encode_valid()
476 its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16); in its_encode_target()
481 its_mask_encode(&cmd->raw_cmd[2], col, 15, 0); in its_encode_collection()
486 its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32); in its_encode_vpeid()
491 its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0); in its_encode_virt_id()
496 its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32); in its_encode_db_phys_id()
501 its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0); in its_encode_db_valid()
506 its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32); in its_encode_seq_num()
511 its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0); in its_encode_its_list()
516 its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16); in its_encode_vpt_addr()
521 its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0); in its_encode_vpt_size()
526 its_mask_encode(&cmd->raw_cmd[0], vconf_pa >> 16, 51, 16); in its_encode_vconf_addr()
531 its_mask_encode(&cmd->raw_cmd[0], alloc, 8, 8); in its_encode_alloc()
536 its_mask_encode(&cmd->raw_cmd[0], ptz, 9, 9); in its_encode_ptz()
542 its_mask_encode(&cmd->raw_cmd[1], vpe_db_lpi, 31, 0); in its_encode_vmapp_default_db()
548 its_mask_encode(&cmd->raw_cmd[3], vpe_db_lpi, 31, 0); in its_encode_vmovp_default_db()
553 its_mask_encode(&cmd->raw_cmd[2], db, 63, 63); in its_encode_db()
558 its_mask_encode(&cmd->raw_cmd[0], sgi, 35, 32); in its_encode_sgi_intid()
563 its_mask_encode(&cmd->raw_cmd[0], prio >> 4, 23, 20); in its_encode_sgi_priority()
568 its_mask_encode(&cmd->raw_cmd[0], grp, 10, 10); in its_encode_sgi_group()
573 its_mask_encode(&cmd->raw_cmd[0], clr, 9, 9); in its_encode_sgi_clear()
578 its_mask_encode(&cmd->raw_cmd[0], en, 8, 8); in its_encode_sgi_enable()
584 cmd->raw_cmd_le[0] = cpu_to_le64(cmd->raw_cmd[0]); in its_fixup_cmd()
585 cmd->raw_cmd_le[1] = cpu_to_le64(cmd->raw_cmd[1]); in its_fixup_cmd()
586 cmd->raw_cmd_le[2] = cpu_to_le64(cmd->raw_cmd[2]); in its_fixup_cmd()
587 cmd->raw_cmd_le[3] = cpu_to_le64(cmd->raw_cmd[3]); in its_fixup_cmd()
590 static struct its_collection *its_build_mapd_cmd(struct its_node *its, in its_build_mapd_cmd() argument
595 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites); in its_build_mapd_cmd()
597 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt); in its_build_mapd_cmd()
601 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id); in its_build_mapd_cmd()
602 its_encode_size(cmd, size - 1); in its_build_mapd_cmd()
604 its_encode_valid(cmd, desc->its_mapd_cmd.valid); in its_build_mapd_cmd()
611 static struct its_collection *its_build_mapc_cmd(struct its_node *its, in its_build_mapc_cmd() argument
616 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); in its_build_mapc_cmd()
617 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address); in its_build_mapc_cmd()
618 its_encode_valid(cmd, desc->its_mapc_cmd.valid); in its_build_mapc_cmd()
622 return desc->its_mapc_cmd.col; in its_build_mapc_cmd()
625 static struct its_collection *its_build_mapti_cmd(struct its_node *its, in its_build_mapti_cmd() argument
631 col = dev_event_to_col(desc->its_mapti_cmd.dev, in its_build_mapti_cmd()
632 desc->its_mapti_cmd.event_id); in its_build_mapti_cmd()
635 its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id); in its_build_mapti_cmd()
636 its_encode_event_id(cmd, desc->its_mapti_cmd.event_id); in its_build_mapti_cmd()
637 its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id); in its_build_mapti_cmd()
638 its_encode_collection(cmd, col->col_id); in its_build_mapti_cmd()
645 static struct its_collection *its_build_movi_cmd(struct its_node *its, in its_build_movi_cmd() argument
651 col = dev_event_to_col(desc->its_movi_cmd.dev, in its_build_movi_cmd()
652 desc->its_movi_cmd.event_id); in its_build_movi_cmd()
655 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id); in its_build_movi_cmd()
656 its_encode_event_id(cmd, desc->its_movi_cmd.event_id); in its_build_movi_cmd()
657 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id); in its_build_movi_cmd()
664 static struct its_collection *its_build_discard_cmd(struct its_node *its, in its_build_discard_cmd() argument
670 col = dev_event_to_col(desc->its_discard_cmd.dev, in its_build_discard_cmd()
671 desc->its_discard_cmd.event_id); in its_build_discard_cmd()
674 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id); in its_build_discard_cmd()
675 its_encode_event_id(cmd, desc->its_discard_cmd.event_id); in its_build_discard_cmd()
682 static struct its_collection *its_build_inv_cmd(struct its_node *its, in its_build_inv_cmd() argument
688 col = dev_event_to_col(desc->its_inv_cmd.dev, in its_build_inv_cmd()
689 desc->its_inv_cmd.event_id); in its_build_inv_cmd()
692 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); in its_build_inv_cmd()
693 its_encode_event_id(cmd, desc->its_inv_cmd.event_id); in its_build_inv_cmd()
700 static struct its_collection *its_build_int_cmd(struct its_node *its, in its_build_int_cmd() argument
706 col = dev_event_to_col(desc->its_int_cmd.dev, in its_build_int_cmd()
707 desc->its_int_cmd.event_id); in its_build_int_cmd()
710 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id); in its_build_int_cmd()
711 its_encode_event_id(cmd, desc->its_int_cmd.event_id); in its_build_int_cmd()
718 static struct its_collection *its_build_clear_cmd(struct its_node *its, in its_build_clear_cmd() argument
724 col = dev_event_to_col(desc->its_clear_cmd.dev, in its_build_clear_cmd()
725 desc->its_clear_cmd.event_id); in its_build_clear_cmd()
728 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id); in its_build_clear_cmd()
729 its_encode_event_id(cmd, desc->its_clear_cmd.event_id); in its_build_clear_cmd()
736 static struct its_collection *its_build_invall_cmd(struct its_node *its, in its_build_invall_cmd() argument
741 its_encode_collection(cmd, desc->its_invall_cmd.col->col_id); in its_build_invall_cmd()
748 static struct its_vpe *its_build_vinvall_cmd(struct its_node *its, in its_build_vinvall_cmd() argument
753 its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id); in its_build_vinvall_cmd()
757 return valid_vpe(its, desc->its_vinvall_cmd.vpe); in its_build_vinvall_cmd()
760 static struct its_vpe *its_build_vmapp_cmd(struct its_node *its, in its_build_vmapp_cmd() argument
769 its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id); in its_build_vmapp_cmd()
770 its_encode_valid(cmd, desc->its_vmapp_cmd.valid); in its_build_vmapp_cmd()
772 if (!desc->its_vmapp_cmd.valid) { in its_build_vmapp_cmd()
773 if (is_v4_1(its)) { in its_build_vmapp_cmd()
774 alloc = !atomic_dec_return(&desc->its_vmapp_cmd.vpe->vmapp_count); in its_build_vmapp_cmd()
781 vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page)); in its_build_vmapp_cmd()
782 target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset; in its_build_vmapp_cmd()
786 its_encode_vpt_size(cmd, LPI_NRBITS - 1); in its_build_vmapp_cmd()
788 if (!is_v4_1(its)) in its_build_vmapp_cmd()
791 vconf_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->its_vm->vprop_page)); in its_build_vmapp_cmd()
793 alloc = !atomic_fetch_inc(&desc->its_vmapp_cmd.vpe->vmapp_count); in its_build_vmapp_cmd()
800 its_encode_vmapp_default_db(cmd, desc->its_vmapp_cmd.vpe->vpe_db_lpi); in its_build_vmapp_cmd()
805 return valid_vpe(its, desc->its_vmapp_cmd.vpe); in its_build_vmapp_cmd()
808 static struct its_vpe *its_build_vmapti_cmd(struct its_node *its, in its_build_vmapti_cmd() argument
814 if (!is_v4_1(its) && desc->its_vmapti_cmd.db_enabled) in its_build_vmapti_cmd()
815 db = desc->its_vmapti_cmd.vpe->vpe_db_lpi; in its_build_vmapti_cmd()
820 its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id); in its_build_vmapti_cmd()
821 its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id); in its_build_vmapti_cmd()
822 its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id); in its_build_vmapti_cmd()
824 its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id); in its_build_vmapti_cmd()
828 return valid_vpe(its, desc->its_vmapti_cmd.vpe); in its_build_vmapti_cmd()
831 static struct its_vpe *its_build_vmovi_cmd(struct its_node *its, in its_build_vmovi_cmd() argument
837 if (!is_v4_1(its) && desc->its_vmovi_cmd.db_enabled) in its_build_vmovi_cmd()
838 db = desc->its_vmovi_cmd.vpe->vpe_db_lpi; in its_build_vmovi_cmd()
843 its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id); in its_build_vmovi_cmd()
844 its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id); in its_build_vmovi_cmd()
845 its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id); in its_build_vmovi_cmd()
851 return valid_vpe(its, desc->its_vmovi_cmd.vpe); in its_build_vmovi_cmd()
854 static struct its_vpe *its_build_vmovp_cmd(struct its_node *its, in its_build_vmovp_cmd() argument
860 target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset; in its_build_vmovp_cmd()
862 its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num); in its_build_vmovp_cmd()
863 its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list); in its_build_vmovp_cmd()
864 its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id); in its_build_vmovp_cmd()
867 if (is_v4_1(its)) { in its_build_vmovp_cmd()
869 its_encode_vmovp_default_db(cmd, desc->its_vmovp_cmd.vpe->vpe_db_lpi); in its_build_vmovp_cmd()
874 return valid_vpe(its, desc->its_vmovp_cmd.vpe); in its_build_vmovp_cmd()
877 static struct its_vpe *its_build_vinv_cmd(struct its_node *its, in its_build_vinv_cmd() argument
883 map = dev_event_to_vlpi_map(desc->its_inv_cmd.dev, in its_build_vinv_cmd()
884 desc->its_inv_cmd.event_id); in its_build_vinv_cmd()
887 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); in its_build_vinv_cmd()
888 its_encode_event_id(cmd, desc->its_inv_cmd.event_id); in its_build_vinv_cmd()
892 return valid_vpe(its, map->vpe); in its_build_vinv_cmd()
895 static struct its_vpe *its_build_vint_cmd(struct its_node *its, in its_build_vint_cmd() argument
901 map = dev_event_to_vlpi_map(desc->its_int_cmd.dev, in its_build_vint_cmd()
902 desc->its_int_cmd.event_id); in its_build_vint_cmd()
905 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id); in its_build_vint_cmd()
906 its_encode_event_id(cmd, desc->its_int_cmd.event_id); in its_build_vint_cmd()
910 return valid_vpe(its, map->vpe); in its_build_vint_cmd()
913 static struct its_vpe *its_build_vclear_cmd(struct its_node *its, in its_build_vclear_cmd() argument
919 map = dev_event_to_vlpi_map(desc->its_clear_cmd.dev, in its_build_vclear_cmd()
920 desc->its_clear_cmd.event_id); in its_build_vclear_cmd()
923 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id); in its_build_vclear_cmd()
924 its_encode_event_id(cmd, desc->its_clear_cmd.event_id); in its_build_vclear_cmd()
928 return valid_vpe(its, map->vpe); in its_build_vclear_cmd()
931 static struct its_vpe *its_build_invdb_cmd(struct its_node *its, in its_build_invdb_cmd() argument
935 if (WARN_ON(!is_v4_1(its))) in its_build_invdb_cmd()
939 its_encode_vpeid(cmd, desc->its_invdb_cmd.vpe->vpe_id); in its_build_invdb_cmd()
943 return valid_vpe(its, desc->its_invdb_cmd.vpe); in its_build_invdb_cmd()
946 static struct its_vpe *its_build_vsgi_cmd(struct its_node *its, in its_build_vsgi_cmd() argument
950 if (WARN_ON(!is_v4_1(its))) in its_build_vsgi_cmd()
954 its_encode_vpeid(cmd, desc->its_vsgi_cmd.vpe->vpe_id); in its_build_vsgi_cmd()
955 its_encode_sgi_intid(cmd, desc->its_vsgi_cmd.sgi); in its_build_vsgi_cmd()
956 its_encode_sgi_priority(cmd, desc->its_vsgi_cmd.priority); in its_build_vsgi_cmd()
957 its_encode_sgi_group(cmd, desc->its_vsgi_cmd.group); in its_build_vsgi_cmd()
958 its_encode_sgi_clear(cmd, desc->its_vsgi_cmd.clear); in its_build_vsgi_cmd()
959 its_encode_sgi_enable(cmd, desc->its_vsgi_cmd.enable); in its_build_vsgi_cmd()
963 return valid_vpe(its, desc->its_vsgi_cmd.vpe); in its_build_vsgi_cmd()
966 static u64 its_cmd_ptr_to_offset(struct its_node *its, in its_cmd_ptr_to_offset() argument
969 return (ptr - its->cmd_base) * sizeof(*ptr); in its_cmd_ptr_to_offset()
972 static int its_queue_full(struct its_node *its) in its_queue_full() argument
977 widx = its->cmd_write - its->cmd_base; in its_queue_full()
978 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block); in its_queue_full()
980 /* This is incredibly unlikely to happen, unless the ITS locks up. */ in its_queue_full()
987 static struct its_cmd_block *its_allocate_entry(struct its_node *its) in its_allocate_entry() argument
992 while (its_queue_full(its)) { in its_allocate_entry()
993 count--; in its_allocate_entry()
995 pr_err_ratelimited("ITS queue not draining\n"); in its_allocate_entry()
1002 cmd = its->cmd_write++; in its_allocate_entry()
1005 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES)) in its_allocate_entry()
1006 its->cmd_write = its->cmd_base; in its_allocate_entry()
1009 cmd->raw_cmd[0] = 0; in its_allocate_entry()
1010 cmd->raw_cmd[1] = 0; in its_allocate_entry()
1011 cmd->raw_cmd[2] = 0; in its_allocate_entry()
1012 cmd->raw_cmd[3] = 0; in its_allocate_entry()
1017 static struct its_cmd_block *its_post_commands(struct its_node *its) in its_post_commands() argument
1019 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write); in its_post_commands()
1021 writel_relaxed(wr, its->base + GITS_CWRITER); in its_post_commands()
1023 return its->cmd_write; in its_post_commands()
1026 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd) in its_flush_cmd() argument
1030 * the ITS. in its_flush_cmd()
1032 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING) in its_flush_cmd()
1038 static int its_wait_for_range_completion(struct its_node *its, in its_wait_for_range_completion() argument
1046 to_idx = its_cmd_ptr_to_offset(its, to); in its_wait_for_range_completion()
1055 rd_idx = readl_relaxed(its->base + GITS_CREADR); in its_wait_for_range_completion()
1059 * potential wrap-around into account. in its_wait_for_range_completion()
1061 delta = rd_idx - prev_idx; in its_wait_for_range_completion()
1069 count--; in its_wait_for_range_completion()
1071 pr_err_ratelimited("ITS queue timeout (%llu %llu)\n", in its_wait_for_range_completion()
1073 return -1; in its_wait_for_range_completion()
1085 void name(struct its_node *its, \
1094 raw_spin_lock_irqsave(&its->lock, flags); \
1096 cmd = its_allocate_entry(its); \
1098 raw_spin_unlock_irqrestore(&its->lock, flags); \
1101 sync_obj = builder(its, cmd, desc); \
1102 its_flush_cmd(its, cmd); \
1105 sync_cmd = its_allocate_entry(its); \
1109 buildfn(its, sync_cmd, sync_obj); \
1110 its_flush_cmd(its, sync_cmd); \
1114 rd_idx = readl_relaxed(its->base + GITS_CREADR); \
1115 next_cmd = its_post_commands(its); \
1116 raw_spin_unlock_irqrestore(&its->lock, flags); \
1118 if (its_wait_for_range_completion(its, rd_idx, next_cmd)) \
1119 pr_err_ratelimited("ITS cmd %ps failed\n", builder); \
1122 static void its_build_sync_cmd(struct its_node *its, in its_build_sync_cmd() argument
1127 its_encode_target(sync_cmd, sync_col->target_address); in its_build_sync_cmd()
1135 static void its_build_vsync_cmd(struct its_node *its, in BUILD_SINGLE_CMD_FUNC()
1140 its_encode_vpeid(sync_cmd, sync_vpe->vpe_id); in BUILD_SINGLE_CMD_FUNC()
1155 its_send_single_command(dev->its, its_build_int_cmd, &desc); in BUILD_SINGLE_CMD_FUNC()
1165 its_send_single_command(dev->its, its_build_clear_cmd, &desc); in its_send_clear()
1175 its_send_single_command(dev->its, its_build_inv_cmd, &desc); in its_send_inv()
1185 its_send_single_command(dev->its, its_build_mapd_cmd, &desc); in its_send_mapd()
1188 static void its_send_mapc(struct its_node *its, struct its_collection *col, in its_send_mapc() argument
1196 its_send_single_command(its, its_build_mapc_cmd, &desc); in its_send_mapc()
1207 its_send_single_command(dev->its, its_build_mapti_cmd, &desc); in its_send_mapti()
1219 its_send_single_command(dev->its, its_build_movi_cmd, &desc); in its_send_movi()
1229 its_send_single_command(dev->its, its_build_discard_cmd, &desc); in its_send_discard()
1232 static void its_send_invall(struct its_node *its, struct its_collection *col) in its_send_invall() argument
1238 its_send_single_command(its, its_build_invall_cmd, &desc); in its_send_invall()
1246 desc.its_vmapti_cmd.vpe = map->vpe; in its_send_vmapti()
1248 desc.its_vmapti_cmd.virt_id = map->vintid; in its_send_vmapti()
1250 desc.its_vmapti_cmd.db_enabled = map->db_enabled; in its_send_vmapti()
1252 its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc); in its_send_vmapti()
1260 desc.its_vmovi_cmd.vpe = map->vpe; in its_send_vmovi()
1263 desc.its_vmovi_cmd.db_enabled = map->db_enabled; in its_send_vmovi()
1265 its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc); in its_send_vmovi()
1268 static void its_send_vmapp(struct its_node *its, in its_send_vmapp() argument
1275 desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx]; in its_send_vmapp()
1277 its_send_single_vcommand(its, its_build_vmapp_cmd, &desc); in its_send_vmapp()
1283 struct its_node *its; in its_send_vmovp() local
1285 int col_id = vpe->col_idx; in its_send_vmovp()
1290 its = list_first_entry(&its_nodes, struct its_node, entry); in its_send_vmovp()
1291 desc.its_vmovp_cmd.col = &its->collections[col_id]; in its_send_vmovp()
1292 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc); in its_send_vmovp()
1302 * Wall <-- Head. in its_send_vmovp()
1307 desc.its_vmovp_cmd.its_list = get_its_list(vpe->its_vm); in its_send_vmovp()
1310 list_for_each_entry(its, &its_nodes, entry) { in its_send_vmovp()
1311 if (!is_v4(its)) in its_send_vmovp()
1314 if (!require_its_list_vmovp(vpe->its_vm, its)) in its_send_vmovp()
1317 desc.its_vmovp_cmd.col = &its->collections[col_id]; in its_send_vmovp()
1318 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc); in its_send_vmovp()
1324 static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe) in its_send_vinvall() argument
1329 its_send_single_vcommand(its, its_build_vinvall_cmd, &desc); in its_send_vinvall()
1343 its_send_single_vcommand(dev->its, its_build_vinv_cmd, &desc); in its_send_vinv()
1357 its_send_single_vcommand(dev->its, its_build_vint_cmd, &desc); in its_send_vint()
1371 its_send_single_vcommand(dev->its, its_build_vclear_cmd, &desc); in its_send_vclear()
1374 static void its_send_invdb(struct its_node *its, struct its_vpe *vpe) in its_send_invdb() argument
1379 its_send_single_vcommand(its, its_build_invdb_cmd, &desc); in its_send_invdb()
1383 * irqchip functions - assumes MSI, mostly.
1393 va = page_address(map->vm->vprop_page); in lpi_write_config()
1394 hwirq = map->vintid; in lpi_write_config()
1397 map->properties &= ~clr; in lpi_write_config()
1398 map->properties |= set | LPI_PROP_GROUP1; in lpi_write_config()
1400 va = gic_rdists->prop_table_va; in lpi_write_config()
1401 hwirq = d->hwirq; in lpi_write_config()
1404 cfg = va + hwirq - 8192; in lpi_write_config()
1413 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING) in lpi_write_config()
1436 WARN_ON(!is_v4_1(its_dev->its)); in direct_lpi_inv()
1439 val |= FIELD_PREP(GICR_INVLPIR_VPEID, map->vpe->vpe_id); in direct_lpi_inv()
1440 val |= FIELD_PREP(GICR_INVLPIR_INTID, map->vintid); in direct_lpi_inv()
1442 val = d->hwirq; in direct_lpi_inv()
1447 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock); in direct_lpi_inv()
1448 rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base; in direct_lpi_inv()
1452 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock); in direct_lpi_inv()
1461 if (gic_rdists->has_direct_lpi && in lpi_update_config()
1462 (is_v4_1(its_dev->its) || !irqd_is_forwarded_to_vcpu(d))) in lpi_update_config()
1477 * GICv4.1 does away with the per-LPI nonsense, nothing to do in its_vlpi_set_doorbell()
1480 if (is_v4_1(its_dev->its)) in its_vlpi_set_doorbell()
1485 if (map->db_enabled == enable) in its_vlpi_set_doorbell()
1488 map->db_enabled = enable; in its_vlpi_set_doorbell()
1493 * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI in its_vlpi_set_doorbell()
1522 return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed); in its_read_lpi_count()
1524 return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged); in its_read_lpi_count()
1530 atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed); in its_inc_lpi_count()
1532 atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged); in its_inc_lpi_count()
1538 atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed); in its_dec_lpi_count()
1540 atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged); in its_dec_lpi_count()
1572 return -ENOMEM; in its_select_cpu()
1574 node = its_dev->its->numa_node; in its_select_cpu()
1593 * ITS placed next to two NUMA nodes. in its_select_cpu()
1603 if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144)) in its_select_cpu()
1621 if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) && in its_select_cpu()
1630 pr_debug("IRQ%d -> %*pbl CPU%d\n", d->irq, cpumask_pr_args(aff_mask), cpu); in its_select_cpu()
1644 return -EINVAL; in its_set_affinity()
1646 prev_cpu = its_dev->event_map.col_map[id]; in its_set_affinity()
1659 target_col = &its_dev->its->collections[cpu]; in its_set_affinity()
1661 its_dev->event_map.col_map[id] = cpu; in its_set_affinity()
1671 return -EINVAL; in its_set_affinity()
1676 struct its_node *its = its_dev->its; in its_irq_get_msi_base() local
1678 return its->phys_base + GITS_TRANSLATER; in its_irq_get_msi_base()
1684 struct its_node *its; in its_irq_compose_msi_msg() local
1687 its = its_dev->its; in its_irq_compose_msi_msg()
1688 addr = its->get_msi_base(its_dev); in its_irq_compose_msi_msg()
1690 msg->address_lo = lower_32_bits(addr); in its_irq_compose_msi_msg()
1691 msg->address_hi = upper_32_bits(addr); in its_irq_compose_msi_msg()
1692 msg->data = its_get_event_id(d); in its_irq_compose_msi_msg()
1705 return -EINVAL; in its_irq_set_irqchip_state()
1741 if (!its_list_map || gic_rdists->has_rvpeid) in gic_requires_eager_mapping()
1747 static void its_map_vm(struct its_node *its, struct its_vm *vm) in its_map_vm() argument
1760 vm->vlpi_count[its->list_nr]++; in its_map_vm()
1762 if (vm->vlpi_count[its->list_nr] == 1) { in its_map_vm()
1765 for (i = 0; i < vm->nr_vpes; i++) { in its_map_vm()
1766 struct its_vpe *vpe = vm->vpes[i]; in its_map_vm()
1767 struct irq_data *d = irq_get_irq_data(vpe->irq); in its_map_vm()
1770 vpe->col_idx = cpumask_first(cpu_online_mask); in its_map_vm()
1771 its_send_vmapp(its, vpe, true); in its_map_vm()
1772 its_send_vinvall(its, vpe); in its_map_vm()
1773 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx)); in its_map_vm()
1780 static void its_unmap_vm(struct its_node *its, struct its_vm *vm) in its_unmap_vm() argument
1784 /* Not using the ITS list? Everything is always mapped. */ in its_unmap_vm()
1790 if (!--vm->vlpi_count[its->list_nr]) { in its_unmap_vm()
1793 for (i = 0; i < vm->nr_vpes; i++) in its_unmap_vm()
1794 its_send_vmapp(its, vm->vpes[i], false); in its_unmap_vm()
1806 if (!info->map) in its_vlpi_map()
1807 return -EINVAL; in its_vlpi_map()
1809 raw_spin_lock(&its_dev->event_map.vlpi_lock); in its_vlpi_map()
1811 if (!its_dev->event_map.vm) { in its_vlpi_map()
1814 maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps), in its_vlpi_map()
1817 ret = -ENOMEM; in its_vlpi_map()
1821 its_dev->event_map.vm = info->map->vm; in its_vlpi_map()
1822 its_dev->event_map.vlpi_maps = maps; in its_vlpi_map()
1823 } else if (its_dev->event_map.vm != info->map->vm) { in its_vlpi_map()
1824 ret = -EINVAL; in its_vlpi_map()
1829 its_dev->event_map.vlpi_maps[event] = *info->map; in its_vlpi_map()
1835 /* Ensure all the VPEs are mapped on this ITS */ in its_vlpi_map()
1836 its_map_vm(its_dev->its, info->map->vm); in its_vlpi_map()
1845 lpi_write_config(d, 0xff, info->map->properties); in its_vlpi_map()
1854 its_dev->event_map.nr_vlpis++; in its_vlpi_map()
1858 raw_spin_unlock(&its_dev->event_map.vlpi_lock); in its_vlpi_map()
1868 raw_spin_lock(&its_dev->event_map.vlpi_lock); in its_vlpi_get()
1872 if (!its_dev->event_map.vm || !map) { in its_vlpi_get()
1873 ret = -EINVAL; in its_vlpi_get()
1878 *info->map = *map; in its_vlpi_get()
1881 raw_spin_unlock(&its_dev->event_map.vlpi_lock); in its_vlpi_get()
1891 raw_spin_lock(&its_dev->event_map.vlpi_lock); in its_vlpi_unmap()
1893 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) { in its_vlpi_unmap()
1894 ret = -EINVAL; in its_vlpi_unmap()
1903 its_send_mapti(its_dev, d->hwirq, event); in its_vlpi_unmap()
1908 /* Potentially unmap the VM from this ITS */ in its_vlpi_unmap()
1909 its_unmap_vm(its_dev->its, its_dev->event_map.vm); in its_vlpi_unmap()
1915 if (!--its_dev->event_map.nr_vlpis) { in its_vlpi_unmap()
1916 its_dev->event_map.vm = NULL; in its_vlpi_unmap()
1917 kfree(its_dev->event_map.vlpi_maps); in its_vlpi_unmap()
1921 raw_spin_unlock(&its_dev->event_map.vlpi_lock); in its_vlpi_unmap()
1929 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) in its_vlpi_prop_update()
1930 return -EINVAL; in its_vlpi_prop_update()
1932 if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI) in its_vlpi_prop_update()
1933 lpi_update_config(d, 0xff, info->config); in its_vlpi_prop_update()
1935 lpi_write_config(d, 0xff, info->config); in its_vlpi_prop_update()
1936 its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED)); in its_vlpi_prop_update()
1946 /* Need a v4 ITS */ in its_irq_set_vcpu_affinity()
1947 if (!is_v4(its_dev->its)) in its_irq_set_vcpu_affinity()
1948 return -EINVAL; in its_irq_set_vcpu_affinity()
1954 switch (info->cmd_type) { in its_irq_set_vcpu_affinity()
1966 return -EINVAL; in its_irq_set_vcpu_affinity()
1971 .name = "ITS",
2015 range->base_id = base; in mk_lpi_range()
2016 range->span = span; in mk_lpi_range()
2025 int err = -ENOSPC; in alloc_lpi_range()
2030 if (range->span >= nr_lpis) { in alloc_lpi_range()
2031 *base = range->base_id; in alloc_lpi_range()
2032 range->base_id += nr_lpis; in alloc_lpi_range()
2033 range->span -= nr_lpis; in alloc_lpi_range()
2035 if (range->span == 0) { in alloc_lpi_range()
2036 list_del(&range->entry); in alloc_lpi_range()
2047 pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis); in alloc_lpi_range()
2053 if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list) in merge_lpi_ranges()
2055 if (a->base_id + a->span != b->base_id) in merge_lpi_ranges()
2057 b->base_id = a->base_id; in merge_lpi_ranges()
2058 b->span += a->span; in merge_lpi_ranges()
2059 list_del(&a->entry); in merge_lpi_ranges()
2069 return -ENOMEM; in free_lpi_range()
2074 if (old->base_id < base) in free_lpi_range()
2078 * old is the last element with ->base_id smaller than base, in free_lpi_range()
2080 * ->base_id smaller than base, &old->entry ends up pointing in free_lpi_range()
2084 list_add(&new->entry, &old->entry); in free_lpi_range()
2098 u32 lpis = (1UL << id_bits) - 8192; in its_lpi_init()
2102 numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer); in its_lpi_init()
2106 pr_info("ITS: Using hypervisor restricted LPI range [%u]\n", in its_lpi_init()
2115 pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis); in its_lpi_init()
2133 err = -ENOSPC; in its_lpi_alloc()
2159 /* Priority 0xa0, Group-1, disabled */ in gic_reset_prop_table()
2198 addr_end = addr + size - 1; in gic_check_reserved_range()
2222 if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) { in its_setup_lpi_prop_table()
2228 gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12); in its_setup_lpi_prop_table()
2229 gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa, in its_setup_lpi_prop_table()
2232 gic_reset_prop_table(gic_rdists->prop_table_va); in its_setup_lpi_prop_table()
2237 GICD_TYPER_ID_BITS(gic_rdists->gicd_typer), in its_setup_lpi_prop_table()
2242 return -ENOMEM; in its_setup_lpi_prop_table()
2245 gic_rdists->prop_table_pa = page_to_phys(page); in its_setup_lpi_prop_table()
2246 gic_rdists->prop_table_va = page_address(page); in its_setup_lpi_prop_table()
2247 WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa, in its_setup_lpi_prop_table()
2252 &gic_rdists->prop_table_pa); in its_setup_lpi_prop_table()
2267 static u64 its_read_baser(struct its_node *its, struct its_baser *baser) in its_read_baser() argument
2269 u32 idx = baser - its->tables; in its_read_baser()
2271 return gits_read_baser(its->base + GITS_BASER + (idx << 3)); in its_read_baser()
2274 static void its_write_baser(struct its_node *its, struct its_baser *baser, in its_write_baser() argument
2277 u32 idx = baser - its->tables; in its_write_baser()
2279 gits_write_baser(val, its->base + GITS_BASER + (idx << 3)); in its_write_baser()
2280 baser->val = its_read_baser(its, baser); in its_write_baser()
2283 static int its_setup_baser(struct its_node *its, struct its_baser *baser, in its_setup_baser() argument
2286 u64 val = its_read_baser(its, baser); in its_setup_baser()
2294 psz = baser->psz; in its_setup_baser()
2297 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n", in its_setup_baser()
2298 &its->phys_base, its_base_type_string[type], in its_setup_baser()
2304 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order); in its_setup_baser()
2306 return -ENOMEM; in its_setup_baser()
2316 pr_err("ITS: no 52bit PA support when psz=%d\n", psz); in its_setup_baser()
2318 return -ENXIO; in its_setup_baser()
2328 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | in its_setup_baser()
2329 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) | in its_setup_baser()
2348 its_write_baser(its, baser, val); in its_setup_baser()
2349 tmp = baser->val; in its_setup_baser()
2357 * non-cacheable as well. in its_setup_baser()
2368 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n", in its_setup_baser()
2369 &its->phys_base, its_base_type_string[type], in its_setup_baser()
2372 return -ENXIO; in its_setup_baser()
2375 baser->order = order; in its_setup_baser()
2376 baser->base = base; in its_setup_baser()
2377 baser->psz = psz; in its_setup_baser()
2380 pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n", in its_setup_baser()
2381 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp), in its_setup_baser()
2390 static bool its_parse_indirect_baser(struct its_node *its, in its_parse_indirect_baser() argument
2394 u64 tmp = its_read_baser(its, baser); in its_parse_indirect_baser()
2399 u32 psz = baser->psz; in its_parse_indirect_baser()
2405 * Find out whether hw supports a single or two-level table by in its_parse_indirect_baser()
2408 its_write_baser(its, baser, val | GITS_BASER_INDIRECT); in its_parse_indirect_baser()
2409 indirect = !!(baser->val & GITS_BASER_INDIRECT); in its_parse_indirect_baser()
2413 * The size of the lvl2 table is equal to ITS page size in its_parse_indirect_baser()
2416 * which is reported by ITS hardware times lvl1 table in its_parse_indirect_baser()
2419 ids -= ilog2(psz / (int)esz); in its_parse_indirect_baser()
2426 * range of device IDs that the ITS can grok... The ID in its_parse_indirect_baser()
2428 * massive waste of memory if two-level device table in its_parse_indirect_baser()
2433 new_order = MAX_ORDER - 1; in its_parse_indirect_baser()
2435 pr_warn("ITS@%pa: %s Table too large, reduce ids %llu->%u\n", in its_parse_indirect_baser()
2436 &its->phys_base, its_base_type_string[type], in its_parse_indirect_baser()
2437 device_ids(its), ids); in its_parse_indirect_baser()
2455 static u32 compute_its_aff(struct its_node *its) in compute_its_aff() argument
2461 * Reencode the ITS SVPET and MPIDR as a GICR_TYPER, and compute in compute_its_aff()
2465 svpet = FIELD_GET(GITS_TYPER_SVPET, its->typer); in compute_its_aff()
2467 val |= FIELD_PREP(GICR_TYPER_AFFINITY, its->mpidr); in compute_its_aff()
2473 struct its_node *its; in find_sibling_its() local
2476 if (!FIELD_GET(GITS_TYPER_SVPET, cur_its->typer)) in find_sibling_its()
2481 list_for_each_entry(its, &its_nodes, entry) { in find_sibling_its()
2484 if (!is_v4_1(its) || its == cur_its) in find_sibling_its()
2487 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer)) in find_sibling_its()
2490 if (aff != compute_its_aff(its)) in find_sibling_its()
2494 baser = its->tables[2].val; in find_sibling_its()
2498 return its; in find_sibling_its()
2504 static void its_free_tables(struct its_node *its) in its_free_tables() argument
2509 if (its->tables[i].base) { in its_free_tables()
2510 free_pages((unsigned long)its->tables[i].base, in its_free_tables()
2511 its->tables[i].order); in its_free_tables()
2512 its->tables[i].base = NULL; in its_free_tables()
2517 static int its_probe_baser_psz(struct its_node *its, struct its_baser *baser) in its_probe_baser_psz() argument
2524 val = its_read_baser(its, baser); in its_probe_baser_psz()
2543 its_write_baser(its, baser, val); in its_probe_baser_psz()
2545 if (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser->val) == gpsz) in its_probe_baser_psz()
2557 return -1; in its_probe_baser_psz()
2561 baser->psz = psz; in its_probe_baser_psz()
2565 static int its_alloc_tables(struct its_node *its) in its_alloc_tables() argument
2571 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) in its_alloc_tables()
2576 struct its_baser *baser = its->tables + i; in its_alloc_tables()
2577 u64 val = its_read_baser(its, baser); in its_alloc_tables()
2585 if (its_probe_baser_psz(its, baser)) { in its_alloc_tables()
2586 its_free_tables(its); in its_alloc_tables()
2587 return -ENXIO; in its_alloc_tables()
2590 order = get_order(baser->psz); in its_alloc_tables()
2594 indirect = its_parse_indirect_baser(its, baser, &order, in its_alloc_tables()
2595 device_ids(its)); in its_alloc_tables()
2599 if (is_v4_1(its)) { in its_alloc_tables()
2603 if ((sibling = find_sibling_its(its))) { in its_alloc_tables()
2604 *baser = sibling->tables[2]; in its_alloc_tables()
2605 its_write_baser(its, baser, baser->val); in its_alloc_tables()
2610 indirect = its_parse_indirect_baser(its, baser, &order, in its_alloc_tables()
2615 err = its_setup_baser(its, baser, cache, shr, order, indirect); in its_alloc_tables()
2617 its_free_tables(its); in its_alloc_tables()
2622 cache = baser->val & GITS_BASER_CACHEABILITY_MASK; in its_alloc_tables()
2623 shr = baser->val & GITS_BASER_SHAREABILITY_MASK; in its_alloc_tables()
2631 struct its_node *its; in inherit_vpe_l1_table_from_its() local
2638 list_for_each_entry(its, &its_nodes, entry) { in inherit_vpe_l1_table_from_its()
2641 if (!is_v4_1(its)) in inherit_vpe_l1_table_from_its()
2644 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer)) in inherit_vpe_l1_table_from_its()
2647 if (aff != compute_its_aff(its)) in inherit_vpe_l1_table_from_its()
2651 baser = its->tables[2].val; in inherit_vpe_l1_table_from_its()
2656 gic_data_rdist()->vpe_l1_base = its->tables[2].base; in inherit_vpe_l1_table_from_its()
2676 val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, GITS_BASER_NR_PAGES(baser) - 1); in inherit_vpe_l1_table_from_its()
2694 void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base; in inherit_vpe_l1_table_from_rd()
2706 * ours wrt CommonLPIAff. Let's use its own VPROPBASER. in inherit_vpe_l1_table_from_rd()
2712 gic_data_rdist()->vpe_l1_base = gic_data_rdist_cpu(cpu)->vpe_l1_base; in inherit_vpe_l1_table_from_rd()
2713 *mask = gic_data_rdist_cpu(cpu)->vpe_table_mask; in inherit_vpe_l1_table_from_rd()
2723 void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base; in allocate_vpe_l2_table()
2729 if (!gic_rdists->has_rvpeid) in allocate_vpe_l2_table()
2732 /* Skip non-present CPUs */ in allocate_vpe_l2_table()
2766 table = gic_data_rdist_cpu(cpu)->vpe_l1_base; in allocate_vpe_l2_table()
2799 if (!gic_rdists->has_rvpeid) in allocate_vpe_l1_table()
2818 val = inherit_vpe_l1_table_from_rd(&gic_data_rdist()->vpe_table_mask); in allocate_vpe_l1_table()
2822 gic_data_rdist()->vpe_table_mask = kzalloc(sizeof(cpumask_t), GFP_ATOMIC); in allocate_vpe_l1_table()
2823 if (!gic_data_rdist()->vpe_table_mask) in allocate_vpe_l1_table()
2824 return -ENOMEM; in allocate_vpe_l1_table()
2882 val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, npg - 1); in allocate_vpe_l1_table()
2891 return -ENOMEM; in allocate_vpe_l1_table()
2893 gic_data_rdist()->vpe_l1_base = page_address(page); in allocate_vpe_l1_table()
2905 cpumask_set_cpu(smp_processor_id(), gic_data_rdist()->vpe_table_mask); in allocate_vpe_l1_table()
2909 cpumask_pr_args(gic_data_rdist()->vpe_table_mask)); in allocate_vpe_l1_table()
2914 static int its_alloc_collections(struct its_node *its) in its_alloc_collections() argument
2918 its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections), in its_alloc_collections()
2920 if (!its->collections) in its_alloc_collections()
2921 return -ENOMEM; in its_alloc_collections()
2924 its->collections[i].target_address = ~0ULL; in its_alloc_collections()
2938 /* Make sure the GIC will observe the zero-ed page */ in its_allocate_pending_table()
2972 * flag the RD tables as pre-allocated if the stars do align. in allocate_lpi_tables()
2976 gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED | in allocate_lpi_tables()
2996 return -ENOMEM; in allocate_lpi_tables()
2999 gic_data_rdist_cpu(cpu)->pend_page = pend_page; in allocate_lpi_tables()
3021 count--; in its_clear_vpend_valid()
3028 pr_err_ratelimited("ITS virtual pending table not cleaning\n"); in its_clear_vpend_valid()
3042 if (gic_data_rdist()->lpi_enabled) in its_cpu_init_lpis()
3046 if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) && in its_cpu_init_lpis()
3054 if (WARN_ON(gic_rdists->prop_table_pa != paddr)) in its_cpu_init_lpis()
3061 its_free_pending_table(gic_data_rdist()->pend_page); in its_cpu_init_lpis()
3062 gic_data_rdist()->pend_page = NULL; in its_cpu_init_lpis()
3067 pend_page = gic_data_rdist()->pend_page; in its_cpu_init_lpis()
3072 val = (gic_rdists->prop_table_pa | in its_cpu_init_lpis()
3075 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK)); in its_cpu_init_lpis()
3083 * The HW reports non-shareable, we must in its_cpu_init_lpis()
3093 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING; in its_cpu_init_lpis()
3106 * The HW reports non-shareable, we must remove the in its_cpu_init_lpis()
3120 if (gic_rdists->has_vlpis && !gic_rdists->has_rvpeid) { in its_cpu_init_lpis()
3130 val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK; in its_cpu_init_lpis()
3149 gic_rdists->has_rvpeid = false; in its_cpu_init_lpis()
3150 gic_rdists->has_vlpis = false; in its_cpu_init_lpis()
3156 gic_data_rdist()->lpi_enabled = true; in its_cpu_init_lpis()
3159 gic_data_rdist()->pend_page ? "allocated" : "reserved", in its_cpu_init_lpis()
3163 static void its_cpu_init_collection(struct its_node *its) in its_cpu_init_collection() argument
3168 /* avoid cross node collections and its mapping */ in its_cpu_init_collection()
3169 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { in its_cpu_init_collection()
3173 if (its->numa_node != NUMA_NO_NODE && in its_cpu_init_collection()
3174 its->numa_node != of_node_to_nid(cpu_node)) in its_cpu_init_collection()
3179 * We now have to bind each collection to its target in its_cpu_init_collection()
3182 if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) { in its_cpu_init_collection()
3184 * This ITS wants the physical address of the in its_cpu_init_collection()
3187 target = gic_data_rdist()->phys_base; in its_cpu_init_collection()
3189 /* This ITS wants a linear CPU number. */ in its_cpu_init_collection()
3195 its->collections[cpu].target_address = target; in its_cpu_init_collection()
3196 its->collections[cpu].col_id = cpu; in its_cpu_init_collection()
3198 its_send_mapc(its, &its->collections[cpu], 1); in its_cpu_init_collection()
3199 its_send_invall(its, &its->collections[cpu]); in its_cpu_init_collection()
3204 struct its_node *its; in its_cpu_init_collections() local
3208 list_for_each_entry(its, &its_nodes, entry) in its_cpu_init_collections()
3209 its_cpu_init_collection(its); in its_cpu_init_collections()
3214 static struct its_device *its_find_device(struct its_node *its, u32 dev_id) in its_find_device() argument
3219 raw_spin_lock_irqsave(&its->lock, flags); in its_find_device()
3221 list_for_each_entry(tmp, &its->its_device_list, entry) { in its_find_device()
3222 if (tmp->device_id == dev_id) { in its_find_device()
3228 raw_spin_unlock_irqrestore(&its->lock, flags); in its_find_device()
3233 static struct its_baser *its_get_baser(struct its_node *its, u32 type) in its_get_baser() argument
3238 if (GITS_BASER_TYPE(its->tables[i].val) == type) in its_get_baser()
3239 return &its->tables[i]; in its_get_baser()
3245 static bool its_alloc_table_entry(struct its_node *its, in its_alloc_table_entry() argument
3253 esz = GITS_BASER_ENTRY_SIZE(baser->val); in its_alloc_table_entry()
3254 if (!(baser->val & GITS_BASER_INDIRECT)) in its_alloc_table_entry()
3255 return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz)); in its_alloc_table_entry()
3258 idx = id >> ilog2(baser->psz / esz); in its_alloc_table_entry()
3259 if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE)) in its_alloc_table_entry()
3262 table = baser->base; in its_alloc_table_entry()
3266 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, in its_alloc_table_entry()
3267 get_order(baser->psz)); in its_alloc_table_entry()
3272 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) in its_alloc_table_entry()
3273 gic_flush_dcache_to_poc(page_address(page), baser->psz); in its_alloc_table_entry()
3278 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) in its_alloc_table_entry()
3281 /* Ensure updated table contents are visible to ITS hardware */ in its_alloc_table_entry()
3288 static bool its_alloc_device_table(struct its_node *its, u32 dev_id) in its_alloc_device_table() argument
3292 baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE); in its_alloc_device_table()
3294 /* Don't allow device id that exceeds ITS hardware limit */ in its_alloc_device_table()
3296 return (ilog2(dev_id) < device_ids(its)); in its_alloc_device_table()
3298 return its_alloc_table_entry(its, baser, dev_id); in its_alloc_device_table()
3303 struct its_node *its; in its_alloc_vpe_table() local
3313 list_for_each_entry(its, &its_nodes, entry) { in its_alloc_vpe_table()
3316 if (!is_v4(its)) in its_alloc_vpe_table()
3319 baser = its_get_baser(its, GITS_BASER_TYPE_VCPU); in its_alloc_vpe_table()
3323 if (!its_alloc_table_entry(its, baser, vpe_id)) in its_alloc_vpe_table()
3328 if (!gic_rdists->has_rvpeid) in its_alloc_vpe_table()
3343 static struct its_device *its_create_device(struct its_node *its, u32 dev_id, in its_create_device() argument
3356 if (!its_alloc_device_table(its, dev_id)) in its_create_device()
3368 sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1); in its_create_device()
3369 sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; in its_create_device()
3370 itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node); in its_create_device()
3392 dev->its = its; in its_create_device()
3393 dev->itt = itt; in its_create_device()
3394 dev->nr_ites = nr_ites; in its_create_device()
3395 dev->event_map.lpi_map = lpi_map; in its_create_device()
3396 dev->event_map.col_map = col_map; in its_create_device()
3397 dev->event_map.lpi_base = lpi_base; in its_create_device()
3398 dev->event_map.nr_lpis = nr_lpis; in its_create_device()
3399 raw_spin_lock_init(&dev->event_map.vlpi_lock); in its_create_device()
3400 dev->device_id = dev_id; in its_create_device()
3401 INIT_LIST_HEAD(&dev->entry); in its_create_device()
3403 raw_spin_lock_irqsave(&its->lock, flags); in its_create_device()
3404 list_add(&dev->entry, &its->its_device_list); in its_create_device()
3405 raw_spin_unlock_irqrestore(&its->lock, flags); in its_create_device()
3407 /* Map device to its ITT */ in its_create_device()
3417 raw_spin_lock_irqsave(&its_dev->its->lock, flags); in its_free_device()
3418 list_del(&its_dev->entry); in its_free_device()
3419 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); in its_free_device()
3420 kfree(its_dev->event_map.col_map); in its_free_device()
3421 kfree(its_dev->itt); in its_free_device()
3430 idx = bitmap_find_free_region(dev->event_map.lpi_map, in its_alloc_device_irq()
3431 dev->event_map.nr_lpis, in its_alloc_device_irq()
3434 return -ENOSPC; in its_alloc_device_irq()
3436 *hwirq = dev->event_map.lpi_base + idx; in its_alloc_device_irq()
3444 struct its_node *its; in its_msi_prepare() local
3454 * are built on top of the ITS. in its_msi_prepare()
3456 dev_id = info->scratchpad[0].ul; in its_msi_prepare()
3459 its = msi_info->data; in its_msi_prepare()
3461 if (!gic_rdists->has_direct_lpi && in its_msi_prepare()
3463 vpe_proxy.dev->its == its && in its_msi_prepare()
3464 dev_id == vpe_proxy.dev->device_id) { in its_msi_prepare()
3468 return -EINVAL; in its_msi_prepare()
3471 mutex_lock(&its->dev_alloc_lock); in its_msi_prepare()
3472 its_dev = its_find_device(its, dev_id); in its_msi_prepare()
3479 its_dev->shared = true; in its_msi_prepare()
3484 its_dev = its_create_device(its, dev_id, nvec, true); in its_msi_prepare()
3486 err = -ENOMEM; in its_msi_prepare()
3492 mutex_unlock(&its->dev_alloc_lock); in its_msi_prepare()
3493 info->scratchpad[0].ptr = its_dev; in its_msi_prepare()
3507 if (irq_domain_get_of_node(domain->parent)) { in its_irq_gic_domain_alloc()
3508 fwspec.fwnode = domain->parent->fwnode; in its_irq_gic_domain_alloc()
3513 } else if (is_fwnode_irqchip(domain->parent->fwnode)) { in its_irq_gic_domain_alloc()
3514 fwspec.fwnode = domain->parent->fwnode; in its_irq_gic_domain_alloc()
3519 return -EINVAL; in its_irq_gic_domain_alloc()
3529 struct its_device *its_dev = info->scratchpad[0].ptr; in its_irq_domain_alloc()
3530 struct its_node *its = its_dev->its; in its_irq_domain_alloc() local
3540 err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev)); in its_irq_domain_alloc()
3555 (int)(hwirq + i - its_dev->event_map.lpi_base), in its_irq_domain_alloc()
3571 return -EINVAL; in its_irq_domain_activate()
3574 its_dev->event_map.col_map[event] = cpu; in its_irq_domain_activate()
3578 its_send_mapti(its_dev, d->hwirq, event); in its_irq_domain_activate()
3588 its_dec_lpi_count(d, its_dev->event_map.col_map[event]); in its_irq_domain_deactivate()
3598 struct its_node *its = its_dev->its; in its_irq_domain_free() local
3601 bitmap_release_region(its_dev->event_map.lpi_map, in its_irq_domain_free()
3612 mutex_lock(&its->dev_alloc_lock); in its_irq_domain_free()
3618 if (!its_dev->shared && in its_irq_domain_free()
3619 bitmap_empty(its_dev->event_map.lpi_map, in its_irq_domain_free()
3620 its_dev->event_map.nr_lpis)) { in its_irq_domain_free()
3621 its_lpi_free(its_dev->event_map.lpi_map, in its_irq_domain_free()
3622 its_dev->event_map.lpi_base, in its_irq_domain_free()
3623 its_dev->event_map.nr_lpis); in its_irq_domain_free()
3630 mutex_unlock(&its->dev_alloc_lock); in its_irq_domain_free()
3664 if (gic_rdists->has_rvpeid) in its_vpe_db_proxy_unmap_locked()
3668 if (vpe->vpe_proxy_event == -1) in its_vpe_db_proxy_unmap_locked()
3671 its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event); in its_vpe_db_proxy_unmap_locked()
3672 vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL; in its_vpe_db_proxy_unmap_locked()
3682 vpe_proxy.next_victim = vpe->vpe_proxy_event; in its_vpe_db_proxy_unmap_locked()
3684 vpe->vpe_proxy_event = -1; in its_vpe_db_proxy_unmap_locked()
3690 if (gic_rdists->has_rvpeid) in its_vpe_db_proxy_unmap()
3693 if (!gic_rdists->has_direct_lpi) { in its_vpe_db_proxy_unmap()
3705 if (gic_rdists->has_rvpeid) in its_vpe_db_proxy_map_locked()
3709 if (vpe->vpe_proxy_event != -1) in its_vpe_db_proxy_map_locked()
3718 vpe->vpe_proxy_event = vpe_proxy.next_victim; in its_vpe_db_proxy_map_locked()
3719 vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites; in its_vpe_db_proxy_map_locked()
3721 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx; in its_vpe_db_proxy_map_locked()
3722 its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event); in its_vpe_db_proxy_map_locked()
3731 if (gic_rdists->has_rvpeid) in its_vpe_db_proxy_move()
3734 if (gic_rdists->has_direct_lpi) { in its_vpe_db_proxy_move()
3737 rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base; in its_vpe_db_proxy_move()
3738 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR); in its_vpe_db_proxy_move()
3748 target_col = &vpe_proxy.dev->its->collections[to]; in its_vpe_db_proxy_move()
3749 its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event); in its_vpe_db_proxy_move()
3750 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to; in its_vpe_db_proxy_move()
3767 * interrupt to its new location. in its_vpe_set_affinity()
3772 * protect us, and that we must ensure nobody samples vpe->col_idx in its_vpe_set_affinity()
3774 * taken on any vLPI handling path that evaluates vpe->col_idx. in its_vpe_set_affinity()
3780 vpe->col_idx = cpu; in its_vpe_set_affinity()
3784 * is sharing its VPE table with the current one. in its_vpe_set_affinity()
3786 if (gic_data_rdist_cpu(cpu)->vpe_table_mask && in its_vpe_set_affinity()
3787 cpumask_test_cpu(from, gic_data_rdist_cpu(cpu)->vpe_table_mask)) in its_vpe_set_affinity()
3805 if (!gic_rdists->has_vpend_valid_dirty) in its_wait_vpt_parse_complete()
3820 val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) & in its_vpe_schedule()
3822 val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK; in its_vpe_schedule()
3827 val = virt_to_phys(page_address(vpe->vpt_page)) & in its_vpe_schedule()
3834 * easily. So in the end, vpe->pending_last is only an in its_vpe_schedule()
3837 * would be able to read its coarse map pretty quickly anyway, in its_vpe_schedule()
3841 val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0; in its_vpe_schedule()
3855 vpe->idai = !!(val & GICR_VPENDBASER_IDAI); in its_vpe_deschedule()
3856 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast); in its_vpe_deschedule()
3861 struct its_node *its; in its_vpe_invall() local
3863 list_for_each_entry(its, &its_nodes, entry) { in its_vpe_invall()
3864 if (!is_v4(its)) in its_vpe_invall()
3867 if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr]) in its_vpe_invall()
3871 * Sending a VINVALL to a single ITS is enough, as all in its_vpe_invall()
3874 its_send_vinvall(its, vpe); in its_vpe_invall()
3884 switch (info->cmd_type) { in its_vpe_set_vcpu_affinity()
3898 return -EINVAL; in its_vpe_set_vcpu_affinity()
3910 cmd(vpe_proxy.dev, vpe->vpe_proxy_event); in its_vpe_send_cmd()
3919 if (gic_rdists->has_direct_lpi) { in its_vpe_send_inv()
3923 raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); in its_vpe_send_inv()
3924 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; in its_vpe_send_inv()
3925 gic_write_lpir(d->parent_data->hwirq, rdbase + GICR_INVLPIR); in its_vpe_send_inv()
3927 raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); in its_vpe_send_inv()
3941 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0); in its_vpe_mask_irq()
3948 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED); in its_vpe_unmask_irq()
3959 return -EINVAL; in its_vpe_set_irqchip_state()
3961 if (gic_rdists->has_direct_lpi) { in its_vpe_set_irqchip_state()
3964 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; in its_vpe_set_irqchip_state()
3966 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR); in its_vpe_set_irqchip_state()
3968 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR); in its_vpe_set_irqchip_state()
3987 .name = "GICv4-vpe",
3999 static struct its_node *its = NULL; in find_4_1_its() local
4001 if (!its) { in find_4_1_its()
4002 list_for_each_entry(its, &its_nodes, entry) { in find_4_1_its()
4003 if (is_v4_1(its)) in find_4_1_its()
4004 return its; in find_4_1_its()
4008 its = NULL; in find_4_1_its()
4011 return its; in find_4_1_its()
4017 struct its_node *its; in its_vpe_4_1_send_inv() local
4022 * it to the first valid ITS, and let the HW do its magic. in its_vpe_4_1_send_inv()
4024 its = find_4_1_its(); in its_vpe_4_1_send_inv()
4025 if (its) in its_vpe_4_1_send_inv()
4026 its_send_invdb(its, vpe); in its_vpe_4_1_send_inv()
4031 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0); in its_vpe_4_1_mask_irq()
4037 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED); in its_vpe_4_1_unmask_irq()
4049 val |= info->g0en ? GICR_VPENDBASER_4_1_VGRP0EN : 0; in its_vpe_4_1_schedule()
4050 val |= info->g1en ? GICR_VPENDBASER_4_1_VGRP1EN : 0; in its_vpe_4_1_schedule()
4051 val |= FIELD_PREP(GICR_VPENDBASER_4_1_VPEID, vpe->vpe_id); in its_vpe_4_1_schedule()
4064 if (info->req_db) { in its_vpe_4_1_deschedule()
4068 * vPE is going to block: make the vPE non-resident with in its_vpe_4_1_deschedule()
4070 * we read-back PendingLast clear, then a doorbell will be in its_vpe_4_1_deschedule()
4077 raw_spin_lock_irqsave(&vpe->vpe_lock, flags); in its_vpe_4_1_deschedule()
4081 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast); in its_vpe_4_1_deschedule()
4082 raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags); in its_vpe_4_1_deschedule()
4085 * We're not blocking, so just make the vPE non-resident in its_vpe_4_1_deschedule()
4091 vpe->pending_last = true; in its_vpe_4_1_deschedule()
4103 val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id); in its_vpe_4_1_invall()
4107 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock); in its_vpe_4_1_invall()
4108 rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base; in its_vpe_4_1_invall()
4112 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock); in its_vpe_4_1_invall()
4121 switch (info->cmd_type) { in its_vpe_4_1_set_vcpu_affinity()
4135 return -EINVAL; in its_vpe_4_1_set_vcpu_affinity()
4140 .name = "GICv4.1-vpe",
4154 desc.its_vsgi_cmd.sgi = d->hwirq; in its_configure_sgi()
4155 desc.its_vsgi_cmd.priority = vpe->sgi_config[d->hwirq].priority; in its_configure_sgi()
4156 desc.its_vsgi_cmd.enable = vpe->sgi_config[d->hwirq].enabled; in its_configure_sgi()
4157 desc.its_vsgi_cmd.group = vpe->sgi_config[d->hwirq].group; in its_configure_sgi()
4161 * GICv4.1 allows us to send VSGI commands to any ITS as long as the in its_configure_sgi()
4163 * activation time, we're pretty sure the first GICv4.1 ITS will do. in its_configure_sgi()
4172 vpe->sgi_config[d->hwirq].enabled = false; in its_sgi_mask_irq()
4180 vpe->sgi_config[d->hwirq].enabled = true; in its_sgi_unmask_irq()
4202 return -EINVAL; in its_sgi_set_irqchip_state()
4206 struct its_node *its = find_4_1_its(); in its_sgi_set_irqchip_state() local
4209 val = FIELD_PREP(GITS_SGIR_VPEID, vpe->vpe_id); in its_sgi_set_irqchip_state()
4210 val |= FIELD_PREP(GITS_SGIR_VINTID, d->hwirq); in its_sgi_set_irqchip_state()
4211 writeq_relaxed(val, its->sgir_base + GITS_SGIR - SZ_128K); in its_sgi_set_irqchip_state()
4230 return -EINVAL; in its_sgi_get_irqchip_state()
4235 * - Concurent vPE affinity change: we must make sure it cannot in its_sgi_get_irqchip_state()
4239 * - Concurrent VSGIPENDR access: As it involves accessing two in its_sgi_get_irqchip_state()
4243 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock); in its_sgi_get_irqchip_state()
4244 base = gic_data_rdist_cpu(cpu)->rd_base + SZ_128K; in its_sgi_get_irqchip_state()
4245 writel_relaxed(vpe->vpe_id, base + GICR_VSGIR); in its_sgi_get_irqchip_state()
4251 count--; in its_sgi_get_irqchip_state()
4261 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock); in its_sgi_get_irqchip_state()
4265 return -ENXIO; in its_sgi_get_irqchip_state()
4267 *val = !!(status & (1 << d->hwirq)); in its_sgi_get_irqchip_state()
4277 switch (info->cmd_type) { in its_sgi_set_vcpu_affinity()
4279 vpe->sgi_config[d->hwirq].priority = info->priority; in its_sgi_set_vcpu_affinity()
4280 vpe->sgi_config[d->hwirq].group = info->group; in its_sgi_set_vcpu_affinity()
4285 return -EINVAL; in its_sgi_set_vcpu_affinity()
4290 .name = "GICv4.1-sgi",
4310 vpe->sgi_config[i].priority = 0; in its_sgi_irq_domain_alloc()
4311 vpe->sgi_config[i].enabled = false; in its_sgi_irq_domain_alloc()
4312 vpe->sgi_config[i].group = false; in its_sgi_irq_domain_alloc()
4345 * - To change the configuration, CLEAR must be set to false, in its_sgi_irq_domain_deactivate()
4347 * - To clear the pending bit, CLEAR must be set to true, leaving in its_sgi_irq_domain_deactivate()
4352 vpe->sgi_config[d->hwirq].enabled = false; in its_sgi_irq_domain_deactivate()
4388 return -ENOMEM; in its_vpe_init()
4394 return -ENOMEM; in its_vpe_init()
4397 raw_spin_lock_init(&vpe->vpe_lock); in its_vpe_init()
4398 vpe->vpe_id = vpe_id; in its_vpe_init()
4399 vpe->vpt_page = vpt_page; in its_vpe_init()
4400 if (gic_rdists->has_rvpeid) in its_vpe_init()
4401 atomic_set(&vpe->vmapp_count, 0); in its_vpe_init()
4403 vpe->vpe_proxy_event = -1; in its_vpe_init()
4411 its_vpe_id_free(vpe->vpe_id); in its_vpe_teardown()
4412 its_free_pending_table(vpe->vpt_page); in its_vpe_teardown()
4419 struct its_vm *vm = domain->host_data; in its_vpe_irq_domain_free()
4429 BUG_ON(vm != vpe->its_vm); in its_vpe_irq_domain_free()
4431 clear_bit(data->hwirq, vm->db_bitmap); in its_vpe_irq_domain_free()
4436 if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) { in its_vpe_irq_domain_free()
4437 its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis); in its_vpe_irq_domain_free()
4438 its_free_prop_table(vm->vprop_page); in its_vpe_irq_domain_free()
4455 return -ENOMEM; in its_vpe_irq_domain_alloc()
4459 return -ENOMEM; in its_vpe_irq_domain_alloc()
4465 return -ENOMEM; in its_vpe_irq_domain_alloc()
4468 vm->db_bitmap = bitmap; in its_vpe_irq_domain_alloc()
4469 vm->db_lpi_base = base; in its_vpe_irq_domain_alloc()
4470 vm->nr_db_lpis = nr_ids; in its_vpe_irq_domain_alloc()
4471 vm->vprop_page = vprop_page; in its_vpe_irq_domain_alloc()
4473 if (gic_rdists->has_rvpeid) in its_vpe_irq_domain_alloc()
4477 vm->vpes[i]->vpe_db_lpi = base + i; in its_vpe_irq_domain_alloc()
4478 err = its_vpe_init(vm->vpes[i]); in its_vpe_irq_domain_alloc()
4482 vm->vpes[i]->vpe_db_lpi); in its_vpe_irq_domain_alloc()
4486 irqchip, vm->vpes[i]); in its_vpe_irq_domain_alloc()
4492 its_vpe_irq_domain_free(domain, virq, i - 1); in its_vpe_irq_domain_alloc()
4505 struct its_node *its; in its_vpe_irq_domain_activate() local
4516 vpe->col_idx = cpumask_first(cpu_online_mask); in its_vpe_irq_domain_activate()
4518 list_for_each_entry(its, &its_nodes, entry) { in its_vpe_irq_domain_activate()
4519 if (!is_v4(its)) in its_vpe_irq_domain_activate()
4522 its_send_vmapp(its, vpe, true); in its_vpe_irq_domain_activate()
4523 its_send_vinvall(its, vpe); in its_vpe_irq_domain_activate()
4526 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx)); in its_vpe_irq_domain_activate()
4535 struct its_node *its; in its_vpe_irq_domain_deactivate() local
4544 list_for_each_entry(its, &its_nodes, entry) { in its_vpe_irq_domain_deactivate()
4545 if (!is_v4(its)) in its_vpe_irq_domain_deactivate()
4548 its_send_vmapp(its, vpe, false); in its_vpe_irq_domain_deactivate()
4566 * GIC architecture specification requires the ITS to be both in its_force_quiescent()
4573 /* Disable the generation of all interrupts to this ITS */ in its_force_quiescent()
4577 /* Poll GITS_CTLR and wait until ITS becomes quiescent */ in its_force_quiescent()
4583 count--; in its_force_quiescent()
4585 return -EBUSY; in its_force_quiescent()
4594 struct its_node *its = data; in its_enable_quirk_cavium_22375() local
4597 its->typer &= ~GITS_TYPER_DEVBITS; in its_enable_quirk_cavium_22375()
4598 its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, 20 - 1); in its_enable_quirk_cavium_22375()
4599 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375; in its_enable_quirk_cavium_22375()
4606 struct its_node *its = data; in its_enable_quirk_cavium_23144() local
4608 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144; in its_enable_quirk_cavium_23144()
4615 struct its_node *its = data; in its_enable_quirk_qdf2400_e0065() local
4618 its->typer &= ~GITS_TYPER_ITT_ENTRY_SIZE; in its_enable_quirk_qdf2400_e0065()
4619 its->typer |= FIELD_PREP(GITS_TYPER_ITT_ENTRY_SIZE, 16 - 1); in its_enable_quirk_qdf2400_e0065()
4626 struct its_node *its = its_dev->its; in its_irq_get_msi_base_pre_its() local
4629 * The Socionext Synquacer SoC has a so-called 'pre-ITS', in its_irq_get_msi_base_pre_its()
4630 * which maps 32-bit writes targeted at a separate window of in its_irq_get_msi_base_pre_its()
4635 return its->pre_its_base + (its_dev->device_id << 2); in its_irq_get_msi_base_pre_its()
4640 struct its_node *its = data; in its_enable_quirk_socionext_synquacer() local
4644 if (!fwnode_property_read_u32_array(its->fwnode_handle, in its_enable_quirk_socionext_synquacer()
4645 "socionext,synquacer-pre-its", in its_enable_quirk_socionext_synquacer()
4649 its->pre_its_base = pre_its_window[0]; in its_enable_quirk_socionext_synquacer()
4650 its->get_msi_base = its_irq_get_msi_base_pre_its; in its_enable_quirk_socionext_synquacer()
4652 ids = ilog2(pre_its_window[1]) - 2; in its_enable_quirk_socionext_synquacer()
4653 if (device_ids(its) > ids) { in its_enable_quirk_socionext_synquacer()
4654 its->typer &= ~GITS_TYPER_DEVBITS; in its_enable_quirk_socionext_synquacer()
4655 its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, ids - 1); in its_enable_quirk_socionext_synquacer()
4658 /* the pre-ITS breaks isolation, so disable MSI remapping */ in its_enable_quirk_socionext_synquacer()
4659 its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP; in its_enable_quirk_socionext_synquacer()
4667 struct its_node *its = data; in its_enable_quirk_hip07_161600802() local
4673 its->vlpi_redist_offset = SZ_128K; in its_enable_quirk_hip07_161600802()
4680 .desc = "ITS: Cavium errata 22375, 24313",
4688 .desc = "ITS: Cavium erratum 23144",
4696 .desc = "ITS: QDF2400 erratum 0065",
4697 .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */
4705 * The Socionext Synquacer SoC incorporates ARM's own GIC-500
4706 * implementation, but with a 'pre-ITS' added that requires
4709 .desc = "ITS: Socionext Synquacer pre-ITS",
4717 .desc = "ITS: Hip07 erratum 161600802",
4727 static void its_enable_quirks(struct its_node *its) in its_enable_quirks() argument
4729 u32 iidr = readl_relaxed(its->base + GITS_IIDR); in its_enable_quirks()
4731 gic_enable_quirks(iidr, its_quirks, its); in its_enable_quirks()
4736 struct its_node *its; in its_save_disable() local
4740 list_for_each_entry(its, &its_nodes, entry) { in its_save_disable()
4743 base = its->base; in its_save_disable()
4744 its->ctlr_save = readl_relaxed(base + GITS_CTLR); in its_save_disable()
4747 pr_err("ITS@%pa: failed to quiesce: %d\n", in its_save_disable()
4748 &its->phys_base, err); in its_save_disable()
4749 writel_relaxed(its->ctlr_save, base + GITS_CTLR); in its_save_disable()
4753 its->cbaser_save = gits_read_cbaser(base + GITS_CBASER); in its_save_disable()
4758 list_for_each_entry_continue_reverse(its, &its_nodes, entry) { in its_save_disable()
4761 base = its->base; in its_save_disable()
4762 writel_relaxed(its->ctlr_save, base + GITS_CTLR); in its_save_disable()
4772 struct its_node *its; in its_restore_enable() local
4776 list_for_each_entry(its, &its_nodes, entry) { in its_restore_enable()
4780 base = its->base; in its_restore_enable()
4783 * Make sure that the ITS is disabled. If it fails to quiesce, in its_restore_enable()
4785 * registers is undefined according to the GIC v3 ITS in its_restore_enable()
4788 * Firmware resuming with the ITS enabled is terminally broken. in its_restore_enable()
4793 pr_err("ITS@%pa: failed to quiesce on resume: %d\n", in its_restore_enable()
4794 &its->phys_base, ret); in its_restore_enable()
4798 gits_write_cbaser(its->cbaser_save, base + GITS_CBASER); in its_restore_enable()
4804 its->cmd_write = its->cmd_base; in its_restore_enable()
4809 struct its_baser *baser = &its->tables[i]; in its_restore_enable()
4811 if (!(baser->val & GITS_BASER_VALID)) in its_restore_enable()
4814 its_write_baser(its, baser, baser->val); in its_restore_enable()
4816 writel_relaxed(its->ctlr_save, base + GITS_CTLR); in its_restore_enable()
4819 * Reinit the collection if it's stored in the ITS. This is in its_restore_enable()
4823 if (its->collections[smp_processor_id()].col_id < in its_restore_enable()
4825 its_cpu_init_collection(its); in its_restore_enable()
4835 static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) in its_init_domain() argument
4842 return -ENOMEM; in its_init_domain()
4844 inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its); in its_init_domain()
4847 return -ENOMEM; in its_init_domain()
4850 inner_domain->parent = its_parent; in its_init_domain()
4852 inner_domain->flags |= its->msi_domain_flags; in its_init_domain()
4853 info->ops = &its_msi_domain_ops; in its_init_domain()
4854 info->data = its; in its_init_domain()
4855 inner_domain->host_data = info; in its_init_domain()
4862 struct its_node *its; in its_init_vpe_domain() local
4866 if (gic_rdists->has_direct_lpi) { in its_init_vpe_domain()
4867 pr_info("ITS: Using DirectLPI for VPE invalidation\n"); in its_init_vpe_domain()
4871 /* Any ITS will do, even if not v4 */ in its_init_vpe_domain()
4872 its = list_first_entry(&its_nodes, struct its_node, entry); in its_init_vpe_domain()
4878 pr_err("ITS: Can't allocate GICv4 proxy device array\n"); in its_init_vpe_domain()
4879 return -ENOMEM; in its_init_vpe_domain()
4883 devid = GENMASK(device_ids(its) - 1, 0); in its_init_vpe_domain()
4884 vpe_proxy.dev = its_create_device(its, devid, entries, false); in its_init_vpe_domain()
4887 pr_err("ITS: Can't allocate GICv4 proxy device\n"); in its_init_vpe_domain()
4888 return -ENOMEM; in its_init_vpe_domain()
4891 BUG_ON(entries > vpe_proxy.dev->nr_ites); in its_init_vpe_domain()
4895 pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n", in its_init_vpe_domain()
4896 devid, vpe_proxy.dev->nr_ites); in its_init_vpe_domain()
4909 * guaranteed to be single-threaded, hence no in its_compute_its_list_map()
4915 pr_err("ITS@%pa: No ITSList entry available!\n", in its_compute_its_list_map()
4916 &res->start); in its_compute_its_list_map()
4917 return -EINVAL; in its_compute_its_list_map()
4931 pr_err("ITS@%pa: Duplicate ITSList entry %d\n", in its_compute_its_list_map()
4932 &res->start, its_number); in its_compute_its_list_map()
4933 return -EINVAL; in its_compute_its_list_map()
4942 struct its_node *its; in its_probe_one() local
4949 its_base = ioremap(res->start, SZ_64K); in its_probe_one()
4951 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start); in its_probe_one()
4952 return -ENOMEM; in its_probe_one()
4957 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start); in its_probe_one()
4958 err = -ENODEV; in its_probe_one()
4964 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start); in its_probe_one()
4968 pr_info("ITS %pR\n", res); in its_probe_one()
4970 its = kzalloc(sizeof(*its), GFP_KERNEL); in its_probe_one()
4971 if (!its) { in its_probe_one()
4972 err = -ENOMEM; in its_probe_one()
4976 raw_spin_lock_init(&its->lock); in its_probe_one()
4977 mutex_init(&its->dev_alloc_lock); in its_probe_one()
4978 INIT_LIST_HEAD(&its->entry); in its_probe_one()
4979 INIT_LIST_HEAD(&its->its_device_list); in its_probe_one()
4981 its->typer = typer; in its_probe_one()
4982 its->base = its_base; in its_probe_one()
4983 its->phys_base = res->start; in its_probe_one()
4984 if (is_v4(its)) { in its_probe_one()
4990 its->list_nr = err; in its_probe_one()
4992 pr_info("ITS@%pa: Using ITS number %d\n", in its_probe_one()
4993 &res->start, err); in its_probe_one()
4995 pr_info("ITS@%pa: Single VMOVP capable\n", &res->start); in its_probe_one()
4998 if (is_v4_1(its)) { in its_probe_one()
5001 its->sgir_base = ioremap(res->start + SZ_128K, SZ_64K); in its_probe_one()
5002 if (!its->sgir_base) { in its_probe_one()
5003 err = -ENOMEM; in its_probe_one()
5007 its->mpidr = readl_relaxed(its_base + GITS_MPIDR); in its_probe_one()
5009 pr_info("ITS@%pa: Using GICv4.1 mode %08x %08x\n", in its_probe_one()
5010 &res->start, its->mpidr, svpet); in its_probe_one()
5014 its->numa_node = numa_node; in its_probe_one()
5016 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, in its_probe_one()
5019 err = -ENOMEM; in its_probe_one()
5022 its->cmd_base = (void *)page_address(page); in its_probe_one()
5023 its->cmd_write = its->cmd_base; in its_probe_one()
5024 its->fwnode_handle = handle; in its_probe_one()
5025 its->get_msi_base = its_irq_get_msi_base; in its_probe_one()
5026 its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP; in its_probe_one()
5028 its_enable_quirks(its); in its_probe_one()
5030 err = its_alloc_tables(its); in its_probe_one()
5034 err = its_alloc_collections(its); in its_probe_one()
5038 baser = (virt_to_phys(its->cmd_base) | in its_probe_one()
5041 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) | in its_probe_one()
5044 gits_write_cbaser(baser, its->base + GITS_CBASER); in its_probe_one()
5045 tmp = gits_read_cbaser(its->base + GITS_CBASER); in its_probe_one()
5050 * The HW reports non-shareable, we must in its_probe_one()
5057 gits_write_cbaser(baser, its->base + GITS_CBASER); in its_probe_one()
5059 pr_info("ITS: using cache flushing for cmd queue\n"); in its_probe_one()
5060 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING; in its_probe_one()
5063 gits_write_cwriter(0, its->base + GITS_CWRITER); in its_probe_one()
5064 ctlr = readl_relaxed(its->base + GITS_CTLR); in its_probe_one()
5066 if (is_v4(its)) in its_probe_one()
5068 writel_relaxed(ctlr, its->base + GITS_CTLR); in its_probe_one()
5070 err = its_init_domain(handle, its); in its_probe_one()
5075 list_add(&its->entry, &its_nodes); in its_probe_one()
5081 its_free_tables(its); in its_probe_one()
5083 free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ)); in its_probe_one()
5085 if (its->sgir_base) in its_probe_one()
5086 iounmap(its->sgir_base); in its_probe_one()
5088 kfree(its); in its_probe_one()
5091 pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err); in its_probe_one()
5108 return -ENXIO; in redist_disable_lpis()
5117 * LPIs before trying to re-enable them. They are already in redist_disable_lpis()
5122 if (gic_data_rdist()->lpi_enabled || in redist_disable_lpis()
5123 (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED)) in redist_disable_lpis()
5149 return -ETIMEDOUT; in redist_disable_lpis()
5152 timeout--; in redist_disable_lpis()
5162 return -EBUSY; in redist_disable_lpis()
5185 { .compatible = "arm,gic-v3-its", },
5198 if (!of_property_read_bool(np, "msi-controller")) { in its_of_probe()
5199 pr_warn("%pOF: no msi-controller property, ITS ignored\n", in its_of_probe()
5209 its_probe_one(&res, &np->fwnode, of_node_to_nid(np)); in its_of_probe()
5222 /* GIC ITS ID */
5254 return -EINVAL; in gic_acpi_parse_srat_its()
5256 if (its_affinity->header.length < sizeof(*its_affinity)) { in gic_acpi_parse_srat_its()
5257 pr_err("SRAT: Invalid header length %d in ITS affinity\n", in gic_acpi_parse_srat_its()
5258 its_affinity->header.length); in gic_acpi_parse_srat_its()
5259 return -EINVAL; in gic_acpi_parse_srat_its()
5267 node = pxm_to_node(its_affinity->proximity_domain); in gic_acpi_parse_srat_its()
5270 pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node); in gic_acpi_parse_srat_its()
5275 its_srat_maps[its_in_srat].its_id = its_affinity->its_id; in gic_acpi_parse_srat_its()
5277 pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n", in gic_acpi_parse_srat_its()
5278 its_affinity->proximity_domain, its_affinity->its_id, node); in gic_acpi_parse_srat_its()
5307 /* free the its_srat_maps after ITS probing */
5328 res.start = its_entry->base_address; in gic_acpi_parse_madt_its()
5329 res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1; in gic_acpi_parse_madt_its()
5334 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n", in gic_acpi_parse_madt_its()
5336 return -ENOMEM; in gic_acpi_parse_madt_its()
5339 err = iort_register_domain_token(its_entry->translation_id, res.start, in gic_acpi_parse_madt_its()
5342 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", in gic_acpi_parse_madt_its()
5343 &res.start, its_entry->translation_id); in gic_acpi_parse_madt_its()
5348 acpi_get_its_numa_node(its_entry->translation_id)); in gic_acpi_parse_madt_its()
5352 iort_deregister_domain_token(its_entry->translation_id); in gic_acpi_parse_madt_its()
5373 struct its_node *its; in its_init() local
5388 pr_warn("ITS: No ITS available, not enabling LPIs\n"); in its_init()
5389 return -ENXIO; in its_init()
5396 list_for_each_entry(its, &its_nodes, entry) { in its_init()
5397 has_v4 |= is_v4(its); in its_init()
5398 has_v4_1 |= is_v4_1(its); in its_init()
5402 if (WARN_ON(!has_v4_1 && rdists->has_rvpeid)) in its_init()
5403 rdists->has_rvpeid = false; in its_init()
5405 if (has_v4 & rdists->has_vlpis) { in its_init()
5415 rdists->has_vlpis = false; in its_init()
5416 pr_err("ITS: Disabling GICv4 support\n"); in its_init()