7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
23 #include <linux/cpu.h>
40  *    To CPU 0                 To CPU 1
44  * +---------------+     +---------------+
46  * |    per-CPU    |	 |    per-CPU    |
50  * +---------------+	 +---------------+
55  *            +-------------------+
60  *            +-------------------+
71  * The "per-CPU mask/unmask" is modified using the
75  * which automatically accesses the registers of the current CPU.
77  * The per-CPU mask/unmask can also be adjusted using the global
78  * per-interrupt ARMADA_370_XP_INT_SOURCE_CTL register, which we use
82  * different levels: at the global level and at the per-CPU level.
86  *  - For global interrupts:
88  *    At ->map() time, a global interrupt is unmasked at the per-CPU
90  *    the current CPU, running the ->map() code. This allows to have
91  *    the interrupt unmasked at this level in non-SMP
92  *    configurations. In SMP configurations, the ->set_affinity()
94  *    ARMADA_370_XP_INT_SOURCE_CTL() readjusts the per-CPU mask/unmask
97  *    The ->mask() and ->unmask() operations only mask/unmask the
100  *    So, a global interrupt is enabled at the per-CPU level as soon
104  *  - For per-CPU interrupts
106  *    At ->map() time, a per-CPU interrupt is unmasked at the global
109  *    The ->mask() and ->unmask() operations mask/unmask the interrupt
110  *    at the per-CPU level.
112  *    So, a per-CPU interrupt is enabled at the global level as soon
114  *    at the per-CPU level.
134 #define ARMADA_370_XP_INT_CAUSE_PERF(cpu)	(1 << cpu)  argument
170  * For CPU interrupts, mask/unmask the calling CPU's bit
212 	msg->address_lo = lower_32_bits(msi_doorbell_addr);  in armada_370_xp_compose_msi_msg()
213 	msg->address_hi = upper_32_bits(msi_doorbell_addr);  in armada_370_xp_compose_msi_msg()
214 	msg->data = 0xf00 | (data->hwirq + PCI_MSI_DOORBELL_START);  in armada_370_xp_compose_msi_msg()
220 	 return -EINVAL;  in armada_370_xp_msi_set_affinity()
240 		return -ENOSPC;  in armada_370_xp_msi_alloc()
249 				    domain->host_data, handle_simple_irq,  in armada_370_xp_msi_alloc()
262 	bitmap_clear(msi_used, d->hwirq, nr_irqs);  in armada_370_xp_msi_free()
283 		return -ENOMEM;  in armada_370_xp_msi_init()
291 		return -ENOMEM;  in armada_370_xp_msi_init()
329 	reg &= ~BIT(d->hwirq);  in armada_370_xp_ipi_mask()
337 	reg |= BIT(d->hwirq);  in armada_370_xp_ipi_unmask()
345 	int cpu;  in armada_370_xp_ipi_send_mask()  local
347 	/* Convert our logical CPU mask into a physical one. */  in armada_370_xp_ipi_send_mask()
348 	for_each_cpu(cpu, mask)  in armada_370_xp_ipi_send_mask()
349 		map |= 1 << cpu_logical_map(cpu);  in armada_370_xp_ipi_send_mask()
358 	writel((map << 8) | d->hwirq, main_int_base +  in armada_370_xp_ipi_send_mask()
364 	writel(~BIT(d->hwirq), per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);  in armada_370_xp_ipi_eoi()
384 				    d->host_data,  in armada_370_xp_ipi_alloc()
433 	base_ipi = __irq_domain_alloc_irqs(ipi_domain, -1, IPI_DOORBELL_END,  in armada_xp_ipi_init()
448 	int cpu;  in armada_xp_set_affinity()  local
451 	cpu = cpumask_any_and(mask_val, cpu_online_mask);  in armada_xp_set_affinity()
452 	mask = 1UL << cpu_logical_map(cpu);  in armada_xp_set_affinity()
460 	irq_data_update_effective_affinity(d, cpumask_of(cpu));  in armada_xp_set_affinity()
490 	/* Re-enable per-CPU interrupts that were enabled before suspend */  in armada_xp_mpic_reenable_percpu()
510 static int armada_xp_mpic_starting_cpu(unsigned int cpu)  in armada_xp_mpic_starting_cpu()  argument
518 static int mpic_cascaded_starting_cpu(unsigned int cpu)  in mpic_cascaded_starting_cpu()  argument
592 					       msinr - PCI_MSI_DOORBELL_START);  in armada_370_xp_handle_msi_irq()
595 			irq = msinr - PCI_MSI_DOORBELL_START;  in armada_370_xp_handle_msi_irq()
620 		/* Check if the interrupt is not masked on current CPU.  in armada_370_xp_mpic_handle_cascade_irq()
621 		 * Test IRQ (0-1) and FIQ (8-9) mask bits.  in armada_370_xp_mpic_handle_cascade_irq()
691 	/* Re-enable interrupts */  in armada_370_xp_mpic_resume()
704 			/* Non per-CPU interrupts */  in armada_370_xp_mpic_resume()
710 			/* Per-CPU interrupts */  in armada_370_xp_mpic_resume()
715 			 * Re-enable on the current CPU,  in armada_370_xp_mpic_resume()
752 				   node->full_name));  in armada_370_xp_mpic_of_init()
755 				   node->full_name));  in armada_370_xp_mpic_of_init()
777 	/* Setup for the boot CPU */  in armada_370_xp_mpic_of_init()