Lines Matching +full:smmu +full:- +full:v1
1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for QCOM secure IOMMUs. Somewhat based on arm-smmu.c
13 #include <linux/dma-iommu.h>
14 #include <linux/dma-mapping.h>
18 #include <linux/io-64-nonatomic-hi-lo.h>
19 #include <linux/io-pgtable.h>
36 #include "arm-smmu.h"
57 struct qcom_iommu_ctx *ctxs[]; /* indexed by asid-1 */
88 if (!fwspec || fwspec->ops != &qcom_iommu_ops) in to_iommu()
96 struct qcom_iommu_dev *qcom_iommu = d->iommu; in to_ctx()
99 return qcom_iommu->ctxs[asid - 1]; in to_ctx()
105 writel_relaxed(val, ctx->base + reg); in iommu_writel()
111 writeq_relaxed(val, ctx->base + reg); in iommu_writeq()
117 return readl_relaxed(ctx->base + reg); in iommu_readl()
123 return readq_relaxed(ctx->base + reg); in iommu_readq()
129 struct iommu_fwspec *fwspec = qcom_domain->fwspec; in qcom_iommu_tlb_sync()
132 for (i = 0; i < fwspec->num_ids; i++) { in qcom_iommu_tlb_sync()
133 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); in qcom_iommu_tlb_sync()
138 ret = readl_poll_timeout(ctx->base + ARM_SMMU_CB_TLBSTATUS, val, in qcom_iommu_tlb_sync()
141 dev_err(ctx->dev, "timeout waiting for TLB SYNC\n"); in qcom_iommu_tlb_sync()
148 struct iommu_fwspec *fwspec = qcom_domain->fwspec; in qcom_iommu_tlb_inv_context()
151 for (i = 0; i < fwspec->num_ids; i++) { in qcom_iommu_tlb_inv_context()
152 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); in qcom_iommu_tlb_inv_context()
153 iommu_writel(ctx, ARM_SMMU_CB_S1_TLBIASID, ctx->asid); in qcom_iommu_tlb_inv_context()
163 struct iommu_fwspec *fwspec = qcom_domain->fwspec; in qcom_iommu_tlb_inv_range_nosync()
168 for (i = 0; i < fwspec->num_ids; i++) { in qcom_iommu_tlb_inv_range_nosync()
169 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); in qcom_iommu_tlb_inv_range_nosync()
173 iova |= ctx->asid; in qcom_iommu_tlb_inv_range_nosync()
177 } while (s -= granule); in qcom_iommu_tlb_inv_range_nosync()
223 if (!report_iommu_fault(ctx->domain, ctx->dev, iova, 0)) { in qcom_iommu_fault()
224 dev_err_ratelimited(ctx->dev, in qcom_iommu_fault()
227 fsr, iova, fsynr, ctx->asid); in qcom_iommu_fault()
247 mutex_lock(&qcom_domain->init_mutex); in qcom_iommu_init_domain()
248 if (qcom_domain->iommu) in qcom_iommu_init_domain()
256 .iommu_dev = qcom_iommu->dev, in qcom_iommu_init_domain()
259 qcom_domain->iommu = qcom_iommu; in qcom_iommu_init_domain()
260 qcom_domain->fwspec = fwspec; in qcom_iommu_init_domain()
264 dev_err(qcom_iommu->dev, "failed to allocate pagetable ops\n"); in qcom_iommu_init_domain()
265 ret = -ENOMEM; in qcom_iommu_init_domain()
270 domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap; in qcom_iommu_init_domain()
271 domain->geometry.aperture_end = (1ULL << pgtbl_cfg.ias) - 1; in qcom_iommu_init_domain()
272 domain->geometry.force_aperture = true; in qcom_iommu_init_domain()
274 for (i = 0; i < fwspec->num_ids; i++) { in qcom_iommu_init_domain()
275 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); in qcom_iommu_init_domain()
277 if (!ctx->secure_init) { in qcom_iommu_init_domain()
278 ret = qcom_scm_restore_sec_cfg(qcom_iommu->sec_id, ctx->asid); in qcom_iommu_init_domain()
280 dev_err(qcom_iommu->dev, "secure init failed: %d\n", ret); in qcom_iommu_init_domain()
283 ctx->secure_init = true; in qcom_iommu_init_domain()
289 FIELD_PREP(ARM_SMMU_TTBRn_ASID, ctx->asid)); in qcom_iommu_init_domain()
298 /* MAIRs (stage-1 only) */ in qcom_iommu_init_domain()
315 ctx->domain = domain; in qcom_iommu_init_domain()
318 mutex_unlock(&qcom_domain->init_mutex); in qcom_iommu_init_domain()
321 qcom_domain->pgtbl_ops = pgtbl_ops; in qcom_iommu_init_domain()
326 qcom_domain->iommu = NULL; in qcom_iommu_init_domain()
328 mutex_unlock(&qcom_domain->init_mutex); in qcom_iommu_init_domain()
348 iommu_get_dma_cookie(&qcom_domain->domain)) { in qcom_iommu_domain_alloc()
353 mutex_init(&qcom_domain->init_mutex); in qcom_iommu_domain_alloc()
354 spin_lock_init(&qcom_domain->pgtbl_lock); in qcom_iommu_domain_alloc()
356 return &qcom_domain->domain; in qcom_iommu_domain_alloc()
365 if (qcom_domain->iommu) { in qcom_iommu_domain_free()
368 * off, for example, with GPUs or anything involving dma-buf. in qcom_iommu_domain_free()
372 pm_runtime_get_sync(qcom_domain->iommu->dev); in qcom_iommu_domain_free()
373 free_io_pgtable_ops(qcom_domain->pgtbl_ops); in qcom_iommu_domain_free()
374 pm_runtime_put_sync(qcom_domain->iommu->dev); in qcom_iommu_domain_free()
388 return -ENXIO; in qcom_iommu_attach_dev()
392 pm_runtime_get_sync(qcom_iommu->dev); in qcom_iommu_attach_dev()
394 pm_runtime_put_sync(qcom_iommu->dev); in qcom_iommu_attach_dev()
402 if (qcom_domain->iommu != qcom_iommu) { in qcom_iommu_attach_dev()
405 dev_name(qcom_domain->iommu->dev), in qcom_iommu_attach_dev()
406 dev_name(qcom_iommu->dev)); in qcom_iommu_attach_dev()
407 return -EINVAL; in qcom_iommu_attach_dev()
420 if (WARN_ON(!qcom_domain->iommu)) in qcom_iommu_detach_dev()
423 pm_runtime_get_sync(qcom_iommu->dev); in qcom_iommu_detach_dev()
424 for (i = 0; i < fwspec->num_ids; i++) { in qcom_iommu_detach_dev()
425 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]); in qcom_iommu_detach_dev()
430 ctx->domain = NULL; in qcom_iommu_detach_dev()
432 pm_runtime_put_sync(qcom_iommu->dev); in qcom_iommu_detach_dev()
441 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops; in qcom_iommu_map()
444 return -ENODEV; in qcom_iommu_map()
446 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags); in qcom_iommu_map()
447 ret = ops->map(ops, iova, paddr, size, prot, GFP_ATOMIC); in qcom_iommu_map()
448 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags); in qcom_iommu_map()
458 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops; in qcom_iommu_unmap()
464 * for example, with GPUs or anything involving dma-buf. So we in qcom_iommu_unmap()
468 pm_runtime_get_sync(qcom_domain->iommu->dev); in qcom_iommu_unmap()
469 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags); in qcom_iommu_unmap()
470 ret = ops->unmap(ops, iova, size, gather); in qcom_iommu_unmap()
471 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags); in qcom_iommu_unmap()
472 pm_runtime_put_sync(qcom_domain->iommu->dev); in qcom_iommu_unmap()
480 struct io_pgtable *pgtable = container_of(qcom_domain->pgtbl_ops, in qcom_iommu_flush_iotlb_all()
482 if (!qcom_domain->pgtbl_ops) in qcom_iommu_flush_iotlb_all()
485 pm_runtime_get_sync(qcom_domain->iommu->dev); in qcom_iommu_flush_iotlb_all()
486 qcom_iommu_tlb_sync(pgtable->cookie); in qcom_iommu_flush_iotlb_all()
487 pm_runtime_put_sync(qcom_domain->iommu->dev); in qcom_iommu_flush_iotlb_all()
502 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops; in qcom_iommu_iova_to_phys()
507 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags); in qcom_iommu_iova_to_phys()
508 ret = ops->iova_to_phys(ops, iova); in qcom_iommu_iova_to_phys()
509 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags); in qcom_iommu_iova_to_phys()
519 * Return true here as the SMMU can always send out coherent in qcom_iommu_capable()
536 return ERR_PTR(-ENODEV); in qcom_iommu_probe_device()
543 link = device_link_add(dev, qcom_iommu->dev, DL_FLAG_PM_RUNTIME); in qcom_iommu_probe_device()
545 dev_err(qcom_iommu->dev, "Unable to create device link between %s and %s\n", in qcom_iommu_probe_device()
546 dev_name(qcom_iommu->dev), dev_name(dev)); in qcom_iommu_probe_device()
547 return ERR_PTR(-ENODEV); in qcom_iommu_probe_device()
550 return &qcom_iommu->iommu; in qcom_iommu_probe_device()
567 unsigned asid = args->args[0]; in qcom_iommu_of_xlate()
569 if (args->args_count != 1) { in qcom_iommu_of_xlate()
572 args->np->full_name, args->args_count); in qcom_iommu_of_xlate()
573 return -EINVAL; in qcom_iommu_of_xlate()
576 iommu_pdev = of_find_device_by_node(args->np); in qcom_iommu_of_xlate()
578 return -EINVAL; in qcom_iommu_of_xlate()
583 * to sanity check this elsewhere, since 'asid - 1' is used to in qcom_iommu_of_xlate()
584 * index into qcom_iommu->ctxs: in qcom_iommu_of_xlate()
587 WARN_ON(asid > qcom_iommu->num_ctxs)) { in qcom_iommu_of_xlate()
588 put_device(&iommu_pdev->dev); in qcom_iommu_of_xlate()
589 return -EINVAL; in qcom_iommu_of_xlate()
600 put_device(&iommu_pdev->dev); in qcom_iommu_of_xlate()
601 return -EINVAL; in qcom_iommu_of_xlate()
654 return -ENOMEM; in qcom_iommu_sec_ptbl_init()
679 return -ENODEV; in get_asid()
687 struct device *dev = &pdev->dev; in qcom_iommu_ctx_probe()
688 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev->parent); in qcom_iommu_ctx_probe()
694 return -ENOMEM; in qcom_iommu_ctx_probe()
696 ctx->dev = dev; in qcom_iommu_ctx_probe()
700 ctx->base = devm_ioremap_resource(dev, res); in qcom_iommu_ctx_probe()
701 if (IS_ERR(ctx->base)) in qcom_iommu_ctx_probe()
702 return PTR_ERR(ctx->base); in qcom_iommu_ctx_probe()
706 return -ENODEV; in qcom_iommu_ctx_probe()
709 * boot-loader left us a surprise: in qcom_iommu_ctx_probe()
716 "qcom-iommu-fault", in qcom_iommu_ctx_probe()
723 ret = get_asid(dev->of_node); in qcom_iommu_ctx_probe()
729 ctx->asid = ret; in qcom_iommu_ctx_probe()
731 dev_dbg(dev, "found asid %u\n", ctx->asid); in qcom_iommu_ctx_probe()
733 qcom_iommu->ctxs[ctx->asid - 1] = ctx; in qcom_iommu_ctx_probe()
740 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(pdev->dev.parent); in qcom_iommu_ctx_remove()
745 qcom_iommu->ctxs[ctx->asid - 1] = NULL; in qcom_iommu_ctx_remove()
751 { .compatible = "qcom,msm-iommu-v1-ns" },
752 { .compatible = "qcom,msm-iommu-v1-sec" },
758 .name = "qcom-iommu-ctx",
769 for_each_child_of_node(qcom_iommu->dev->of_node, child) in qcom_iommu_has_secure_context()
770 if (of_device_is_compatible(child, "qcom,msm-iommu-v1-sec")) in qcom_iommu_has_secure_context()
780 struct device *dev = &pdev->dev; in qcom_iommu_device_probe()
788 for_each_child_of_node(dev->of_node, child) in qcom_iommu_device_probe()
794 return -ENOMEM; in qcom_iommu_device_probe()
795 qcom_iommu->num_ctxs = max_asid; in qcom_iommu_device_probe()
796 qcom_iommu->dev = dev; in qcom_iommu_device_probe()
800 qcom_iommu->local_base = devm_ioremap_resource(dev, res); in qcom_iommu_device_probe()
801 if (IS_ERR(qcom_iommu->local_base)) in qcom_iommu_device_probe()
802 return PTR_ERR(qcom_iommu->local_base); in qcom_iommu_device_probe()
810 qcom_iommu->clks[CLK_IFACE].clk = clk; in qcom_iommu_device_probe()
817 qcom_iommu->clks[CLK_BUS].clk = clk; in qcom_iommu_device_probe()
824 qcom_iommu->clks[CLK_TBU].clk = clk; in qcom_iommu_device_probe()
826 if (of_property_read_u32(dev->of_node, "qcom,iommu-secure-id", in qcom_iommu_device_probe()
827 &qcom_iommu->sec_id)) { in qcom_iommu_device_probe()
828 dev_err(dev, "missing qcom,iommu-secure-id property\n"); in qcom_iommu_device_probe()
829 return -ENODEV; in qcom_iommu_device_probe()
851 ret = iommu_device_sysfs_add(&qcom_iommu->iommu, dev, NULL, in qcom_iommu_device_probe()
858 iommu_device_set_ops(&qcom_iommu->iommu, &qcom_iommu_ops); in qcom_iommu_device_probe()
859 iommu_device_set_fwnode(&qcom_iommu->iommu, dev->fwnode); in qcom_iommu_device_probe()
861 ret = iommu_device_register(&qcom_iommu->iommu); in qcom_iommu_device_probe()
869 if (qcom_iommu->local_base) { in qcom_iommu_device_probe()
871 writel_relaxed(0xffffffff, qcom_iommu->local_base + SMMU_INTR_SEL_NS); in qcom_iommu_device_probe()
884 pm_runtime_force_suspend(&pdev->dev); in qcom_iommu_device_remove()
886 iommu_device_sysfs_remove(&qcom_iommu->iommu); in qcom_iommu_device_remove()
887 iommu_device_unregister(&qcom_iommu->iommu); in qcom_iommu_device_remove()
896 return clk_bulk_prepare_enable(CLK_NUM, qcom_iommu->clks); in qcom_iommu_resume()
903 clk_bulk_disable_unprepare(CLK_NUM, qcom_iommu->clks); in qcom_iommu_suspend()
915 { .compatible = "qcom,msm-iommu-v1" },
921 .name = "qcom-iommu",