1 // SPDX-License-Identifier: GPL-2.0-only
2 // Miscellaneous Arm SMMU implementation and integration quirks
5 #define pr_fmt(fmt) "arm-smmu: " fmt
10 #include "arm-smmu.h"
28 static u32 arm_smmu_read_ns(struct arm_smmu_device *smmu, int page,  in arm_smmu_read_ns()  argument
33 	return readl_relaxed(arm_smmu_page(smmu, page) + offset);  in arm_smmu_read_ns()
36 static void arm_smmu_write_ns(struct arm_smmu_device *smmu, int page,  in arm_smmu_write_ns()  argument
41 	writel_relaxed(val, arm_smmu_page(smmu, page) + offset);  in arm_smmu_write_ns()
44 /* Since we don't care for sGFAR, we can do without 64-bit accessors */
52 	struct arm_smmu_device smmu;  member
56 static int cavium_cfg_probe(struct arm_smmu_device *smmu)  in cavium_cfg_probe()  argument
59 	struct cavium_smmu *cs = container_of(smmu, struct cavium_smmu, smmu);  in cavium_cfg_probe()
65 	cs->id_base = atomic_fetch_add(smmu->num_context_banks, &context_count);  in cavium_cfg_probe()
66 	dev_notice(smmu->dev, "\tenabling workaround for Cavium erratum 27704\n");  in cavium_cfg_probe()
74 	struct cavium_smmu *cs = container_of(smmu_domain->smmu,  in cavium_init_context()
75 					      struct cavium_smmu, smmu);  in cavium_init_context()
77 	if (smmu_domain->stage == ARM_SMMU_DOMAIN_S2)  in cavium_init_context()
78 		smmu_domain->cfg.vmid += cs->id_base;  in cavium_init_context()
80 		smmu_domain->cfg.asid += cs->id_base;  in cavium_init_context()
90 static struct arm_smmu_device *cavium_smmu_impl_init(struct arm_smmu_device *smmu)  in cavium_smmu_impl_init()  argument
94 	cs = devm_kzalloc(smmu->dev, sizeof(*cs), GFP_KERNEL);  in cavium_smmu_impl_init()
96 		return ERR_PTR(-ENOMEM);  in cavium_smmu_impl_init()
98 	cs->smmu = *smmu;  in cavium_smmu_impl_init()
99 	cs->smmu.impl = &cavium_impl;  in cavium_smmu_impl_init()
101 	devm_kfree(smmu->dev, smmu);  in cavium_smmu_impl_init()
103 	return &cs->smmu;  in cavium_smmu_impl_init()
113 int arm_mmu500_reset(struct arm_smmu_device *smmu)  in arm_mmu500_reset()  argument
118 	 * On MMU-500 r2p0 onwards we need to clear ACR.CACHE_LOCK before  in arm_mmu500_reset()
120 	 * Secure has also cleared SACR.CACHE_LOCK for this to take effect...  in arm_mmu500_reset()
122 	reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID7);  in arm_mmu500_reset()
124 	reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sACR);  in arm_mmu500_reset()
132 	arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sACR, reg);  in arm_mmu500_reset()
135 	 * Disable MMU-500's not-particularly-beneficial next-page  in arm_mmu500_reset()
138 	for (i = 0; i < smmu->num_context_banks; ++i) {  in arm_mmu500_reset()
139 		reg = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR);  in arm_mmu500_reset()
141 		arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, reg);  in arm_mmu500_reset()
151 static u64 mrvl_mmu500_readq(struct arm_smmu_device *smmu, int page, int off)  in mrvl_mmu500_readq()  argument
154 	 * Marvell Armada-AP806 erratum #582743.  in mrvl_mmu500_readq()
157 	return hi_lo_readq_relaxed(arm_smmu_page(smmu, page) + off);  in mrvl_mmu500_readq()
160 static void mrvl_mmu500_writeq(struct arm_smmu_device *smmu, int page, int off,  in mrvl_mmu500_writeq()  argument
164 	 * Marvell Armada-AP806 erratum #582743.  in mrvl_mmu500_writeq()
167 	hi_lo_writeq_relaxed(val, arm_smmu_page(smmu, page) + off);  in mrvl_mmu500_writeq()
170 static int mrvl_mmu500_cfg_probe(struct arm_smmu_device *smmu)  in mrvl_mmu500_cfg_probe()  argument
174 	 * Armada-AP806 erratum #582743.  in mrvl_mmu500_cfg_probe()
176 	 * formats altogether and allow using 32 bits access on the  in mrvl_mmu500_cfg_probe()
179 	smmu->features &= ~(ARM_SMMU_FEAT_FMT_AARCH64_4K |  in mrvl_mmu500_cfg_probe()
194 struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu)  in arm_smmu_impl_init()  argument
196 	const struct device_node *np = smmu->dev->of_node;  in arm_smmu_impl_init()
199 	 * Set the impl for model-specific implementation quirks first,  in arm_smmu_impl_init()
203 	switch (smmu->model) {  in arm_smmu_impl_init()
205 		smmu->impl = &arm_mmu500_impl;  in arm_smmu_impl_init()
208 		return cavium_smmu_impl_init(smmu);  in arm_smmu_impl_init()
213 	/* This is implicitly MMU-400 */  in arm_smmu_impl_init()
214 	if (of_property_read_bool(np, "calxeda,smmu-secure-config-access"))  in arm_smmu_impl_init()
215 		smmu->impl = &calxeda_impl;  in arm_smmu_impl_init()
217 	if (of_device_is_compatible(np, "nvidia,tegra194-smmu"))  in arm_smmu_impl_init()
218 		return nvidia_smmu_impl_init(smmu);  in arm_smmu_impl_init()
220 	if (of_device_is_compatible(np, "qcom,sdm845-smmu-500") ||  in arm_smmu_impl_init()
221 	    of_device_is_compatible(np, "qcom,sc7180-smmu-500") ||  in arm_smmu_impl_init()
222 	    of_device_is_compatible(np, "qcom,sm8150-smmu-500") ||  in arm_smmu_impl_init()
223 	    of_device_is_compatible(np, "qcom,sm8250-smmu-500"))  in arm_smmu_impl_init()
224 		return qcom_smmu_impl_init(smmu);  in arm_smmu_impl_init()
226 	if (of_device_is_compatible(np, "marvell,ap806-smmu-500"))  in arm_smmu_impl_init()
227 		smmu->impl = &mrvl_mmu500_impl;  in arm_smmu_impl_init()
229 	return smmu;  in arm_smmu_impl_init()