Lines Matching full:iommu
19 #include <linux/amd-iommu.h>
24 #include <asm/iommu.h>
97 * structure describing one IOMMU in the ACPI table. Typically followed by one
117 * A device entry describing which devices a specific IOMMU translates and
133 * An AMD IOMMU memory definition structure. It defines things like exclusion
198 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
204 * The rlookup table is used to find the IOMMU which is responsible
217 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
260 bool translation_pre_enabled(struct amd_iommu *iommu) in translation_pre_enabled() argument
262 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); in translation_pre_enabled()
266 static void clear_translation_pre_enabled(struct amd_iommu *iommu) in clear_translation_pre_enabled() argument
268 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; in clear_translation_pre_enabled()
271 static void init_translation_status(struct amd_iommu *iommu) in init_translation_status() argument
275 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in init_translation_status()
277 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; in init_translation_status()
301 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) in iommu_read_l1() argument
305 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); in iommu_read_l1()
306 pci_read_config_dword(iommu->dev, 0xfc, &val); in iommu_read_l1()
310 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) in iommu_write_l1() argument
312 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); in iommu_write_l1()
313 pci_write_config_dword(iommu->dev, 0xfc, val); in iommu_write_l1()
314 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); in iommu_write_l1()
317 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) in iommu_read_l2() argument
321 pci_write_config_dword(iommu->dev, 0xf0, address); in iommu_read_l2()
322 pci_read_config_dword(iommu->dev, 0xf4, &val); in iommu_read_l2()
326 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) in iommu_write_l2() argument
328 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); in iommu_write_l2()
329 pci_write_config_dword(iommu->dev, 0xf4, val); in iommu_write_l2()
334 * AMD IOMMU MMIO register space handling functions
336 * These functions are used to program the IOMMU device registers in
342 * This function set the exclusion range in the IOMMU. DMA accesses to the
345 static void iommu_set_exclusion_range(struct amd_iommu *iommu) in iommu_set_exclusion_range() argument
347 u64 start = iommu->exclusion_start & PAGE_MASK; in iommu_set_exclusion_range()
348 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK; in iommu_set_exclusion_range()
351 if (!iommu->exclusion_start) in iommu_set_exclusion_range()
355 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, in iommu_set_exclusion_range()
359 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, in iommu_set_exclusion_range()
363 static void iommu_set_cwwb_range(struct amd_iommu *iommu) in iommu_set_cwwb_range() argument
365 u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem); in iommu_set_cwwb_range()
368 if (!iommu_feature(iommu, FEATURE_SNP)) in iommu_set_cwwb_range()
375 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, in iommu_set_cwwb_range()
382 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, in iommu_set_cwwb_range()
386 /* Programs the physical address of the device table into the IOMMU hardware */
387 static void iommu_set_device_table(struct amd_iommu *iommu) in iommu_set_device_table() argument
391 BUG_ON(iommu->mmio_base == NULL); in iommu_set_device_table()
395 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, in iommu_set_device_table()
399 /* Generic functions to enable/disable certain features of the IOMMU. */
400 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) in iommu_feature_enable() argument
404 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
406 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
409 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) in iommu_feature_disable() argument
413 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_disable()
415 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_disable()
418 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout) in iommu_set_inv_tlb_timeout() argument
422 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_set_inv_tlb_timeout()
425 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_set_inv_tlb_timeout()
429 static void iommu_enable(struct amd_iommu *iommu) in iommu_enable() argument
431 iommu_feature_enable(iommu, CONTROL_IOMMU_EN); in iommu_enable()
434 static void iommu_disable(struct amd_iommu *iommu) in iommu_disable() argument
436 if (!iommu->mmio_base) in iommu_disable()
440 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in iommu_disable()
443 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); in iommu_disable()
444 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); in iommu_disable()
446 /* Disable IOMMU GA_LOG */ in iommu_disable()
447 iommu_feature_disable(iommu, CONTROL_GALOG_EN); in iommu_disable()
448 iommu_feature_disable(iommu, CONTROL_GAINT_EN); in iommu_disable()
450 /* Disable IOMMU hardware itself */ in iommu_disable()
451 iommu_feature_disable(iommu, CONTROL_IOMMU_EN); in iommu_disable()
455 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
470 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) in iommu_unmap_mmio_space() argument
472 if (iommu->mmio_base) in iommu_unmap_mmio_space()
473 iounmap(iommu->mmio_base); in iommu_unmap_mmio_space()
474 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end); in iommu_unmap_mmio_space()
495 * The functions below belong to the first pass of AMD IOMMU ACPI table
519 * After reading the highest device id from the IOMMU PCI capability header
609 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
616 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
617 * write commands to that buffer later and the IOMMU will execute them
620 static int __init alloc_command_buffer(struct amd_iommu *iommu) in alloc_command_buffer() argument
622 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, in alloc_command_buffer()
625 return iommu->cmd_buf ? 0 : -ENOMEM; in alloc_command_buffer()
629 * This function resets the command buffer if the IOMMU stopped fetching
632 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) in amd_iommu_reset_cmd_buffer() argument
634 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in amd_iommu_reset_cmd_buffer()
636 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); in amd_iommu_reset_cmd_buffer()
637 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); in amd_iommu_reset_cmd_buffer()
638 iommu->cmd_buf_head = 0; in amd_iommu_reset_cmd_buffer()
639 iommu->cmd_buf_tail = 0; in amd_iommu_reset_cmd_buffer()
641 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); in amd_iommu_reset_cmd_buffer()
648 static void iommu_enable_command_buffer(struct amd_iommu *iommu) in iommu_enable_command_buffer() argument
652 BUG_ON(iommu->cmd_buf == NULL); in iommu_enable_command_buffer()
654 entry = iommu_virt_to_phys(iommu->cmd_buf); in iommu_enable_command_buffer()
657 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, in iommu_enable_command_buffer()
660 amd_iommu_reset_cmd_buffer(iommu); in iommu_enable_command_buffer()
666 static void iommu_disable_command_buffer(struct amd_iommu *iommu) in iommu_disable_command_buffer() argument
668 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in iommu_disable_command_buffer()
671 static void __init free_command_buffer(struct amd_iommu *iommu) in free_command_buffer() argument
673 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE)); in free_command_buffer()
676 static void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, in iommu_alloc_4k_pages() argument
683 iommu_feature(iommu, FEATURE_SNP) && in iommu_alloc_4k_pages()
692 /* allocates the memory where the IOMMU will log its events to */
693 static int __init alloc_event_buffer(struct amd_iommu *iommu) in alloc_event_buffer() argument
695 iommu->evt_buf = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, in alloc_event_buffer()
698 return iommu->evt_buf ? 0 : -ENOMEM; in alloc_event_buffer()
701 static void iommu_enable_event_buffer(struct amd_iommu *iommu) in iommu_enable_event_buffer() argument
705 BUG_ON(iommu->evt_buf == NULL); in iommu_enable_event_buffer()
707 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; in iommu_enable_event_buffer()
709 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, in iommu_enable_event_buffer()
713 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); in iommu_enable_event_buffer()
714 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); in iommu_enable_event_buffer()
716 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); in iommu_enable_event_buffer()
722 static void iommu_disable_event_buffer(struct amd_iommu *iommu) in iommu_disable_event_buffer() argument
724 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); in iommu_disable_event_buffer()
727 static void __init free_event_buffer(struct amd_iommu *iommu) in free_event_buffer() argument
729 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); in free_event_buffer()
732 /* allocates the memory where the IOMMU will log its events to */
733 static int __init alloc_ppr_log(struct amd_iommu *iommu) in alloc_ppr_log() argument
735 iommu->ppr_log = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, in alloc_ppr_log()
738 return iommu->ppr_log ? 0 : -ENOMEM; in alloc_ppr_log()
741 static void iommu_enable_ppr_log(struct amd_iommu *iommu) in iommu_enable_ppr_log() argument
745 if (iommu->ppr_log == NULL) in iommu_enable_ppr_log()
748 entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512; in iommu_enable_ppr_log()
750 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET, in iommu_enable_ppr_log()
754 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); in iommu_enable_ppr_log()
755 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); in iommu_enable_ppr_log()
757 iommu_feature_enable(iommu, CONTROL_PPRLOG_EN); in iommu_enable_ppr_log()
758 iommu_feature_enable(iommu, CONTROL_PPR_EN); in iommu_enable_ppr_log()
761 static void __init free_ppr_log(struct amd_iommu *iommu) in free_ppr_log() argument
763 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE)); in free_ppr_log()
766 static void free_ga_log(struct amd_iommu *iommu) in free_ga_log() argument
769 free_pages((unsigned long)iommu->ga_log, get_order(GA_LOG_SIZE)); in free_ga_log()
770 free_pages((unsigned long)iommu->ga_log_tail, get_order(8)); in free_ga_log()
774 static int iommu_ga_log_enable(struct amd_iommu *iommu) in iommu_ga_log_enable() argument
779 if (!iommu->ga_log) in iommu_ga_log_enable()
782 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in iommu_ga_log_enable()
788 iommu_feature_enable(iommu, CONTROL_GAINT_EN); in iommu_ga_log_enable()
789 iommu_feature_enable(iommu, CONTROL_GALOG_EN); in iommu_ga_log_enable()
792 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in iommu_ga_log_enable()
804 static int iommu_init_ga_log(struct amd_iommu *iommu) in iommu_init_ga_log() argument
811 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, in iommu_init_ga_log()
813 if (!iommu->ga_log) in iommu_init_ga_log()
816 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, in iommu_init_ga_log()
818 if (!iommu->ga_log_tail) in iommu_init_ga_log()
821 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; in iommu_init_ga_log()
822 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET, in iommu_init_ga_log()
824 entry = (iommu_virt_to_phys(iommu->ga_log_tail) & in iommu_init_ga_log()
826 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET, in iommu_init_ga_log()
828 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); in iommu_init_ga_log()
829 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET); in iommu_init_ga_log()
833 free_ga_log(iommu); in iommu_init_ga_log()
838 static int iommu_init_ga(struct amd_iommu *iommu) in iommu_init_ga() argument
847 !iommu_feature(iommu, FEATURE_GAM_VAPIC)) in iommu_init_ga()
850 ret = iommu_init_ga_log(iommu); in iommu_init_ga()
856 static int __init alloc_cwwb_sem(struct amd_iommu *iommu) in alloc_cwwb_sem() argument
858 iommu->cmd_sem = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 1); in alloc_cwwb_sem()
860 return iommu->cmd_sem ? 0 : -ENOMEM; in alloc_cwwb_sem()
863 static void __init free_cwwb_sem(struct amd_iommu *iommu) in free_cwwb_sem() argument
865 if (iommu->cmd_sem) in free_cwwb_sem()
866 free_page((unsigned long)iommu->cmd_sem); in free_cwwb_sem()
869 static void iommu_enable_xt(struct amd_iommu *iommu) in iommu_enable_xt() argument
878 iommu_feature_enable(iommu, CONTROL_XT_EN); in iommu_enable_xt()
882 static void iommu_enable_gt(struct amd_iommu *iommu) in iommu_enable_gt() argument
884 if (!iommu_feature(iommu, FEATURE_GT)) in iommu_enable_gt()
887 iommu_feature_enable(iommu, CONTROL_GT_EN); in iommu_enable_gt()
914 struct amd_iommu *iommu; in copy_device_table() local
923 for_each_iommu(iommu) { in copy_device_table()
925 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET); in copy_device_table()
926 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4); in copy_device_table()
929 pr_err("IOMMU:%d should use the same dev table as others!\n", in copy_device_table()
930 iommu->index); in copy_device_table()
937 pr_err("The device table size of IOMMU:%d is not expected!\n", in copy_device_table()
938 iommu->index); in copy_device_table()
1019 /* Writes the specific IOMMU for a device into the rlookup table */
1020 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid) in set_iommu_for_device() argument
1022 amd_iommu_rlookup_table[devid] = iommu; in set_iommu_for_device()
1029 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, in set_dev_entry_from_acpi() argument
1049 set_iommu_for_device(iommu, devid); in set_dev_entry_from_acpi()
1160 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
1163 static int __init init_iommu_from_acpi(struct amd_iommu *iommu, in init_iommu_from_acpi() argument
1185 iommu->acpi_flags = h->flags; in init_iommu_from_acpi()
1209 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0); in init_iommu_from_acpi()
1221 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1251 set_dev_entry_from_acpi(iommu, devid , e->flags, 0); in init_iommu_from_acpi()
1252 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); in init_iommu_from_acpi()
1284 set_dev_entry_from_acpi(iommu, devid, e->flags, in init_iommu_from_acpi()
1312 set_dev_entry_from_acpi(iommu, in init_iommu_from_acpi()
1315 set_dev_entry_from_acpi(iommu, dev_i, in init_iommu_from_acpi()
1351 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1416 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1430 static void __init free_iommu_one(struct amd_iommu *iommu) in free_iommu_one() argument
1432 free_cwwb_sem(iommu); in free_iommu_one()
1433 free_command_buffer(iommu); in free_iommu_one()
1434 free_event_buffer(iommu); in free_iommu_one()
1435 free_ppr_log(iommu); in free_iommu_one()
1436 free_ga_log(iommu); in free_iommu_one()
1437 iommu_unmap_mmio_space(iommu); in free_iommu_one()
1442 struct amd_iommu *iommu, *next; in free_iommu_all() local
1444 for_each_iommu_safe(iommu, next) { in free_iommu_all()
1445 list_del(&iommu->list); in free_iommu_all()
1446 free_iommu_one(iommu); in free_iommu_all()
1447 kfree(iommu); in free_iommu_all()
1452 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1457 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) in amd_iommu_erratum_746_workaround() argument
1466 pci_write_config_dword(iommu->dev, 0xf0, 0x90); in amd_iommu_erratum_746_workaround()
1467 pci_read_config_dword(iommu->dev, 0xf4, &value); in amd_iommu_erratum_746_workaround()
1473 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8)); in amd_iommu_erratum_746_workaround()
1475 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4); in amd_iommu_erratum_746_workaround()
1476 pci_info(iommu->dev, "Applying erratum 746 workaround\n"); in amd_iommu_erratum_746_workaround()
1479 pci_write_config_dword(iommu->dev, 0xf0, 0x90); in amd_iommu_erratum_746_workaround()
1483 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1488 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu) in amd_iommu_ats_write_check_workaround() argument
1498 value = iommu_read_l2(iommu, 0x47); in amd_iommu_ats_write_check_workaround()
1504 iommu_write_l2(iommu, 0x47, value | BIT(0)); in amd_iommu_ats_write_check_workaround()
1506 pci_info(iommu->dev, "Applying ATS write check workaround\n"); in amd_iommu_ats_write_check_workaround()
1510 * This function clues the initialization function for one IOMMU
1512 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1514 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h) in init_iommu_one() argument
1518 raw_spin_lock_init(&iommu->lock); in init_iommu_one()
1519 iommu->cmd_sem_val = 0; in init_iommu_one()
1521 /* Add IOMMU to internal data structures */ in init_iommu_one()
1522 list_add_tail(&iommu->list, &amd_iommu_list); in init_iommu_one()
1523 iommu->index = amd_iommus_present++; in init_iommu_one()
1525 if (unlikely(iommu->index >= MAX_IOMMUS)) { in init_iommu_one()
1530 /* Index is fine - add IOMMU to the array */ in init_iommu_one()
1531 amd_iommus[iommu->index] = iommu; in init_iommu_one()
1534 * Copy data from ACPI table entry to the iommu struct in init_iommu_one()
1536 iommu->devid = h->devid; in init_iommu_one()
1537 iommu->cap_ptr = h->cap_ptr; in init_iommu_one()
1538 iommu->pci_seg = h->pci_seg; in init_iommu_one()
1539 iommu->mmio_phys = h->mmio_phys; in init_iommu_one()
1547 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; in init_iommu_one()
1549 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; in init_iommu_one()
1563 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; in init_iommu_one()
1565 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; in init_iommu_one()
1580 * the IOMMU MMIO access to MSI capability block registers in init_iommu_one()
1592 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys, in init_iommu_one()
1593 iommu->mmio_phys_end); in init_iommu_one()
1594 if (!iommu->mmio_base) in init_iommu_one()
1597 if (alloc_cwwb_sem(iommu)) in init_iommu_one()
1600 if (alloc_command_buffer(iommu)) in init_iommu_one()
1603 if (alloc_event_buffer(iommu)) in init_iommu_one()
1606 iommu->int_enabled = false; in init_iommu_one()
1608 init_translation_status(iommu); in init_iommu_one()
1609 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { in init_iommu_one()
1610 iommu_disable(iommu); in init_iommu_one()
1611 clear_translation_pre_enabled(iommu); in init_iommu_one()
1612 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n", in init_iommu_one()
1613 iommu->index); in init_iommu_one()
1616 amd_iommu_pre_enabled = translation_pre_enabled(iommu); in init_iommu_one()
1618 ret = init_iommu_from_acpi(iommu, h); in init_iommu_one()
1622 ret = amd_iommu_create_irq_domain(iommu); in init_iommu_one()
1627 * Make sure IOMMU is not considered to translate itself. The IVRS in init_iommu_one()
1630 amd_iommu_rlookup_table[iommu->devid] = NULL; in init_iommu_one()
1662 * Iterates over all IOMMU entries in the ACPI table, allocates the
1663 * IOMMU structure and initializes it with init_iommu_one()
1669 struct amd_iommu *iommu; in init_iommu_all() local
1687 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); in init_iommu_all()
1688 if (iommu == NULL) in init_iommu_all()
1691 ret = init_iommu_one(iommu, h); in init_iommu_all()
1703 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
1706 static void init_iommu_perf_ctr(struct amd_iommu *iommu) in init_iommu_perf_ctr() argument
1708 struct pci_dev *pdev = iommu->dev; in init_iommu_perf_ctr()
1711 if (!iommu_feature(iommu, FEATURE_PC)) in init_iommu_perf_ctr()
1717 if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, false)) in init_iommu_perf_ctr()
1721 if ((iommu_pc_get_set_reg(iommu, 0, 0, 0, &val, true)) || in init_iommu_perf_ctr()
1722 (iommu_pc_get_set_reg(iommu, 0, 0, 0, &val2, false)) || in init_iommu_perf_ctr()
1727 if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, true)) in init_iommu_perf_ctr()
1730 pci_info(pdev, "IOMMU performance counters supported\n"); in init_iommu_perf_ctr()
1732 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET); in init_iommu_perf_ctr()
1733 iommu->max_banks = (u8) ((val >> 12) & 0x3f); in init_iommu_perf_ctr()
1734 iommu->max_counters = (u8) ((val >> 7) & 0xf); in init_iommu_perf_ctr()
1739 pci_err(pdev, "Unable to read/write to IOMMU perf counter.\n"); in init_iommu_perf_ctr()
1748 struct amd_iommu *iommu = dev_to_amd_iommu(dev); in amd_iommu_show_cap() local
1749 return sprintf(buf, "%x\n", iommu->cap); in amd_iommu_show_cap()
1757 struct amd_iommu *iommu = dev_to_amd_iommu(dev); in amd_iommu_show_features() local
1758 return sprintf(buf, "%llx\n", iommu->features); in amd_iommu_show_features()
1769 .name = "amd-iommu",
1778 static int __init iommu_init_pci(struct amd_iommu *iommu) in iommu_init_pci() argument
1780 int cap_ptr = iommu->cap_ptr; in iommu_init_pci()
1783 iommu->dev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(iommu->devid), in iommu_init_pci()
1784 iommu->devid & 0xff); in iommu_init_pci()
1785 if (!iommu->dev) in iommu_init_pci()
1788 /* Prevent binding other PCI device drivers to IOMMU devices */ in iommu_init_pci()
1789 iommu->dev->match_driver = false; in iommu_init_pci()
1791 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, in iommu_init_pci()
1792 &iommu->cap); in iommu_init_pci()
1794 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) in iommu_init_pci()
1798 iommu->features = readq(iommu->mmio_base + MMIO_EXT_FEATURES); in iommu_init_pci()
1800 if (iommu_feature(iommu, FEATURE_GT)) { in iommu_init_pci()
1805 pasmax = iommu->features & FEATURE_PASID_MASK; in iommu_init_pci()
1813 glxval = iommu->features & FEATURE_GLXVAL_MASK; in iommu_init_pci()
1822 if (iommu_feature(iommu, FEATURE_GT) && in iommu_init_pci()
1823 iommu_feature(iommu, FEATURE_PPR)) { in iommu_init_pci()
1824 iommu->is_iommu_v2 = true; in iommu_init_pci()
1828 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu)) in iommu_init_pci()
1831 ret = iommu_init_ga(iommu); in iommu_init_pci()
1835 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) in iommu_init_pci()
1838 init_iommu_perf_ctr(iommu); in iommu_init_pci()
1840 if (is_rd890_iommu(iommu->dev)) { in iommu_init_pci()
1843 iommu->root_pdev = in iommu_init_pci()
1844 pci_get_domain_bus_and_slot(0, iommu->dev->bus->number, in iommu_init_pci()
1852 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_init_pci()
1853 &iommu->stored_addr_lo); in iommu_init_pci()
1854 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, in iommu_init_pci()
1855 &iommu->stored_addr_hi); in iommu_init_pci()
1858 iommu->stored_addr_lo &= ~1; in iommu_init_pci()
1862 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); in iommu_init_pci()
1865 iommu->stored_l2[i] = iommu_read_l2(iommu, i); in iommu_init_pci()
1868 amd_iommu_erratum_746_workaround(iommu); in iommu_init_pci()
1869 amd_iommu_ats_write_check_workaround(iommu); in iommu_init_pci()
1871 iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev, in iommu_init_pci()
1872 amd_iommu_groups, "ivhd%d", iommu->index); in iommu_init_pci()
1873 iommu_device_set_ops(&iommu->iommu, &amd_iommu_ops); in iommu_init_pci()
1874 iommu_device_register(&iommu->iommu); in iommu_init_pci()
1876 return pci_enable_device(iommu->dev); in iommu_init_pci()
1885 struct amd_iommu *iommu; in print_iommu_info() local
1887 for_each_iommu(iommu) { in print_iommu_info()
1888 struct pci_dev *pdev = iommu->dev; in print_iommu_info()
1891 pci_info(pdev, "Found IOMMU cap 0x%hx\n", iommu->cap_ptr); in print_iommu_info()
1893 if (iommu->cap & (1 << IOMMU_CAP_EFR)) { in print_iommu_info()
1895 iommu->features); in print_iommu_info()
1897 if (iommu_feature(iommu, (1ULL << i))) in print_iommu_info()
1901 if (iommu->features & FEATURE_GAM_VAPIC) in print_iommu_info()
1918 struct amd_iommu *iommu; in amd_iommu_init_pci() local
1921 for_each_iommu(iommu) { in amd_iommu_init_pci()
1922 ret = iommu_init_pci(iommu); in amd_iommu_init_pci()
1927 iommu_set_cwwb_range(iommu); in amd_iommu_init_pci()
1944 for_each_iommu(iommu) in amd_iommu_init_pci()
1945 iommu_flush_all_caches(iommu); in amd_iommu_init_pci()
1962 static int iommu_setup_msi(struct amd_iommu *iommu) in iommu_setup_msi() argument
1966 r = pci_enable_msi(iommu->dev); in iommu_setup_msi()
1970 r = request_threaded_irq(iommu->dev->irq, in iommu_setup_msi()
1974 iommu); in iommu_setup_msi()
1977 pci_disable_msi(iommu->dev); in iommu_setup_msi()
1981 iommu->int_enabled = true; in iommu_setup_msi()
1996 static void iommu_update_intcapxt(struct amd_iommu *iommu) in iommu_update_intcapxt() argument
1999 u32 addr_lo = readl(iommu->mmio_base + MMIO_MSI_ADDR_LO_OFFSET); in iommu_update_intcapxt()
2000 u32 addr_hi = readl(iommu->mmio_base + MMIO_MSI_ADDR_HI_OFFSET); in iommu_update_intcapxt()
2001 u32 data = readl(iommu->mmio_base + MMIO_MSI_DATA_OFFSET); in iommu_update_intcapxt()
2014 * Current IOMMU implemtation uses the same IRQ for all in iommu_update_intcapxt()
2015 * 3 IOMMU interrupts. in iommu_update_intcapxt()
2017 writeq(val, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET); in iommu_update_intcapxt()
2018 writeq(val, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET); in iommu_update_intcapxt()
2019 writeq(val, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET); in iommu_update_intcapxt()
2025 struct amd_iommu *iommu; in _irq_notifier_notify() local
2027 for_each_iommu(iommu) { in _irq_notifier_notify()
2028 if (iommu->dev->irq == notify->irq) { in _irq_notifier_notify()
2029 iommu_update_intcapxt(iommu); in _irq_notifier_notify()
2039 static int iommu_init_intcapxt(struct amd_iommu *iommu) in iommu_init_intcapxt() argument
2042 struct irq_affinity_notify *notify = &iommu->intcapxt_notify; in iommu_init_intcapxt()
2055 notify->irq = iommu->dev->irq; in iommu_init_intcapxt()
2058 ret = irq_set_affinity_notifier(iommu->dev->irq, notify); in iommu_init_intcapxt()
2061 iommu->devid, iommu->dev->irq); in iommu_init_intcapxt()
2065 iommu_update_intcapxt(iommu); in iommu_init_intcapxt()
2066 iommu_feature_enable(iommu, CONTROL_INTCAPXT_EN); in iommu_init_intcapxt()
2070 static int iommu_init_msi(struct amd_iommu *iommu) in iommu_init_msi() argument
2074 if (iommu->int_enabled) in iommu_init_msi()
2077 if (iommu->dev->msi_cap) in iommu_init_msi()
2078 ret = iommu_setup_msi(iommu); in iommu_init_msi()
2086 ret = iommu_init_intcapxt(iommu); in iommu_init_msi()
2090 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); in iommu_init_msi()
2092 if (iommu->ppr_log != NULL) in iommu_init_msi()
2093 iommu_feature_enable(iommu, CONTROL_PPRINT_EN); in iommu_init_msi()
2095 iommu_ga_log_enable(iommu); in iommu_init_msi()
2227 static void iommu_init_flags(struct amd_iommu *iommu) in iommu_init_flags() argument
2229 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? in iommu_init_flags()
2230 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : in iommu_init_flags()
2231 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); in iommu_init_flags()
2233 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? in iommu_init_flags()
2234 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : in iommu_init_flags()
2235 iommu_feature_disable(iommu, CONTROL_PASSPW_EN); in iommu_init_flags()
2237 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? in iommu_init_flags()
2238 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : in iommu_init_flags()
2239 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); in iommu_init_flags()
2241 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? in iommu_init_flags()
2242 iommu_feature_enable(iommu, CONTROL_ISOC_EN) : in iommu_init_flags()
2243 iommu_feature_disable(iommu, CONTROL_ISOC_EN); in iommu_init_flags()
2246 * make IOMMU memory accesses cache coherent in iommu_init_flags()
2248 iommu_feature_enable(iommu, CONTROL_COHERENT_EN); in iommu_init_flags()
2251 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S); in iommu_init_flags()
2254 static void iommu_apply_resume_quirks(struct amd_iommu *iommu) in iommu_apply_resume_quirks() argument
2258 struct pci_dev *pdev = iommu->root_pdev; in iommu_apply_resume_quirks()
2260 /* RD890 BIOSes may not have completely reconfigured the iommu */ in iommu_apply_resume_quirks()
2261 if (!is_rd890_iommu(iommu->dev) || !pdev) in iommu_apply_resume_quirks()
2265 * First, we need to ensure that the iommu is enabled. This is in iommu_apply_resume_quirks()
2273 /* Enable the iommu */ in iommu_apply_resume_quirks()
2277 /* Restore the iommu BAR */ in iommu_apply_resume_quirks()
2278 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_apply_resume_quirks()
2279 iommu->stored_addr_lo); in iommu_apply_resume_quirks()
2280 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, in iommu_apply_resume_quirks()
2281 iommu->stored_addr_hi); in iommu_apply_resume_quirks()
2286 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); in iommu_apply_resume_quirks()
2290 iommu_write_l2(iommu, i, iommu->stored_l2[i]); in iommu_apply_resume_quirks()
2293 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_apply_resume_quirks()
2294 iommu->stored_addr_lo | 1); in iommu_apply_resume_quirks()
2297 static void iommu_enable_ga(struct amd_iommu *iommu) in iommu_enable_ga() argument
2302 iommu_feature_enable(iommu, CONTROL_GAM_EN); in iommu_enable_ga()
2305 iommu_feature_enable(iommu, CONTROL_GA_EN); in iommu_enable_ga()
2306 iommu->irte_ops = &irte_128_ops; in iommu_enable_ga()
2309 iommu->irte_ops = &irte_32_ops; in iommu_enable_ga()
2315 static void early_enable_iommu(struct amd_iommu *iommu) in early_enable_iommu() argument
2317 iommu_disable(iommu); in early_enable_iommu()
2318 iommu_init_flags(iommu); in early_enable_iommu()
2319 iommu_set_device_table(iommu); in early_enable_iommu()
2320 iommu_enable_command_buffer(iommu); in early_enable_iommu()
2321 iommu_enable_event_buffer(iommu); in early_enable_iommu()
2322 iommu_set_exclusion_range(iommu); in early_enable_iommu()
2323 iommu_enable_ga(iommu); in early_enable_iommu()
2324 iommu_enable_xt(iommu); in early_enable_iommu()
2325 iommu_enable(iommu); in early_enable_iommu()
2326 iommu_flush_all_caches(iommu); in early_enable_iommu()
2339 struct amd_iommu *iommu; in early_enable_iommus() local
2354 for_each_iommu(iommu) { in early_enable_iommus()
2355 clear_translation_pre_enabled(iommu); in early_enable_iommus()
2356 early_enable_iommu(iommu); in early_enable_iommus()
2363 for_each_iommu(iommu) { in early_enable_iommus()
2364 iommu_disable_command_buffer(iommu); in early_enable_iommus()
2365 iommu_disable_event_buffer(iommu); in early_enable_iommus()
2366 iommu_enable_command_buffer(iommu); in early_enable_iommus()
2367 iommu_enable_event_buffer(iommu); in early_enable_iommus()
2368 iommu_enable_ga(iommu); in early_enable_iommus()
2369 iommu_enable_xt(iommu); in early_enable_iommus()
2370 iommu_set_device_table(iommu); in early_enable_iommus()
2371 iommu_flush_all_caches(iommu); in early_enable_iommus()
2383 struct amd_iommu *iommu; in enable_iommus_v2() local
2385 for_each_iommu(iommu) { in enable_iommus_v2()
2386 iommu_enable_ppr_log(iommu); in enable_iommus_v2()
2387 iommu_enable_gt(iommu); in enable_iommus_v2()
2400 struct amd_iommu *iommu; in disable_iommus() local
2402 for_each_iommu(iommu) in disable_iommus()
2403 iommu_disable(iommu); in disable_iommus()
2418 struct amd_iommu *iommu; in amd_iommu_resume() local
2420 for_each_iommu(iommu) in amd_iommu_resume()
2421 iommu_apply_resume_quirks(iommu); in amd_iommu_resume()
2529 * This is the hardware init function for AMD IOMMU in the system.
2533 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
2608 * IOMMU see for that device in early_amd_iommu_init()
2615 /* IOMMU rlookup table - find the IOMMU for a specific device */ in early_amd_iommu_init()
2648 /* Disable IOMMU if there's Stoney Ridge graphics */ in early_amd_iommu_init()
2652 pr_info("Disable IOMMU on Stoney Ridge\n"); in early_amd_iommu_init()
2708 struct amd_iommu *iommu; in amd_iommu_enable_interrupts() local
2711 for_each_iommu(iommu) { in amd_iommu_enable_interrupts()
2712 ret = iommu_init_msi(iommu); in amd_iommu_enable_interrupts()
2745 * AMD IOMMU Initialization State Machine
2766 pr_info("AMD IOMMU disabled\n"); in state_next()
2813 struct amd_iommu *iommu; in state_next() local
2816 for_each_iommu(iommu) in state_next()
2817 iommu_flush_all_caches(iommu); in state_next()
2883 * This is the core init function for AMD IOMMU hardware in the system.
2889 struct amd_iommu *iommu; in amd_iommu_init() local
2896 * We failed to initialize the AMD IOMMU - try fallback in amd_iommu_init()
2903 for_each_iommu(iommu) in amd_iommu_init()
2904 amd_iommu_debugfs_setup(iommu); in amd_iommu_init()
2922 pr_notice("IOMMU not currently supported when SME is active\n"); in amd_iommu_sme_check()
2929 * Early detect code. This code runs at IOMMU detection time in the DMA
2950 x86_init.iommu.iommu_init = amd_iommu_init; in amd_iommu_detect()
2957 * Parsing functions for the AMD IOMMU specific kernel command line
3111 struct amd_iommu *iommu; in get_amd_iommu() local
3113 for_each_iommu(iommu) in get_amd_iommu()
3115 return iommu; in get_amd_iommu()
3122 * IOMMU EFR Performance Counter support functionality. This code allows
3123 * access to the IOMMU PC functionality.
3129 struct amd_iommu *iommu = get_amd_iommu(idx); in amd_iommu_pc_get_max_banks() local
3131 if (iommu) in amd_iommu_pc_get_max_banks()
3132 return iommu->max_banks; in amd_iommu_pc_get_max_banks()
3146 struct amd_iommu *iommu = get_amd_iommu(idx); in amd_iommu_pc_get_max_counters() local
3148 if (iommu) in amd_iommu_pc_get_max_counters()
3149 return iommu->max_counters; in amd_iommu_pc_get_max_counters()
3155 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, in iommu_pc_get_set_reg() argument
3161 /* Make sure the IOMMU PC resource is available */ in iommu_pc_get_set_reg()
3165 /* Check for valid iommu and pc register indexing */ in iommu_pc_get_set_reg()
3166 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7))) in iommu_pc_get_set_reg()
3172 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) | in iommu_pc_get_set_reg()
3173 (iommu->max_counters << 8) | 0x28); in iommu_pc_get_set_reg()
3181 writel((u32)val, iommu->mmio_base + offset); in iommu_pc_get_set_reg()
3182 writel((val >> 32), iommu->mmio_base + offset + 4); in iommu_pc_get_set_reg()
3184 *value = readl(iommu->mmio_base + offset + 4); in iommu_pc_get_set_reg()
3186 *value |= readl(iommu->mmio_base + offset); in iommu_pc_get_set_reg()
3193 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) in amd_iommu_pc_get_reg() argument
3195 if (!iommu) in amd_iommu_pc_get_reg()
3198 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false); in amd_iommu_pc_get_reg()
3202 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) in amd_iommu_pc_set_reg() argument
3204 if (!iommu) in amd_iommu_pc_set_reg()
3207 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true); in amd_iommu_pc_set_reg()