Lines Matching refs:SYM_LSB
182 (((value) >> SYM_LSB(regname, fldname)) & \
187 (((value) >> SYM_LSB(regname, fldname)) & MASK_ACROSS(0, nbits))
198 #define SYM_LSB(regname, fldname) (QIB_7322_##regname##_##fldname##_LSB) macro
370 SYM_LSB(RcvTIDFlowTable0, GenMismatch)) | \
372 SYM_LSB(RcvTIDFlowTable0, SeqMismatch)))
476 #define IBA7322_LINKSPEED_SHIFT SYM_LSB(IBCStatusA_0, LinkSpeedActive)
477 #define IBA7322_LINKWIDTH_SHIFT SYM_LSB(IBCStatusA_0, LinkWidthActive)
678 SYM_LSB(IntStatus, SendBufAvail), 0, 0},
680 SYM_LSB(IntStatus, SDmaInt_0), 1, 1 },
682 SYM_LSB(IntStatus, SDmaInt_1), 2, 1 },
684 SYM_LSB(IntStatus, SDmaIdleInt_0), 1, 1},
686 SYM_LSB(IntStatus, SDmaIdleInt_1), 2, 1},
688 SYM_LSB(IntStatus, SDmaProgressInt_0), 1, 1 },
690 SYM_LSB(IntStatus, SDmaProgressInt_1), 2, 1 },
692 SYM_LSB(IntStatus, SDmaCleanupDone_0), 1, 0 },
694 SYM_LSB(IntStatus, SDmaCleanupDone_1), 2 , 0},
705 { 0, SYM_LSB(DCACtrlB, RcvHdrq0DCAOPH),
707 { 0, SYM_LSB(DCACtrlB, RcvHdrq1DCAOPH),
709 { 0, SYM_LSB(DCACtrlB, RcvHdrq2DCAOPH),
711 { 0, SYM_LSB(DCACtrlB, RcvHdrq3DCAOPH),
713 { 1, SYM_LSB(DCACtrlC, RcvHdrq4DCAOPH),
715 { 1, SYM_LSB(DCACtrlC, RcvHdrq5DCAOPH),
717 { 1, SYM_LSB(DCACtrlC, RcvHdrq6DCAOPH),
719 { 1, SYM_LSB(DCACtrlC, RcvHdrq7DCAOPH),
721 { 2, SYM_LSB(DCACtrlD, RcvHdrq8DCAOPH),
723 { 2, SYM_LSB(DCACtrlD, RcvHdrq9DCAOPH),
725 { 2, SYM_LSB(DCACtrlD, RcvHdrq10DCAOPH),
727 { 2, SYM_LSB(DCACtrlD, RcvHdrq11DCAOPH),
729 { 3, SYM_LSB(DCACtrlE, RcvHdrq12DCAOPH),
731 { 3, SYM_LSB(DCACtrlE, RcvHdrq13DCAOPH),
733 { 3, SYM_LSB(DCACtrlE, RcvHdrq14DCAOPH),
735 { 3, SYM_LSB(DCACtrlE, RcvHdrq15DCAOPH),
737 { 4, SYM_LSB(DCACtrlF, RcvHdrq16DCAOPH),
739 { 4, SYM_LSB(DCACtrlF, RcvHdrq17DCAOPH),
949 #define QIB_I_RCVURG_LSB SYM_LSB(IntMask, RcvUrg0IntMask)
952 #define QIB_I_RCVAVAIL_LSB SYM_LSB(IntMask, RcvAvail0IntMask)
1158 #define IBA7322_IBCC_LINKCMD_SHIFT SYM_LSB(IBCCtrlA_0, LinkCmd)
1173 #define IBA7322_IBC_SPEED_LSB SYM_LSB(IBCCtrlB_0, SD_SPEED_SDR)
1175 #define IBA7322_LEDBLINK_OFF_SHIFT SYM_LSB(RcvPktLEDCnt_0, OFFperiod)
1176 #define IBA7322_LEDBLINK_ON_SHIFT SYM_LSB(RcvPktLEDCnt_0, ONperiod)
1179 #define IBA7322_IBC_WIDTH_4X_ONLY (1<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1180 #define IBA7322_IBC_WIDTH_1X_ONLY (0<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1183 #define IBA7322_IBC_RXPOL_LSB SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1187 SYM_LSB(IBCCtrlB_0, HRTBT_ENB))
1188 #define IBA7322_IBC_HRTBT_LSB SYM_LSB(IBCCtrlB_0, HRTBT_ENB)
1301 SYM_LSB(IntMask, fldname##Mask##_0), \
1302 SYM_LSB(IntMask, fldname##Mask##_1)), \
1306 SYM_LSB(IntMask, fldname##Mask##_1), \
1307 SYM_LSB(IntMask, fldname##Mask##_0)), \
1314 SYM_LSB(IntMask, fldname##0IntMask), \
1315 SYM_LSB(IntMask, fldname##17IntMask)), \
2358 ((u64)(numvls - 1) << SYM_LSB(IBCCtrlA_0, NumVLane)); in set_vls()
2403 ibc = 0x5ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlWaterMark); in qib_7322_bringup_serdes()
2409 ibc |= 24ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlPeriod); in qib_7322_bringup_serdes()
2411 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, PhyerrThreshold); in qib_7322_bringup_serdes()
2413 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, OverrunThreshold); in qib_7322_bringup_serdes()
2419 SYM_LSB(IBCCtrlA_0, MaxPktLen); in qib_7322_bringup_serdes()
2472 val |= 0xfULL << SYM_LSB(IBCCtrlC_0, IB_FRONT_PORCH); in qib_7322_bringup_serdes()
2733 SYM_LSB(DCACtrlF, SendDma1DCAOPH) : in qib_update_sdma_dca()
2734 SYM_LSB(DCACtrlF, SendDma0DCAOPH)); in qib_update_sdma_dca()
2757 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq0DCAXfrCnt)) | in qib_setup_dca()
2758 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq1DCAXfrCnt)) | in qib_setup_dca()
2759 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq2DCAXfrCnt)) | in qib_setup_dca()
2760 (1ULL << SYM_LSB(DCACtrlB, RcvHdrq3DCAXfrCnt)); in qib_setup_dca()
2762 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq4DCAXfrCnt)) | in qib_setup_dca()
2763 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq5DCAXfrCnt)) | in qib_setup_dca()
2764 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq6DCAXfrCnt)) | in qib_setup_dca()
2765 (1ULL << SYM_LSB(DCACtrlC, RcvHdrq7DCAXfrCnt)); in qib_setup_dca()
2767 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq8DCAXfrCnt)) | in qib_setup_dca()
2768 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq9DCAXfrCnt)) | in qib_setup_dca()
2769 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq10DCAXfrCnt)) | in qib_setup_dca()
2770 (1ULL << SYM_LSB(DCACtrlD, RcvHdrq11DCAXfrCnt)); in qib_setup_dca()
2772 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq12DCAXfrCnt)) | in qib_setup_dca()
2773 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq13DCAXfrCnt)) | in qib_setup_dca()
2774 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq14DCAXfrCnt)) | in qib_setup_dca()
2775 (1ULL << SYM_LSB(DCACtrlE, RcvHdrq15DCAXfrCnt)); in qib_setup_dca()
2777 (1ULL << SYM_LSB(DCACtrlF, RcvHdrq16DCAXfrCnt)) | in qib_setup_dca()
2778 (1ULL << SYM_LSB(DCACtrlF, RcvHdrq17DCAXfrCnt)); in qib_setup_dca()
2993 pins >>= SYM_LSB(EXTStatus, GPIOIn); in unknown_7322_gpio_intr()
3509 SYM_LSB(IntRedirect0, vec1); in qib_setup_7322_interrupt()
3937 dd->rcvctrl |= 2ULL << SYM_LSB(RcvCtrl, ContextCfg); in qib_7322_config_ctxts()
3939 dd->rcvctrl |= 1ULL << SYM_LSB(RcvCtrl, ContextCfg); in qib_7322_config_ctxts()
3943 dd->rcvctrl |= 5ULL << SYM_LSB(RcvCtrl, XrcTypeCode); in qib_7322_config_ctxts()
3986 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP); in qib_7322_get_ib_cfg()
3991 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED); in qib_7322_get_ib_cfg()
4103 lsb = SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS); in qib_7322_set_ib_cfg()
4128 lsb = SYM_LSB(IBCCtrlB_0, IB_ENHANCED_MODE); in qib_7322_set_ib_cfg()
4132 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP); in qib_7322_set_ib_cfg()
4137 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED); in qib_7322_set_ib_cfg()
4148 SYM_LSB(IBCCtrlA_0, OverrunThreshold); in qib_7322_set_ib_cfg()
4162 SYM_LSB(IBCCtrlA_0, PhyerrThreshold); in qib_7322_set_ib_cfg()
4199 SYM_LSB(IBCCtrlA_0, MaxPktLen); in qib_7322_set_ib_cfg()
4362 vl->vl = (val >> SYM_LSB(LowPriority0_0, VirtualLane)) & in get_vl_weights()
4364 vl->weight = (val >> SYM_LSB(LowPriority0_0, Weight)) & in get_vl_weights()
4378 SYM_LSB(LowPriority0_0, VirtualLane)) | in set_vl_weights()
4380 SYM_LSB(LowPriority0_0, Weight)); in set_vl_weights()
4510 (mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel)); in rcvctrl_7322_mod()
4524 ~(mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel)); in rcvctrl_7322_mod()
4526 dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull); in rcvctrl_7322_mod()
4528 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull)); in rcvctrl_7322_mod()
4530 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail)); in rcvctrl_7322_mod()
4532 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail)); in rcvctrl_7322_mod()
4682 SYM_LSB(SendCtrl, DisarmSendBuf)); in sendctrl_7322_mod()
5704 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe)); in gpio_7322_mod()
5705 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe)); in gpio_7322_mod()
6027 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert)); in qib_init_7322_qsfp()
6250 SYM_LSB(IB_SDTEST_IF_TX_0, VL_CAP); in write_7322_init_portregs()
6692 << SYM_LSB(SendCtrl, AvailUpdThld)) | in qib_init_7322_variables()
7114 SYM_LSB(SendCtrl, AvailUpdThld); in qib_7322_txchk_change()
7134 << SYM_LSB(SendCtrl, AvailUpdThld); in qib_7322_txchk_change()
7724 #define AHB_ADDR_LSB SYM_LSB(ahb_transaction_reg, ahb_address)
7725 #define AHB_DATA_LSB SYM_LSB(ahb_transaction_reg, ahb_data)
8195 txampcntl_d2a)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0, in write_tx_serdes_param()
8198 txc0_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0, in write_tx_serdes_param()
8201 txcp1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0, in write_tx_serdes_param()
8204 txcn1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0, in write_tx_serdes_param()
8244 #define BISTEN_LSB SYM_LSB(SPC_JTAG_ACCESS_REG, bist_en)