Lines Matching +full:combined +full:- +full:power +full:- +full:req
2 * Copyright (c) 2012 - 2017 Intel Corporation. All rights reserved.
3 * Copyright (c) 2008 - 2012 QLogic Corporation. All rights reserved.
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
88 #define BMASK(msb, lsb) (((1 << ((msb) + 1 - (lsb))) - 1) << (lsb))
95 /* Below is special-purpose, so only really works for the IB SerDes blocks. */
112 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
125 MODULE_PARM_DESC(singleport, "Use only IB port 1; more per-port buffer space");
140 MODULE_PARM_DESC(rcvhdrsize, "receive header size in 32-bit words");
144 MODULE_PARM_DESC(rcvhdrentsize, "receive header entry size in 32-bit words");
162 #define IS_QMH(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
164 #define IS_QME(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
172 (((1ULL << ((msb) + 1 - (lsb))) - 1) << (lsb))
237 * This file contains almost all the chip-specific register information and
238 * access functions for the FAKED QLogic InfiniPath 7322 PCI-Express chip.
241 /* Use defines to tie machine-generated names to lower-case names */
267 #define kr_rcvctrl KREG_IDX(RcvCtrl) /* Common, but chip also has per-port */
295 * per-port kernel registers. Access only with qib_read_kreg_port()
350 * Per-context kernel registers. Access only with qib_read_kreg_ctxt()
365 #define ur_rcvflowtable (KREG_IDX(RcvTIDFlowTable0) - KREG_IDX(RcvHdrTail0))
374 /* Most (not all) Counters are per-IBport.
378 ((QIB_7322_##regname##_0_OFFS - QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
424 /* these are the (few) counters that are not port-specific */
425 #define CREG_DEVIDX(regname) ((QIB_7322_##regname##_OFFS - \
449 /* values for vl and port fields in PBC, 7322-specific */
617 #define QDR_STATIC_ADAPT_DOWN 0xf0f0f0f0ULL /* link down, H1-H4 QDR adapts */
618 #define QDR_STATIC_ADAPT_DOWN_R1 0ULL /* r1 link down, H1-H4 QDR adapts */
619 #define QDR_STATIC_ADAPT_INIT 0xffffffffffULL /* up, disable H0,H1-8, LE */
620 #define QDR_STATIC_ADAPT_INIT_R1 0xf0ffffffffULL /* r1 up, disable H0,H1-8 */
635 * DDR when faking DDR negotiations with non-IBTA switches.
637 * a non-zero delta.
657 * Per-bay per-channel rcv QMH H1 values and Tx values for QDR.
666 char sdmamsgbuf[192]; /* for per-port sdma error messages */
673 int port; /* 0 if not port-specific, else port # */
676 { "", qib_7322intr, -1, 0, 0 },
773 * qib_read_ureg32 - read 32-bit virtualized per-context register
779 * Returns -1 on errors (not distinguishable from valid contents at
785 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) in qib_read_ureg32()
788 (dd->ureg_align * ctxt) + (dd->userbase ? in qib_read_ureg32()
789 (char __iomem *)dd->userbase : in qib_read_ureg32()
790 (char __iomem *)dd->kregbase + dd->uregbase))); in qib_read_ureg32()
794 * qib_read_ureg - read virtualized per-context register
800 * Returns -1 on errors (not distinguishable from valid contents at
807 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) in qib_read_ureg()
810 (dd->ureg_align * ctxt) + (dd->userbase ? in qib_read_ureg()
811 (char __iomem *)dd->userbase : in qib_read_ureg()
812 (char __iomem *)dd->kregbase + dd->uregbase))); in qib_read_ureg()
816 * qib_write_ureg - write virtualized per-context register
829 if (dd->userbase) in qib_write_ureg()
831 ((char __iomem *) dd->userbase + in qib_write_ureg()
832 dd->ureg_align * ctxt); in qib_write_ureg()
835 (dd->uregbase + in qib_write_ureg()
836 (char __iomem *) dd->kregbase + in qib_write_ureg()
837 dd->ureg_align * ctxt); in qib_write_ureg()
839 if (dd->kregbase && (dd->flags & QIB_PRESENT)) in qib_write_ureg()
846 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) in qib_read_kreg32()
847 return -1; in qib_read_kreg32()
848 return readl((u32 __iomem *) &dd->kregbase[regno]); in qib_read_kreg32()
854 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) in qib_read_kreg64()
855 return -1; in qib_read_kreg64()
856 return readq(&dd->kregbase[regno]); in qib_read_kreg64()
862 if (dd->kregbase && (dd->flags & QIB_PRESENT)) in qib_write_kreg()
863 writeq(value, &dd->kregbase[regno]); in qib_write_kreg()
867 * not many sanity checks for the port-specific kernel register routines,
873 if (!ppd->cpspec->kpregbase || !(ppd->dd->flags & QIB_PRESENT)) in qib_read_kreg_port()
875 return readq(&ppd->cpspec->kpregbase[regno]); in qib_read_kreg_port()
881 if (ppd->cpspec && ppd->dd && ppd->cpspec->kpregbase && in qib_write_kreg_port()
882 (ppd->dd->flags & QIB_PRESENT)) in qib_write_kreg_port()
883 writeq(value, &ppd->cpspec->kpregbase[regno]); in qib_write_kreg_port()
887 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
902 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) in read_7322_creg()
904 return readq(&dd->cspec->cregbase[regno]); in read_7322_creg()
911 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) in read_7322_creg32()
913 return readl(&dd->cspec->cregbase[regno]); in read_7322_creg32()
921 if (ppd->cpspec && ppd->cpspec->cpregbase && in write_7322_creg_port()
922 (ppd->dd->flags & QIB_PRESENT)) in write_7322_creg_port()
923 writeq(value, &ppd->cpspec->cpregbase[regno]); in write_7322_creg_port()
929 if (!ppd->cpspec || !ppd->cpspec->cpregbase || in read_7322_creg_port()
930 !(ppd->dd->flags & QIB_PRESENT)) in read_7322_creg_port()
932 return readq(&ppd->cpspec->cpregbase[regno]); in read_7322_creg_port()
938 if (!ppd->cpspec || !ppd->cpspec->cpregbase || in read_7322_creg32_port()
939 !(ppd->dd->flags & QIB_PRESENT)) in read_7322_creg32_port()
941 return readl(&ppd->cpspec->cpregbase[regno]); in read_7322_creg32_port()
1033 * Per chip (rather than per-port) errors. Most either do
1034 * nothing but trigger a print (because they self-recover, or
1051 * E_AUTO mechanism. This is true of most of the per-port fatal errors
1052 * as well, but since this is port-independent, by definition, it's
1055 * per-packet errors.
1071 /* Error Bits that Packet-related (Receive, per-port) */
1081 * Error bits that are Send-related (per port)
1294 * Below generates "auto-message" for interrupts not specific to any port or
1299 /* Below generates "auto-message" for interrupts specific to a port */
1310 * Below generates "auto-message" for interrupts specific to a context,
1311 * with ctxt-number appended
1336 * PIO buffer, and may need to cancel that buffer, so it can be re-used,
1341 struct qib_devdata *dd = ppd->dd; in qib_disarm_7322_senderrbufs()
1344 u32 piobcnt = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS; in qib_disarm_7322_senderrbufs()
1345 u32 regcnt = (piobcnt + BITS_PER_LONG - 1) / BITS_PER_LONG; in qib_disarm_7322_senderrbufs()
1374 while (errs && msp && msp->mask) { in err_decode()
1375 multi = (msp->mask & (msp->mask - 1)); in err_decode()
1376 while (errs & msp->mask) { in err_decode()
1377 these = (errs & msp->mask); in err_decode()
1378 lmask = (these & (these - 1)) ^ these; in err_decode()
1383 len--; in err_decode()
1385 /* msp->sz counts the nul */ in err_decode()
1386 took = min_t(size_t, msp->sz - (size_t)1, len); in err_decode()
1387 memcpy(msg, msp->msg, took); in err_decode()
1388 len -= took; in err_decode()
1396 int idx = -1; in err_decode()
1398 while (lmask & msp->mask) { in err_decode()
1403 len -= took; in err_decode()
1418 struct qib_devdata *dd = ppd->dd; in flush_fifo()
1442 (((u64)ppd->hw_pidx) << (PBC_PORT_SEL_LSB + 32)) | in flush_fifo()
1449 if (dd->flags & QIB_PIO_FLUSH_WC) { in flush_fifo()
1451 qib_pio_copy(piobuf + 2, hdr, hdrwords - 1); in flush_fifo()
1453 __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords + 1); in flush_fifo()
1465 struct qib_devdata *dd = ppd->dd; in qib_7322_sdma_sendctrl()
1493 spin_lock(&dd->sendctrl_lock); in qib_7322_sdma_sendctrl()
1497 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable); in qib_7322_sdma_sendctrl()
1498 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl); in qib_7322_sdma_sendctrl()
1502 ppd->p_sendctrl |= set_sendctrl; in qib_7322_sdma_sendctrl()
1503 ppd->p_sendctrl &= ~clr_sendctrl; in qib_7322_sdma_sendctrl()
1507 ppd->p_sendctrl | in qib_7322_sdma_sendctrl()
1510 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl); in qib_7322_sdma_sendctrl()
1514 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable); in qib_7322_sdma_sendctrl()
1515 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl); in qib_7322_sdma_sendctrl()
1519 spin_unlock(&dd->sendctrl_lock); in qib_7322_sdma_sendctrl()
1521 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1) in qib_7322_sdma_sendctrl()
1537 qib_write_kreg_port(ppd, krp_senddmalengen, ppd->sdma_descq_cnt); in qib_sdma_7322_setlengen()
1539 ppd->sdma_descq_cnt | in qib_sdma_7322_setlengen()
1550 ppd->sdma_descq_tail = tail; in qib_sdma_update_7322_tail()
1569 ppd->sdma_head_dma[0] = 0; in qib_7322_sdma_hw_start_up()
1571 ppd->sdma_state.current_op | QIB_SDMA_SENDCTRL_OP_CLEANUP); in qib_7322_sdma_hw_start_up()
1589 struct qib_devdata *dd = ppd->dd; in sdma_7322_p_errors()
1592 err_decode(ppd->cpspec->sdmamsgbuf, sizeof(ppd->cpspec->sdmamsgbuf), in sdma_7322_p_errors()
1596 qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", dd->unit, in sdma_7322_p_errors()
1597 ppd->port); in sdma_7322_p_errors()
1599 spin_lock_irqsave(&ppd->sdma_lock, flags); in sdma_7322_p_errors()
1603 qib_dev_porterr(dd, ppd->port, in sdma_7322_p_errors()
1605 qib_sdma_state_names[ppd->sdma_state.current_state], in sdma_7322_p_errors()
1606 errs, ppd->cpspec->sdmamsgbuf); in sdma_7322_p_errors()
1610 switch (ppd->sdma_state.current_state) { in sdma_7322_p_errors()
1644 spin_unlock_irqrestore(&ppd->sdma_lock, flags); in sdma_7322_p_errors()
1648 * handle per-device errors (not per-port errors)
1660 qib_devinfo(dd->pcidev, in handle_7322_errors()
1666 errs &= dd->cspec->errormask; in handle_7322_errors()
1667 msg = dd->cspec->emsgbuf; in handle_7322_errors()
1672 qib_7322_handle_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf)); in handle_7322_errors()
1676 qib_disarm_7322_senderrbufs(dd->pport); in handle_7322_errors()
1682 qib_disarm_7322_senderrbufs(dd->pport); in handle_7322_errors()
1694 err_decode(msg, sizeof(dd->cspec->emsgbuf), errs & ~mask, in handle_7322_errors()
1705 "Got reset, requires re-init (unload and reload driver)\n"); in handle_7322_errors()
1706 dd->flags &= ~QIB_INITTED; /* needs re-init */ in handle_7322_errors()
1708 *dd->devstatusp |= QIB_STATUS_HWERROR; in handle_7322_errors()
1709 for (pidx = 0; pidx < dd->num_pports; ++pidx) in handle_7322_errors()
1710 if (dd->pport[pidx].link_speed_supported) in handle_7322_errors()
1711 *dd->pport[pidx].statusp &= ~QIB_STATUS_IB_CONF; in handle_7322_errors()
1741 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); in qib_error_tasklet()
1747 struct qib_pportdata *ppd = cp->ppd; in reenable_chase()
1749 ppd->cpspec->chase_timer.expires = 0; in reenable_chase()
1757 ppd->cpspec->chase_end = 0; in disable_chase()
1764 ppd->cpspec->chase_timer.expires = jiffies + QIB_CHASE_DIS_TIME; in disable_chase()
1765 add_timer(&ppd->cpspec->chase_timer); in disable_chase()
1779 * then re-enable. in handle_serdes_issues()
1787 if (ppd->cpspec->chase_end && in handle_serdes_issues()
1788 time_after(tnow, ppd->cpspec->chase_end)) in handle_serdes_issues()
1790 else if (!ppd->cpspec->chase_end) in handle_serdes_issues()
1791 ppd->cpspec->chase_end = tnow + QIB_CHASE_TIME; in handle_serdes_issues()
1794 ppd->cpspec->chase_end = 0; in handle_serdes_issues()
1803 ppd->cpspec->qdr_reforce = 1; in handle_serdes_issues()
1804 if (!ppd->dd->cspec->r1) in handle_serdes_issues()
1806 } else if (ppd->cpspec->qdr_reforce && in handle_serdes_issues()
1813 if ((IS_QMH(ppd->dd) || IS_QME(ppd->dd)) && in handle_serdes_issues()
1814 ppd->link_speed_enabled == QIB_IB_QDR && in handle_serdes_issues()
1823 u8 pibclt = (u8)SYM_FIELD(ppd->lastibcstat, IBCStatusA_0, in handle_serdes_issues()
1825 if (!ppd->dd->cspec->r1 && in handle_serdes_issues()
1834 if (!ppd->cpspec->qdr_dfe_on && in handle_serdes_issues()
1836 ppd->cpspec->qdr_dfe_on = 1; in handle_serdes_issues()
1837 ppd->cpspec->qdr_dfe_time = 0; in handle_serdes_issues()
1840 ppd->dd->cspec->r1 ? in handle_serdes_issues()
1844 "IB%u:%u re-enabled QDR adaptation ibclt %x\n", in handle_serdes_issues()
1845 ppd->dd->unit, ppd->port, ibclt); in handle_serdes_issues()
1853 * This is per-pport error handling.
1861 struct qib_devdata *dd = ppd->dd; in handle_7322_p_errors()
1870 qib_devinfo(dd->pcidev, in handle_7322_p_errors()
1872 ppd->port); in handle_7322_p_errors()
1878 msg = ppd->cpspec->epmsgbuf; in handle_7322_p_errors()
1882 err_decode(msg, sizeof(ppd->cpspec->epmsgbuf), in handle_7322_p_errors()
1885 snprintf(msg, sizeof(ppd->cpspec->epmsgbuf), in handle_7322_p_errors()
1887 qib_dev_porterr(dd, ppd->port, in handle_7322_p_errors()
1899 err_decode(msg, sizeof(ppd->cpspec->epmsgbuf), symptom, in handle_7322_p_errors()
1907 !(ppd->lflags & QIBL_LINKACTIVE)) { in handle_7322_p_errors()
1915 err_decode(msg, sizeof(ppd->cpspec->epmsgbuf), in handle_7322_p_errors()
1923 !(ppd->lflags & QIBL_LINKACTIVE)) { in handle_7322_p_errors()
1931 err_decode(msg, sizeof(ppd->cpspec->epmsgbuf), errs, in handle_7322_p_errors()
1960 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) in handle_7322_p_errors()
1962 if (!(ppd->cpspec->ibcctrl_a & in handle_7322_p_errors()
1967 * other "chatter" from link-negotiation (pre Init) in handle_7322_p_errors()
1969 ppd->cpspec->ibcctrl_a |= in handle_7322_p_errors()
1972 ppd->cpspec->ibcctrl_a); in handle_7322_p_errors()
1976 ppd->link_width_active = in handle_7322_p_errors()
1979 ppd->link_speed_active = (ibcs & SYM_MASK(IBCStatusA_0, in handle_7322_p_errors()
1984 if ((ppd->lflags & QIBL_IB_LINK_DISABLED) && ltstate != in handle_7322_p_errors()
2004 qib_dev_porterr(dd, ppd->port, "%s error\n", msg); in handle_7322_p_errors()
2006 if (ppd->state_wanted & ppd->lflags) in handle_7322_p_errors()
2007 wake_up_interruptible(&ppd->state_wait); in handle_7322_p_errors()
2016 if (dd->flags & QIB_BADINTR) in qib_7322_set_intr_state()
2018 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask); in qib_7322_set_intr_state()
2019 /* cause any pending enabled interrupts to be re-delivered */ in qib_7322_set_intr_state()
2021 if (dd->cspec->num_msix_entries) { in qib_7322_set_intr_state()
2037 * Forcibly update the in-memory pioavail register copies after cleanup
2044 * This is in chip-specific code because of all of the register accesses,
2054 for (pidx = 0; pidx < dd->num_pports; ++pidx) in qib_7322_clear_freeze()
2055 if (dd->pport[pidx].link_speed_supported) in qib_7322_clear_freeze()
2056 qib_write_kreg_port(dd->pport + pidx, krp_errmask, in qib_7322_clear_freeze()
2063 qib_write_kreg(dd, kr_control, dd->control); in qib_7322_clear_freeze()
2069 * and cancelling sends. Re-enable error interrupts before possible in qib_7322_clear_freeze()
2070 * force of re-interrupt on pending interrupts. in qib_7322_clear_freeze()
2074 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); in qib_7322_clear_freeze()
2075 /* We need to purge per-port errs and reset mask, too */ in qib_7322_clear_freeze()
2076 for (pidx = 0; pidx < dd->num_pports; ++pidx) { in qib_7322_clear_freeze()
2077 if (!dd->pport[pidx].link_speed_supported) in qib_7322_clear_freeze()
2079 qib_write_kreg_port(dd->pport + pidx, krp_errclear, ~0Ull); in qib_7322_clear_freeze()
2080 qib_write_kreg_port(dd->pport + pidx, krp_errmask, ~0Ull); in qib_7322_clear_freeze()
2087 * qib_7322_handle_hwerrors - display hardware errors.
2118 hwerrs &= dd->cspec->hwerrmask; in qib_7322_handle_hwerrors()
2123 qib_devinfo(dd->pcidev, in qib_7322_handle_hwerrors()
2128 if ((ctrl & SYM_MASK(Control, FreezeMode)) && !dd->diag_client) { in qib_7322_handle_hwerrors()
2133 dd->cspec->stay_in_freeze) { in qib_7322_handle_hwerrors()
2141 if (dd->flags & QIB_INITTED) in qib_7322_handle_hwerrors()
2153 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed); in qib_7322_handle_hwerrors()
2154 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_7322_handle_hwerrors()
2169 struct qib_pportdata *ppd = dd->pport; in qib_7322_handle_hwerrors()
2171 for (; pidx < dd->num_pports; ++pidx, ppd++) { in qib_7322_handle_hwerrors()
2180 spin_lock_irqsave(&ppd->sdma_lock, flags); in qib_7322_handle_hwerrors()
2182 spin_unlock_irqrestore(&ppd->sdma_lock, flags); in qib_7322_handle_hwerrors()
2187 if (isfatal && !dd->diag_client) { in qib_7322_handle_hwerrors()
2190 dd->serial); in qib_7322_handle_hwerrors()
2195 if (dd->freezemsg) in qib_7322_handle_hwerrors()
2196 snprintf(dd->freezemsg, dd->freezelen, in qib_7322_handle_hwerrors()
2204 * qib_7322_init_hwerrors - enable hardware errors
2225 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_7322_init_hwerrors()
2231 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask); in qib_7322_init_hwerrors()
2232 for (pidx = 0; pidx < dd->num_pports; ++pidx) in qib_7322_init_hwerrors()
2233 if (dd->pport[pidx].link_speed_supported) in qib_7322_init_hwerrors()
2234 qib_write_kreg_port(dd->pport + pidx, krp_errmask, in qib_7322_init_hwerrors()
2240 * on chips that are count-based, rather than trigger-based. There is no
2242 * Only chip-specific because it's all register accesses
2248 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH; in qib_set_7322_armlaunch()
2250 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH; in qib_set_7322_armlaunch()
2251 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); in qib_set_7322_armlaunch()
2255 * Formerly took parameter <which> in pre-shifted,
2256 * pre-merged form with LinkCmd and LinkInitCmd
2263 struct qib_devdata *dd = ppd->dd; in qib_set_ib_7322_lstate()
2268 * If we are told to disable, note that so link-recovery in qib_set_ib_7322_lstate()
2271 * completely clean when re-enabled (before we in qib_set_ib_7322_lstate()
2275 spin_lock_irqsave(&ppd->lflags_lock, flags); in qib_set_ib_7322_lstate()
2276 ppd->lflags |= QIBL_IB_LINK_DISABLED; in qib_set_ib_7322_lstate()
2277 spin_unlock_irqrestore(&ppd->lflags_lock, flags); in qib_set_ib_7322_lstate()
2282 * link-recovery code attempt to bring us back up. in qib_set_ib_7322_lstate()
2284 spin_lock_irqsave(&ppd->lflags_lock, flags); in qib_set_ib_7322_lstate()
2285 ppd->lflags &= ~QIBL_IB_LINK_DISABLED; in qib_set_ib_7322_lstate()
2286 spin_unlock_irqrestore(&ppd->lflags_lock, flags); in qib_set_ib_7322_lstate()
2291 ppd->cpspec->ibcctrl_a &= in qib_set_ib_7322_lstate()
2298 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a | in qib_set_ib_7322_lstate()
2300 /* write to chip to prevent back-to-back writes of ibc reg */ in qib_set_ib_7322_lstate()
2314 #define NUM_RCV_BUF_UNITS(dd) ((64 * 1024) / (RCV_BUF_UNITSZ * dd->num_pports))
2319 struct qib_devdata *dd = ppd->dd; in set_vls()
2322 numvls = qib_num_vls(ppd->vls_operational); in set_vls()
2325 * Set up per-VL credits. Below is kluge based on these assumptions: in set_vls()
2327 * 2) give VL15 17 credits, for two max-plausible packets. in set_vls()
2328 * 3) Give VL0-N the rest, with any rounding excess used for VL0 in set_vls()
2332 cred_vl = (2 * 288 + RCV_BUF_UNITSZ - 1) / RCV_BUF_UNITSZ; in set_vls()
2333 totcred -= cred_vl; in set_vls()
2336 vl0extra = totcred - cred_vl * numvls; in set_vls()
2356 ppd->cpspec->ibcctrl_a = (ppd->cpspec->ibcctrl_a & in set_vls()
2358 ((u64)(numvls - 1) << SYM_LSB(IBCCtrlA_0, NumVLane)); in set_vls()
2359 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a); in set_vls()
2370 * qib_7322_bringup_serdes - bring up the serdes
2375 struct qib_devdata *dd = ppd->dd; in qib_7322_bringup_serdes()
2385 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn); in qib_7322_bringup_serdes()
2386 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a); in qib_7322_bringup_serdes()
2395 ppd->cpspec->ibdeltainprog = 1; in qib_7322_bringup_serdes()
2396 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd, in qib_7322_bringup_serdes()
2398 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd, in qib_7322_bringup_serdes()
2418 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) << in qib_7322_bringup_serdes()
2420 ppd->cpspec->ibcctrl_a = ibc; /* without linkcmd or linkinitcmd! */ in qib_7322_bringup_serdes()
2428 if (!ppd->cpspec->ibcctrl_b) { in qib_7322_bringup_serdes()
2429 unsigned lse = ppd->link_speed_enabled; in qib_7322_bringup_serdes()
2432 * Not on re-init after reset, establish shadow in qib_7322_bringup_serdes()
2435 ppd->cpspec->ibcctrl_b = qib_read_kreg_port(ppd, in qib_7322_bringup_serdes()
2437 ppd->cpspec->ibcctrl_b &= ~(IBA7322_IBC_SPEED_QDR | in qib_7322_bringup_serdes()
2442 if (lse & (lse - 1)) /* Muliple speeds enabled */ in qib_7322_bringup_serdes()
2443 ppd->cpspec->ibcctrl_b |= in qib_7322_bringup_serdes()
2448 ppd->cpspec->ibcctrl_b |= (lse == QIB_IB_QDR) ? in qib_7322_bringup_serdes()
2454 if ((ppd->link_width_enabled & (IB_WIDTH_1X | IB_WIDTH_4X)) == in qib_7322_bringup_serdes()
2456 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_WIDTH_AUTONEG; in qib_7322_bringup_serdes()
2458 ppd->cpspec->ibcctrl_b |= in qib_7322_bringup_serdes()
2459 ppd->link_width_enabled == IB_WIDTH_4X ? in qib_7322_bringup_serdes()
2464 ppd->cpspec->ibcctrl_b |= (IBA7322_IBC_RXPOL_MASK | in qib_7322_bringup_serdes()
2467 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b); in qib_7322_bringup_serdes()
2477 guid = be64_to_cpu(ppd->guid); in qib_7322_bringup_serdes()
2479 if (dd->base_guid) in qib_7322_bringup_serdes()
2480 guid = be64_to_cpu(dd->base_guid) + ppd->port - 1; in qib_7322_bringup_serdes()
2481 ppd->guid = cpu_to_be64(guid); in qib_7322_bringup_serdes()
2485 /* write to chip to prevent back-to-back writes of ibc reg */ in qib_7322_bringup_serdes()
2489 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, IBLinkEn); in qib_7322_bringup_serdes()
2493 val = ppd->cpspec->ibcctrl_a | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE << in qib_7322_bringup_serdes()
2498 ppd->cpspec->ibcctrl_a = val & ~SYM_MASK(IBCCtrlA_0, LinkInitCmd); in qib_7322_bringup_serdes()
2501 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in qib_7322_bringup_serdes()
2502 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvIBPortEnable); in qib_7322_bringup_serdes()
2503 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl); in qib_7322_bringup_serdes()
2504 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in qib_7322_bringup_serdes()
2516 * qib_7322_quiet_serdes - set serdes to txidle
2527 spin_lock_irqsave(&ppd->lflags_lock, flags); in qib_7322_mini_quiet_serdes()
2528 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG; in qib_7322_mini_quiet_serdes()
2529 spin_unlock_irqrestore(&ppd->lflags_lock, flags); in qib_7322_mini_quiet_serdes()
2530 wake_up(&ppd->cpspec->autoneg_wait); in qib_7322_mini_quiet_serdes()
2531 cancel_delayed_work_sync(&ppd->cpspec->autoneg_work); in qib_7322_mini_quiet_serdes()
2532 if (ppd->dd->cspec->r1) in qib_7322_mini_quiet_serdes()
2533 cancel_delayed_work_sync(&ppd->cpspec->ipg_work); in qib_7322_mini_quiet_serdes()
2535 ppd->cpspec->chase_end = 0; in qib_7322_mini_quiet_serdes()
2536 if (ppd->cpspec->chase_timer.function) /* if initted */ in qib_7322_mini_quiet_serdes()
2537 del_timer_sync(&ppd->cpspec->chase_timer); in qib_7322_mini_quiet_serdes()
2546 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn); in qib_7322_mini_quiet_serdes()
2553 if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta || in qib_7322_mini_quiet_serdes()
2554 ppd->cpspec->ibdeltainprog || ppd->cpspec->iblnkdowndelta) { in qib_7322_mini_quiet_serdes()
2555 struct qib_devdata *dd = ppd->dd; in qib_7322_mini_quiet_serdes()
2563 if (ppd->cpspec->ibsymdelta || ppd->cpspec->ibdeltainprog) { in qib_7322_mini_quiet_serdes()
2565 if (ppd->cpspec->ibdeltainprog) in qib_7322_mini_quiet_serdes()
2566 val -= val - ppd->cpspec->ibsymsnap; in qib_7322_mini_quiet_serdes()
2567 val -= ppd->cpspec->ibsymdelta; in qib_7322_mini_quiet_serdes()
2570 if (ppd->cpspec->iblnkerrdelta || ppd->cpspec->ibdeltainprog) { in qib_7322_mini_quiet_serdes()
2572 if (ppd->cpspec->ibdeltainprog) in qib_7322_mini_quiet_serdes()
2573 val -= val - ppd->cpspec->iblnkerrsnap; in qib_7322_mini_quiet_serdes()
2574 val -= ppd->cpspec->iblnkerrdelta; in qib_7322_mini_quiet_serdes()
2577 if (ppd->cpspec->iblnkdowndelta) { in qib_7322_mini_quiet_serdes()
2579 val += ppd->cpspec->iblnkdowndelta; in qib_7322_mini_quiet_serdes()
2593 * qib_setup_7322_setextled - set the state of the two external LEDs
2610 * require waking up every 10-20 msecs and checking the counters
2616 struct qib_devdata *dd = ppd->dd; in qib_setup_7322_setextled()
2625 if (dd->diag_client) in qib_setup_7322_setextled()
2629 if (ppd->led_override) { in qib_setup_7322_setextled()
2630 grn = (ppd->led_override & QIB_LED_PHYS); in qib_setup_7322_setextled()
2631 yel = (ppd->led_override & QIB_LED_LOG); in qib_setup_7322_setextled()
2642 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in qib_setup_7322_setextled()
2643 extctl = dd->cspec->extctrl & (ppd->port == 1 ? in qib_setup_7322_setextled()
2646 extctl |= ppd->port == 1 ? ExtLED_IB1_GRN : ExtLED_IB2_GRN; in qib_setup_7322_setextled()
2656 extctl |= ppd->port == 1 ? ExtLED_IB1_YEL : ExtLED_IB2_YEL; in qib_setup_7322_setextled()
2657 dd->cspec->extctrl = extctl; in qib_setup_7322_setextled()
2658 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); in qib_setup_7322_setextled()
2659 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in qib_setup_7322_setextled()
2671 if (dd->flags & QIB_DCA_ENABLED) in qib_7322_notify_dca()
2673 if (!dca_add_requester(&dd->pcidev->dev)) { in qib_7322_notify_dca()
2674 qib_devinfo(dd->pcidev, "DCA enabled\n"); in qib_7322_notify_dca()
2675 dd->flags |= QIB_DCA_ENABLED; in qib_7322_notify_dca()
2680 if (dd->flags & QIB_DCA_ENABLED) { in qib_7322_notify_dca()
2681 dca_remove_requester(&dd->pcidev->dev); in qib_7322_notify_dca()
2682 dd->flags &= ~QIB_DCA_ENABLED; in qib_7322_notify_dca()
2683 dd->cspec->dca_ctrl = 0; in qib_7322_notify_dca()
2685 dd->cspec->dca_ctrl); in qib_7322_notify_dca()
2694 struct qib_devdata *dd = rcd->dd; in qib_update_rhdrq_dca()
2695 struct qib_chip_specific *cspec = dd->cspec; in qib_update_rhdrq_dca()
2697 if (!(dd->flags & QIB_DCA_ENABLED)) in qib_update_rhdrq_dca()
2699 if (cspec->rhdr_cpu[rcd->ctxt] != cpu) { in qib_update_rhdrq_dca()
2702 cspec->rhdr_cpu[rcd->ctxt] = cpu; in qib_update_rhdrq_dca()
2703 rmp = &dca_rcvhdr_reg_map[rcd->ctxt]; in qib_update_rhdrq_dca()
2704 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] &= rmp->mask; in qib_update_rhdrq_dca()
2705 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] |= in qib_update_rhdrq_dca()
2706 (u64) dca3_get_tag(&dd->pcidev->dev, cpu) << rmp->lsb; in qib_update_rhdrq_dca()
2707 qib_devinfo(dd->pcidev, in qib_update_rhdrq_dca()
2708 "Ctxt %d cpu %d dca %llx\n", rcd->ctxt, cpu, in qib_update_rhdrq_dca()
2709 (long long) cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]); in qib_update_rhdrq_dca()
2710 qib_write_kreg(dd, rmp->regno, in qib_update_rhdrq_dca()
2711 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]); in qib_update_rhdrq_dca()
2712 cspec->dca_ctrl |= SYM_MASK(DCACtrlA, RcvHdrqDCAEnable); in qib_update_rhdrq_dca()
2713 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl); in qib_update_rhdrq_dca()
2719 struct qib_devdata *dd = ppd->dd; in qib_update_sdma_dca()
2720 struct qib_chip_specific *cspec = dd->cspec; in qib_update_sdma_dca()
2721 unsigned pidx = ppd->port - 1; in qib_update_sdma_dca()
2723 if (!(dd->flags & QIB_DCA_ENABLED)) in qib_update_sdma_dca()
2725 if (cspec->sdma_cpu[pidx] != cpu) { in qib_update_sdma_dca()
2726 cspec->sdma_cpu[pidx] = cpu; in qib_update_sdma_dca()
2727 cspec->dca_rcvhdr_ctrl[4] &= ~(ppd->hw_pidx ? in qib_update_sdma_dca()
2730 cspec->dca_rcvhdr_ctrl[4] |= in qib_update_sdma_dca()
2731 (u64) dca3_get_tag(&dd->pcidev->dev, cpu) << in qib_update_sdma_dca()
2732 (ppd->hw_pidx ? in qib_update_sdma_dca()
2735 qib_devinfo(dd->pcidev, in qib_update_sdma_dca()
2736 "sdma %d cpu %d dca %llx\n", ppd->hw_pidx, cpu, in qib_update_sdma_dca()
2737 (long long) cspec->dca_rcvhdr_ctrl[4]); in qib_update_sdma_dca()
2739 cspec->dca_rcvhdr_ctrl[4]); in qib_update_sdma_dca()
2740 cspec->dca_ctrl |= ppd->hw_pidx ? in qib_update_sdma_dca()
2743 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl); in qib_update_sdma_dca()
2749 struct qib_chip_specific *cspec = dd->cspec; in qib_setup_dca()
2752 for (i = 0; i < ARRAY_SIZE(cspec->rhdr_cpu); i++) in qib_setup_dca()
2753 cspec->rhdr_cpu[i] = -1; in qib_setup_dca()
2754 for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++) in qib_setup_dca()
2755 cspec->sdma_cpu[i] = -1; in qib_setup_dca()
2756 cspec->dca_rcvhdr_ctrl[0] = in qib_setup_dca()
2761 cspec->dca_rcvhdr_ctrl[1] = in qib_setup_dca()
2766 cspec->dca_rcvhdr_ctrl[2] = in qib_setup_dca()
2771 cspec->dca_rcvhdr_ctrl[3] = in qib_setup_dca()
2776 cspec->dca_rcvhdr_ctrl[4] = in qib_setup_dca()
2779 for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++) in qib_setup_dca()
2781 cspec->dca_rcvhdr_ctrl[i]); in qib_setup_dca()
2782 for (i = 0; i < cspec->num_msix_entries; i++) in qib_setup_dca()
2793 if (n->rcv) { in qib_irq_notifier_notify()
2794 struct qib_ctxtdata *rcd = (struct qib_ctxtdata *)n->arg; in qib_irq_notifier_notify()
2798 struct qib_pportdata *ppd = (struct qib_pportdata *)n->arg; in qib_irq_notifier_notify()
2810 if (n->rcv) { in qib_irq_notifier_release()
2811 struct qib_ctxtdata *rcd = (struct qib_ctxtdata *)n->arg; in qib_irq_notifier_release()
2813 dd = rcd->dd; in qib_irq_notifier_release()
2815 struct qib_pportdata *ppd = (struct qib_pportdata *)n->arg; in qib_irq_notifier_release()
2817 dd = ppd->dd; in qib_irq_notifier_release()
2819 qib_devinfo(dd->pcidev, in qib_irq_notifier_release()
2830 dd->cspec->main_int_mask = ~0ULL; in qib_7322_free_irq()
2832 for (i = 0; i < dd->cspec->num_msix_entries; i++) { in qib_7322_free_irq()
2834 if (dd->cspec->msix_entries[i].arg) { in qib_7322_free_irq()
2838 irq_set_affinity_hint(pci_irq_vector(dd->pcidev, i), in qib_7322_free_irq()
2840 free_cpumask_var(dd->cspec->msix_entries[i].mask); in qib_7322_free_irq()
2841 pci_free_irq(dd->pcidev, i, in qib_7322_free_irq()
2842 dd->cspec->msix_entries[i].arg); in qib_7322_free_irq()
2847 if (!dd->cspec->num_msix_entries) in qib_7322_free_irq()
2848 pci_free_irq(dd->pcidev, 0, dd); in qib_7322_free_irq()
2850 dd->cspec->num_msix_entries = 0; in qib_7322_free_irq()
2852 pci_free_irq_vectors(dd->pcidev); in qib_7322_free_irq()
2865 if (dd->flags & QIB_DCA_ENABLED) { in qib_setup_7322_cleanup()
2866 dca_remove_requester(&dd->pcidev->dev); in qib_setup_7322_cleanup()
2867 dd->flags &= ~QIB_DCA_ENABLED; in qib_setup_7322_cleanup()
2868 dd->cspec->dca_ctrl = 0; in qib_setup_7322_cleanup()
2869 qib_write_kreg(dd, KREG_IDX(DCACtrlA), dd->cspec->dca_ctrl); in qib_setup_7322_cleanup()
2874 kfree(dd->cspec->cntrs); in qib_setup_7322_cleanup()
2875 kfree(dd->cspec->sendchkenable); in qib_setup_7322_cleanup()
2876 kfree(dd->cspec->sendgrhchk); in qib_setup_7322_cleanup()
2877 kfree(dd->cspec->sendibchk); in qib_setup_7322_cleanup()
2878 kfree(dd->cspec->msix_entries); in qib_setup_7322_cleanup()
2879 for (i = 0; i < dd->num_pports; i++) { in qib_setup_7322_cleanup()
2884 kfree(dd->pport[i].cpspec->portcntrs); in qib_setup_7322_cleanup()
2885 if (dd->flags & QIB_HAS_QSFP) { in qib_setup_7322_cleanup()
2886 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in qib_setup_7322_cleanup()
2887 dd->cspec->gpio_mask &= ~mask; in qib_setup_7322_cleanup()
2888 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); in qib_setup_7322_cleanup()
2889 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in qib_setup_7322_cleanup()
2897 struct qib_pportdata *ppd0 = &dd->pport[0]; in sdma_7322_intr()
2898 struct qib_pportdata *ppd1 = &dd->pport[1]; in sdma_7322_intr()
2922 spin_lock_irqsave(&dd->sendctrl_lock, flags); in qib_wantpiobuf_7322_intr()
2924 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail); in qib_wantpiobuf_7322_intr()
2926 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail); in qib_wantpiobuf_7322_intr()
2927 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl); in qib_wantpiobuf_7322_intr()
2929 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in qib_wantpiobuf_7322_intr()
2935 * keep mainline interrupt handler cache-friendly
2946 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills)); in unknown_7322_ibits()
2949 /* keep mainline interrupt handler cache-friendly */
2966 * have a bad side-effect on some diagnostic that wanted in unknown_7322_gpio_intr()
2967 * to poll for a status-change, but the various shadows in unknown_7322_gpio_intr()
2976 for (pidx = 0; pidx < dd->num_pports && (dd->flags & QIB_HAS_QSFP); in unknown_7322_gpio_intr()
2982 if (!dd->pport[pidx].link_speed_supported) in unknown_7322_gpio_intr()
2985 ppd = dd->pport + pidx; in unknown_7322_gpio_intr()
2986 mask <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx); in unknown_7322_gpio_intr()
2987 if (gpiostatus & dd->cspec->gpio_mask & mask) { in unknown_7322_gpio_intr()
2990 qd = &ppd->cpspec->qsfp_data; in unknown_7322_gpio_intr()
2996 qd->t_insert = jiffies; in unknown_7322_gpio_intr()
2997 queue_work(ib_wq, &qd->work); in unknown_7322_gpio_intr()
3009 dd->cspec->gpio_mask &= ~gpio_irq; in unknown_7322_gpio_intr()
3010 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); in unknown_7322_gpio_intr()
3026 tasklet_schedule(&dd->error_tasklet); in unlikely_7322_intr()
3028 if (istat & INT_MASK_P(Err, 0) && dd->rcd[0]) in unlikely_7322_intr()
3029 handle_7322_p_errors(dd->rcd[0]->ppd); in unlikely_7322_intr()
3030 if (istat & INT_MASK_P(Err, 1) && dd->rcd[1]) in unlikely_7322_intr()
3031 handle_7322_p_errors(dd->rcd[1]->ppd); in unlikely_7322_intr()
3040 struct qib_devdata *dd = rcd->dd; in adjust_rcv_timeout()
3041 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt]; in adjust_rcv_timeout()
3054 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout; in adjust_rcv_timeout()
3055 qib_write_kreg(dd, kr_rcvavailtimeout + rcd->ctxt, timeout); in adjust_rcv_timeout()
3076 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) { in qib_7322intr()
3097 istat &= dd->cspec->main_int_mask; in qib_7322intr()
3104 this_cpu_inc(*dd->int_counter); in qib_7322intr()
3115 * the queue, and will re-interrupt if necessary. The processor in qib_7322intr()
3129 for (i = 0; i < dd->first_user_ctxt; i++) { in qib_7322intr()
3132 if (dd->rcd[i]) in qib_7322intr()
3133 qib_kreceive(dd->rcd[i], NULL, &npkts); in qib_7322intr()
3147 if ((istat & QIB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED)) in qib_7322intr()
3161 struct qib_devdata *dd = rcd->dd; in qib_7322pintr()
3164 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) in qib_7322pintr()
3173 this_cpu_inc(*dd->int_counter); in qib_7322pintr()
3177 (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt); in qib_7322pintr()
3191 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) in qib_7322bufavail()
3200 this_cpu_inc(*dd->int_counter); in qib_7322bufavail()
3206 if (dd->flags & QIB_INITTED) in qib_7322bufavail()
3220 struct qib_devdata *dd = ppd->dd; in sdma_intr()
3222 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) in sdma_intr()
3231 this_cpu_inc(*dd->int_counter); in sdma_intr()
3234 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? in sdma_intr()
3247 struct qib_devdata *dd = ppd->dd; in sdma_idle_intr()
3249 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) in sdma_idle_intr()
3258 this_cpu_inc(*dd->int_counter); in sdma_idle_intr()
3261 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? in sdma_idle_intr()
3274 struct qib_devdata *dd = ppd->dd; in sdma_progress_intr()
3276 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) in sdma_progress_intr()
3285 this_cpu_inc(*dd->int_counter); in sdma_progress_intr()
3288 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? in sdma_progress_intr()
3302 struct qib_devdata *dd = ppd->dd; in sdma_cleanup_intr()
3304 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) in sdma_cleanup_intr()
3313 this_cpu_inc(*dd->int_counter); in sdma_cleanup_intr()
3316 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ? in sdma_cleanup_intr()
3328 if (!dd->cspec->msix_entries[msixnum].dca) in reset_dca_notifier()
3331 qib_devinfo(dd->pcidev, "Disabling notifier on HCA %d irq %d\n", in reset_dca_notifier()
3332 dd->unit, pci_irq_vector(dd->pcidev, msixnum)); in reset_dca_notifier()
3333 irq_set_affinity_notifier(pci_irq_vector(dd->pcidev, msixnum), NULL); in reset_dca_notifier()
3334 dd->cspec->msix_entries[msixnum].notifier = NULL; in reset_dca_notifier()
3339 struct qib_msix_entry *m = &dd->cspec->msix_entries[msixnum]; in setup_dca_notifier()
3342 if (!m->dca) in setup_dca_notifier()
3348 m->notifier = n; in setup_dca_notifier()
3349 n->notify.irq = pci_irq_vector(dd->pcidev, msixnum); in setup_dca_notifier()
3350 n->notify.notify = qib_irq_notifier_notify; in setup_dca_notifier()
3351 n->notify.release = qib_irq_notifier_release; in setup_dca_notifier()
3352 n->arg = m->arg; in setup_dca_notifier()
3353 n->rcv = m->rcv; in setup_dca_notifier()
3354 qib_devinfo(dd->pcidev, in setup_dca_notifier()
3356 n->notify.irq, n->rcv, &n->notify); in setup_dca_notifier()
3358 n->notify.irq, in setup_dca_notifier()
3359 &n->notify); in setup_dca_notifier()
3361 m->notifier = NULL; in setup_dca_notifier()
3370 * Set up our chip-specific interrupt handler.
3385 if (!dd->num_pports) in qib_setup_7322_interrupt()
3407 if (!dd->cspec->num_msix_entries) { in qib_setup_7322_interrupt()
3410 ret = pci_request_irq(dd->pcidev, 0, qib_7322intr, NULL, dd, in qib_setup_7322_interrupt()
3416 pci_irq_vector(dd->pcidev, 0), ret); in qib_setup_7322_interrupt()
3419 dd->cspec->main_int_mask = ~0ULL; in qib_setup_7322_interrupt()
3427 local_mask = cpumask_of_pcibus(dd->pcidev->bus); in qib_setup_7322_interrupt()
3440 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) { in qib_setup_7322_interrupt()
3449 /* skip if for a non-configured port */ in qib_setup_7322_interrupt()
3450 if (irq_table[i].port > dd->num_pports) in qib_setup_7322_interrupt()
3452 arg = dd->pport + irq_table[i].port - 1; in qib_setup_7322_interrupt()
3460 ret = pci_request_irq(dd->pcidev, msixnum, handler, in qib_setup_7322_interrupt()
3462 dd->unit, in qib_setup_7322_interrupt()
3467 ctxt = i - ARRAY_SIZE(irq_table); in qib_setup_7322_interrupt()
3469 arg = dd->rcd[ctxt]; in qib_setup_7322_interrupt()
3479 ret = pci_request_irq(dd->pcidev, msixnum, handler, in qib_setup_7322_interrupt()
3482 dd->unit); in qib_setup_7322_interrupt()
3493 pci_irq_vector(dd->pcidev, msixnum), in qib_setup_7322_interrupt()
3496 pci_alloc_irq_vectors(dd->pcidev, 1, 1, in qib_setup_7322_interrupt()
3500 dd->cspec->msix_entries[msixnum].arg = arg; in qib_setup_7322_interrupt()
3502 dd->cspec->msix_entries[msixnum].dca = dca; in qib_setup_7322_interrupt()
3503 dd->cspec->msix_entries[msixnum].rcv = in qib_setup_7322_interrupt()
3517 &dd->cspec->msix_entries[msixnum].mask, in qib_setup_7322_interrupt()
3521 dd->cspec->msix_entries[msixnum].mask); in qib_setup_7322_interrupt()
3528 dd->cspec->msix_entries[msixnum].mask); in qib_setup_7322_interrupt()
3531 pci_irq_vector(dd->pcidev, msixnum), in qib_setup_7322_interrupt()
3532 dd->cspec->msix_entries[msixnum].mask); in qib_setup_7322_interrupt()
3539 dd->cspec->main_int_mask = mask; in qib_setup_7322_interrupt()
3540 tasklet_setup(&dd->error_tasklet, qib_error_tasklet); in qib_setup_7322_interrupt()
3544 * qib_7322_boardname - fill in the board name and note features
3551 /* Will need enumeration of board-types here */ in qib_7322_boardname()
3555 boardid = SYM_FIELD(dd->revision, Revision, BoardID); in qib_7322_boardname()
3559 dd->boardname = "InfiniPath_QLE7342_Emulation"; in qib_7322_boardname()
3562 dd->boardname = "InfiniPath_QLE7340"; in qib_7322_boardname()
3563 dd->flags |= QIB_HAS_QSFP; in qib_7322_boardname()
3567 dd->boardname = "InfiniPath_QLE7342"; in qib_7322_boardname()
3568 dd->flags |= QIB_HAS_QSFP; in qib_7322_boardname()
3571 dd->boardname = "InfiniPath_QMI7342"; in qib_7322_boardname()
3574 dd->boardname = "InfiniPath_Unsupported7342"; in qib_7322_boardname()
3579 dd->boardname = "InfiniPath_QMH7342"; in qib_7322_boardname()
3583 dd->boardname = "InfiniPath_QME7342"; in qib_7322_boardname()
3586 dd->boardname = "InfiniPath_QME7362"; in qib_7322_boardname()
3587 dd->flags |= QIB_HAS_QSFP; in qib_7322_boardname()
3590 dd->boardname = "Intel IB QDR 1P FLR-QSFP Adptr"; in qib_7322_boardname()
3591 dd->flags |= QIB_HAS_QSFP; in qib_7322_boardname()
3594 dd->boardname = "InfiniPath_QLE7342_TEST"; in qib_7322_boardname()
3595 dd->flags |= QIB_HAS_QSFP; in qib_7322_boardname()
3598 dd->boardname = "InfiniPath_QLE73xy_UNKNOWN"; in qib_7322_boardname()
3602 dd->board_atten = 1; /* index into txdds_Xdr */ in qib_7322_boardname()
3604 snprintf(dd->boardversion, sizeof(dd->boardversion), in qib_7322_boardname()
3606 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname, in qib_7322_boardname()
3607 (unsigned int)SYM_FIELD(dd->revision, Revision_R, Arch), in qib_7322_boardname()
3608 dd->majrev, dd->minrev, in qib_7322_boardname()
3609 (unsigned int)SYM_FIELD(dd->revision, Revision_R, SW)); in qib_7322_boardname()
3612 qib_devinfo(dd->pcidev, in qib_7322_boardname()
3614 dd->unit); in qib_7322_boardname()
3635 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit); in qib_do_7322_reset()
3639 msix_entries = dd->cspec->num_msix_entries; in qib_do_7322_reset()
3641 /* no interrupts till re-initted */ in qib_do_7322_reset()
3648 msix_vecsave = kmalloc_array(2 * dd->cspec->num_msix_entries, in qib_do_7322_reset()
3674 dd->pport->cpspec->ibdeltainprog = 0; in qib_do_7322_reset()
3675 dd->pport->cpspec->ibsymdelta = 0; in qib_do_7322_reset()
3676 dd->pport->cpspec->iblnkerrdelta = 0; in qib_do_7322_reset()
3677 dd->pport->cpspec->ibmalfdelta = 0; in qib_do_7322_reset()
3679 dd->z_int_counter = qib_int_counter(dd); in qib_do_7322_reset()
3686 dd->flags &= ~(QIB_INITTED | QIB_PRESENT | QIB_BADINTR); in qib_do_7322_reset()
3687 dd->flags |= QIB_DOING_RESET; in qib_do_7322_reset()
3688 val = dd->control | QLOGIC_IB_C_RESET; in qib_do_7322_reset()
3689 writeq(val, &dd->kregbase[kr_control]); in qib_do_7322_reset()
3705 val = readq(&dd->kregbase[kr_revision]); in qib_do_7322_reset()
3706 if (val == dd->revision) in qib_do_7322_reset()
3716 dd->flags |= QIB_PRESENT; /* it's back */ in qib_do_7322_reset()
3733 for (i = 0; i < dd->num_pports; ++i) in qib_do_7322_reset()
3734 write_7322_init_portregs(&dd->pport[i]); in qib_do_7322_reset()
3737 if (qib_pcie_params(dd, dd->lbus_width, &msix_entries)) in qib_do_7322_reset()
3741 dd->cspec->num_msix_entries = msix_entries; in qib_do_7322_reset()
3744 for (i = 0; i < dd->num_pports; ++i) { in qib_do_7322_reset()
3745 struct qib_pportdata *ppd = &dd->pport[i]; in qib_do_7322_reset()
3747 spin_lock_irqsave(&ppd->lflags_lock, flags); in qib_do_7322_reset()
3748 ppd->lflags |= QIBL_IB_FORCE_NOTIFY; in qib_do_7322_reset()
3749 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED; in qib_do_7322_reset()
3750 spin_unlock_irqrestore(&ppd->lflags_lock, flags); in qib_do_7322_reset()
3754 dd->flags &= ~QIB_DOING_RESET; /* OK or not, no longer resetting */ in qib_do_7322_reset()
3760 * qib_7322_put_tid - write a TID to the chip
3769 if (!(dd->flags & QIB_PRESENT)) in qib_7322_put_tid()
3771 if (pa != dd->tidinvalid) { in qib_7322_put_tid()
3788 chippa |= dd->tidtemplate; in qib_7322_put_tid()
3797 * qib_7322_clear_tids - clear all TID entries for a ctxt, expected and eager
3812 if (!dd->kregbase || !rcd) in qib_7322_clear_tids()
3815 ctxt = rcd->ctxt; in qib_7322_clear_tids()
3817 tidinv = dd->tidinvalid; in qib_7322_clear_tids()
3819 ((char __iomem *) dd->kregbase + in qib_7322_clear_tids()
3820 dd->rcvtidbase + in qib_7322_clear_tids()
3821 ctxt * dd->rcvtidcnt * sizeof(*tidbase)); in qib_7322_clear_tids()
3823 for (i = 0; i < dd->rcvtidcnt; i++) in qib_7322_clear_tids()
3828 ((char __iomem *) dd->kregbase + in qib_7322_clear_tids()
3829 dd->rcvegrbase + in qib_7322_clear_tids()
3830 rcd->rcvegr_tid_base * sizeof(*tidbase)); in qib_7322_clear_tids()
3832 for (i = 0; i < rcd->rcvegrcnt; i++) in qib_7322_clear_tids()
3838 * qib_7322_tidtemplate - setup constants for TID updates
3854 if (dd->rcvegrbufsize == 2048) in qib_7322_tidtemplate()
3855 dd->tidtemplate = IBA7322_TID_SZ_2K; in qib_7322_tidtemplate()
3856 else if (dd->rcvegrbufsize == 4096) in qib_7322_tidtemplate()
3857 dd->tidtemplate = IBA7322_TID_SZ_4K; in qib_7322_tidtemplate()
3858 dd->tidinvalid = 0; in qib_7322_tidtemplate()
3862 * qib_init_7322_get_base_info - set chip-specific flags for user code
3873 kinfo->spi_runtime_flags |= QIB_RUNTIME_CTXT_MSB_IN_QP | in qib_7322_get_base_info()
3876 if (rcd->dd->cspec->r1) in qib_7322_get_base_info()
3877 kinfo->spi_runtime_flags |= QIB_RUNTIME_RCHK; in qib_7322_get_base_info()
3878 if (rcd->dd->flags & QIB_USE_SPCL_TRIG) in qib_7322_get_base_info()
3879 kinfo->spi_runtime_flags |= QIB_RUNTIME_SPECIAL_TRIGGER; in qib_7322_get_base_info()
3890 (rhf_addr - dd->rhf_offset + offset); in qib_7322_get_msgheader()
3902 dd->cspec->numctxts = nchipctxts; in qib_7322_config_ctxts()
3903 if (qib_n_krcv_queues > 1 && dd->num_pports) { in qib_7322_config_ctxts()
3904 dd->first_user_ctxt = NUM_IB_PORTS + in qib_7322_config_ctxts()
3905 (qib_n_krcv_queues - 1) * dd->num_pports; in qib_7322_config_ctxts()
3906 if (dd->first_user_ctxt > nchipctxts) in qib_7322_config_ctxts()
3907 dd->first_user_ctxt = nchipctxts; in qib_7322_config_ctxts()
3908 dd->n_krcv_queues = dd->first_user_ctxt / dd->num_pports; in qib_7322_config_ctxts()
3910 dd->first_user_ctxt = NUM_IB_PORTS; in qib_7322_config_ctxts()
3911 dd->n_krcv_queues = 1; in qib_7322_config_ctxts()
3915 int nctxts = dd->first_user_ctxt + num_online_cpus(); in qib_7322_config_ctxts()
3918 dd->ctxtcnt = 6; in qib_7322_config_ctxts()
3920 dd->ctxtcnt = 10; in qib_7322_config_ctxts()
3922 dd->ctxtcnt = nchipctxts; in qib_7322_config_ctxts()
3923 } else if (qib_cfgctxts < dd->num_pports) in qib_7322_config_ctxts()
3924 dd->ctxtcnt = dd->num_pports; in qib_7322_config_ctxts()
3926 dd->ctxtcnt = qib_cfgctxts; in qib_7322_config_ctxts()
3927 if (!dd->ctxtcnt) /* none of the above, set to max */ in qib_7322_config_ctxts()
3928 dd->ctxtcnt = nchipctxts; in qib_7322_config_ctxts()
3935 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in qib_7322_config_ctxts()
3936 if (dd->ctxtcnt > 10) in qib_7322_config_ctxts()
3937 dd->rcvctrl |= 2ULL << SYM_LSB(RcvCtrl, ContextCfg); in qib_7322_config_ctxts()
3938 else if (dd->ctxtcnt > 6) in qib_7322_config_ctxts()
3939 dd->rcvctrl |= 1ULL << SYM_LSB(RcvCtrl, ContextCfg); in qib_7322_config_ctxts()
3943 dd->rcvctrl |= 5ULL << SYM_LSB(RcvCtrl, XrcTypeCode); in qib_7322_config_ctxts()
3949 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl); in qib_7322_config_ctxts()
3950 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in qib_7322_config_ctxts()
3953 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt); in qib_7322_config_ctxts()
3955 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt); in qib_7322_config_ctxts()
3957 dd->rcvhdrcnt = 2 * max(dd->cspec->rcvegrcnt, in qib_7322_config_ctxts()
3958 dd->num_pports > 1 ? 1024U : 2048U); in qib_7322_config_ctxts()
3965 u64 maskr; /* right-justified mask */ in qib_7322_get_ib_cfg()
3969 case QIB_IB_CFG_LWID_ENB: /* Get allowed Link-width */ in qib_7322_get_ib_cfg()
3970 ret = ppd->link_width_enabled; in qib_7322_get_ib_cfg()
3973 case QIB_IB_CFG_LWID: /* Get currently active Link-width */ in qib_7322_get_ib_cfg()
3974 ret = ppd->link_width_active; in qib_7322_get_ib_cfg()
3978 ret = ppd->link_speed_enabled; in qib_7322_get_ib_cfg()
3982 ret = ppd->link_speed_active; in qib_7322_get_ib_cfg()
3985 case QIB_IB_CFG_RXPOL_ENB: /* Get Auto-RX-polarity enable */ in qib_7322_get_ib_cfg()
3990 case QIB_IB_CFG_LREV_ENB: /* Get Auto-Lane-reversal enable */ in qib_7322_get_ib_cfg()
4001 ret = ppd->vls_operational; in qib_7322_get_ib_cfg()
4013 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0, in qib_7322_get_ib_cfg()
4018 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0, in qib_7322_get_ib_cfg()
4024 ret = (ppd->cpspec->ibcctrl_a & in qib_7322_get_ib_cfg()
4039 if (ppd->link_speed_active == QIB_IB_QDR) in qib_7322_get_ib_cfg()
4041 else if (ppd->link_speed_active == QIB_IB_DDR) in qib_7322_get_ib_cfg()
4048 ret = -EINVAL; in qib_7322_get_ib_cfg()
4051 ret = (int)((ppd->cpspec->ibcctrl_b >> lsb) & maskr); in qib_7322_get_ib_cfg()
4066 struct qib_devdata *dd = ppd->dd; in qib_7322_set_ib_cfg()
4067 u64 maskr; /* right-justified mask */ in qib_7322_set_ib_cfg()
4075 * Set LID and LMC. Combined to avoid possible hazard in qib_7322_set_ib_cfg()
4081 * For header-checking, the SLID in the packet will in qib_7322_set_ib_cfg()
4085 * false-positives. in qib_7322_set_ib_cfg()
4093 case QIB_IB_CFG_LWID_ENB: /* set allowed Link-width */ in qib_7322_set_ib_cfg()
4094 ppd->link_width_enabled = val; in qib_7322_set_ib_cfg()
4114 ppd->link_speed_enabled = val; in qib_7322_set_ib_cfg()
4118 if (val & (val - 1)) { in qib_7322_set_ib_cfg()
4122 spin_lock_irqsave(&ppd->lflags_lock, flags); in qib_7322_set_ib_cfg()
4123 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED; in qib_7322_set_ib_cfg()
4124 spin_unlock_irqrestore(&ppd->lflags_lock, flags); in qib_7322_set_ib_cfg()
4131 case QIB_IB_CFG_RXPOL_ENB: /* set Auto-RX-polarity enable */ in qib_7322_set_ib_cfg()
4136 case QIB_IB_CFG_LREV_ENB: /* set Auto-Lane-reversal enable */ in qib_7322_set_ib_cfg()
4142 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0, in qib_7322_set_ib_cfg()
4145 ppd->cpspec->ibcctrl_a &= in qib_7322_set_ib_cfg()
4147 ppd->cpspec->ibcctrl_a |= (u64) val << in qib_7322_set_ib_cfg()
4150 ppd->cpspec->ibcctrl_a); in qib_7322_set_ib_cfg()
4156 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0, in qib_7322_set_ib_cfg()
4159 ppd->cpspec->ibcctrl_a &= in qib_7322_set_ib_cfg()
4161 ppd->cpspec->ibcctrl_a |= (u64) val << in qib_7322_set_ib_cfg()
4164 ppd->cpspec->ibcctrl_a); in qib_7322_set_ib_cfg()
4170 maskr = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) | in qib_7322_set_ib_cfg()
4171 ((u64) ppd->pkeys[2] << 32) | in qib_7322_set_ib_cfg()
4172 ((u64) ppd->pkeys[3] << 48); in qib_7322_set_ib_cfg()
4179 ppd->cpspec->ibcctrl_a &= in qib_7322_set_ib_cfg()
4182 ppd->cpspec->ibcctrl_a |= in qib_7322_set_ib_cfg()
4184 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a); in qib_7322_set_ib_cfg()
4196 val = (ppd->ibmaxlen >> 2) + 1; in qib_7322_set_ib_cfg()
4197 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, MaxPktLen); in qib_7322_set_ib_cfg()
4198 ppd->cpspec->ibcctrl_a |= (u64)val << in qib_7322_set_ib_cfg()
4201 ppd->cpspec->ibcctrl_a); in qib_7322_set_ib_cfg()
4209 ppd->cpspec->ibmalfusesnap = 1; in qib_7322_set_ib_cfg()
4210 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd, in qib_7322_set_ib_cfg()
4212 if (!ppd->cpspec->ibdeltainprog && in qib_7322_set_ib_cfg()
4214 ppd->cpspec->ibdeltainprog = 1; in qib_7322_set_ib_cfg()
4215 ppd->cpspec->ibsymsnap = in qib_7322_set_ib_cfg()
4218 ppd->cpspec->iblnkerrsnap = in qib_7322_set_ib_cfg()
4226 if (ppd->cpspec->ibmalfusesnap) { in qib_7322_set_ib_cfg()
4227 ppd->cpspec->ibmalfusesnap = 0; in qib_7322_set_ib_cfg()
4228 ppd->cpspec->ibmalfdelta += in qib_7322_set_ib_cfg()
4230 crp_errlink) - in qib_7322_set_ib_cfg()
4231 ppd->cpspec->ibmalfsnap; in qib_7322_set_ib_cfg()
4240 ret = -EINVAL; in qib_7322_set_ib_cfg()
4241 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16); in qib_7322_set_ib_cfg()
4259 ppd->cpspec->chase_end = 0; in qib_7322_set_ib_cfg()
4264 if (ppd->cpspec->chase_timer.expires) { in qib_7322_set_ib_cfg()
4265 del_timer_sync(&ppd->cpspec->chase_timer); in qib_7322_set_ib_cfg()
4266 ppd->cpspec->chase_timer.expires = 0; in qib_7322_set_ib_cfg()
4271 ret = -EINVAL; in qib_7322_set_ib_cfg()
4272 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n", in qib_7322_set_ib_cfg()
4280 if (ppd->vls_operational != val) { in qib_7322_set_ib_cfg()
4281 ppd->vls_operational = val; in qib_7322_set_ib_cfg()
4292 ret = -EINVAL; in qib_7322_set_ib_cfg()
4301 if (ppd->dd->cspec->r1) { in qib_7322_set_ib_cfg()
4302 cancel_delayed_work(&ppd->cpspec->ipg_work); in qib_7322_set_ib_cfg()
4303 ppd->cpspec->ipg_tries = 0; in qib_7322_set_ib_cfg()
4308 ret = -EINVAL; in qib_7322_set_ib_cfg()
4311 ppd->cpspec->ibcctrl_b &= ~(maskr << lsb); in qib_7322_set_ib_cfg()
4312 ppd->cpspec->ibcctrl_b |= (((u64) val & maskr) << lsb); in qib_7322_set_ib_cfg()
4313 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b); in qib_7322_set_ib_cfg()
4326 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, in qib_7322_set_loopback()
4329 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n", in qib_7322_set_loopback()
4330 ppd->dd->unit, ppd->port); in qib_7322_set_loopback()
4332 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, in qib_7322_set_loopback()
4336 qib_devinfo(ppd->dd->pcidev, in qib_7322_set_loopback()
4338 ppd->dd->unit, ppd->port); in qib_7322_set_loopback()
4340 ret = -EINVAL; in qib_7322_set_loopback()
4343 ppd->cpspec->ibcctrl_a); in qib_7322_set_loopback()
4344 ctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_HRTBT_MASK in qib_7322_set_loopback()
4346 ppd->cpspec->ibcctrl_b = ctrlb | val; in qib_7322_set_loopback()
4348 ppd->cpspec->ibcctrl_b); in qib_7322_set_loopback()
4349 qib_write_kreg(ppd->dd, kr_scratch, 0); in qib_7322_set_loopback()
4362 vl->vl = (val >> SYM_LSB(LowPriority0_0, VirtualLane)) & in get_vl_weights()
4364 vl->weight = (val >> SYM_LSB(LowPriority0_0, Weight)) & in get_vl_weights()
4377 val = ((vl->vl & SYM_RMASK(LowPriority0_0, VirtualLane)) << in set_vl_weights()
4379 ((vl->weight & SYM_RMASK(LowPriority0_0, Weight)) << in set_vl_weights()
4383 if (!(ppd->p_sendctrl & SYM_MASK(SendCtrl_0, IBVLArbiterEn))) { in set_vl_weights()
4384 struct qib_devdata *dd = ppd->dd; in set_vl_weights()
4387 spin_lock_irqsave(&dd->sendctrl_lock, flags); in set_vl_weights()
4388 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, IBVLArbiterEn); in set_vl_weights()
4389 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl); in set_vl_weights()
4391 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in set_vl_weights()
4407 return -EINVAL; in qib_7322_get_ib_table()
4424 return -EINVAL; in qib_7322_set_ib_table()
4439 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt); in qib_update_7322_usrhead()
4440 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); in qib_update_7322_usrhead()
4441 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); in qib_update_7322_usrhead()
4448 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt); in qib_7322_hdrqempty()
4449 if (rcd->rcvhdrtail_kvaddr) in qib_7322_hdrqempty()
4452 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt); in qib_7322_hdrqempty()
4473 * Modify the RCVCTRL register in chip-specific way. This
4475 * location is chip-specifc, but the needed operations are
4476 * generic. <op> is a bit-mask because we often want to
4482 struct qib_devdata *dd = ppd->dd; in rcvctrl_7322_mod()
4487 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in rcvctrl_7322_mod()
4490 dd->rcvctrl |= SYM_MASK(RcvCtrl, TidFlowEnable); in rcvctrl_7322_mod()
4492 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TidFlowEnable); in rcvctrl_7322_mod()
4494 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd); in rcvctrl_7322_mod()
4496 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TailUpd); in rcvctrl_7322_mod()
4498 ppd->p_rcvctrl &= ~SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable); in rcvctrl_7322_mod()
4500 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable); in rcvctrl_7322_mod()
4502 mask = (1ULL << dd->ctxtcnt) - 1; in rcvctrl_7322_mod()
4506 rcd = dd->rcd[ctxt]; in rcvctrl_7322_mod()
4509 ppd->p_rcvctrl |= in rcvctrl_7322_mod()
4511 if (!(dd->flags & QIB_NODMA_RTAIL)) { in rcvctrl_7322_mod()
4513 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd); in rcvctrl_7322_mod()
4517 rcd->rcvhdrqtailaddr_phys); in rcvctrl_7322_mod()
4519 rcd->rcvhdrq_phys); in rcvctrl_7322_mod()
4520 rcd->seq_cnt = 1; in rcvctrl_7322_mod()
4523 ppd->p_rcvctrl &= in rcvctrl_7322_mod()
4526 dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull); in rcvctrl_7322_mod()
4528 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull)); in rcvctrl_7322_mod()
4530 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail)); in rcvctrl_7322_mod()
4532 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail)); in rcvctrl_7322_mod()
4539 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl); in rcvctrl_7322_mod()
4541 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl); in rcvctrl_7322_mod()
4542 if ((op & QIB_RCVCTRL_CTXT_ENB) && dd->rcd[ctxt]) { in rcvctrl_7322_mod()
4555 dd->rcd[ctxt]->head = val; in rcvctrl_7322_mod()
4557 if (ctxt < dd->first_user_ctxt) in rcvctrl_7322_mod()
4558 val |= dd->rhdrhead_intr_off; in rcvctrl_7322_mod()
4561 dd->rcd[ctxt] && dd->rhdrhead_intr_off) { in rcvctrl_7322_mod()
4563 val = dd->rcd[ctxt]->head | dd->rhdrhead_intr_off; in rcvctrl_7322_mod()
4579 for (i = 0; i < dd->cfgctxts; i++) { in rcvctrl_7322_mod()
4589 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in rcvctrl_7322_mod()
4593 * Modify the SENDCTRL register in chip-specific way. This
4596 * The chip doesn't allow back-to-back sendctrl writes, so write
4601 * SEND_ENB and SEND_DIS operate on the per-port ones.
4621 struct qib_devdata *dd = ppd->dd; in sendctrl_7322_mod()
4625 spin_lock_irqsave(&dd->sendctrl_lock, flags); in sendctrl_7322_mod()
4629 dd->sendctrl = 0; in sendctrl_7322_mod()
4631 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd); in sendctrl_7322_mod()
4633 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd); in sendctrl_7322_mod()
4634 if (dd->flags & QIB_USE_SPCL_TRIG) in sendctrl_7322_mod()
4635 dd->sendctrl |= SYM_MASK(SendCtrl, SpecialTriggerEn); in sendctrl_7322_mod()
4640 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable); in sendctrl_7322_mod()
4642 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable); in sendctrl_7322_mod()
4647 tmp_dd_sendctrl = dd->sendctrl; in sendctrl_7322_mod()
4648 last = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS; in sendctrl_7322_mod()
4663 u64 tmp_ppd_sendctrl = ppd->p_sendctrl; in sendctrl_7322_mod()
4677 tmp_dd_sendctrl = dd->sendctrl; in sendctrl_7322_mod()
4684 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd))) in sendctrl_7322_mod()
4693 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl); in sendctrl_7322_mod()
4698 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl); in sendctrl_7322_mod()
4702 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in sendctrl_7322_mod()
4709 * to occur, so in-memory copy is in sync with in sendctrl_7322_mod()
4725 * qib_portcntr_7322 - read a per-port chip counter
4731 struct qib_devdata *dd = ppd->dd; in qib_portcntr_7322()
4774 /* pseudo-counter, summed for all ports */ in qib_portcntr_7322()
4779 qib_devinfo(ppd->dd->pcidev, in qib_portcntr_7322()
4785 /* handle non-counters and special cases first */ in qib_portcntr_7322()
4790 for (i = 0; dd->rcd && i < dd->first_user_ctxt; i++) { in qib_portcntr_7322()
4791 struct qib_ctxtdata *rcd = dd->rcd[i]; in qib_portcntr_7322()
4793 if (!rcd || rcd->ppd != ppd) in qib_portcntr_7322()
4807 /* were counters in older chips, now per-port kernel regs */ in qib_portcntr_7322()
4821 if (ppd->cpspec->ibdeltainprog) in qib_portcntr_7322()
4822 ret -= ret - ppd->cpspec->ibsymsnap; in qib_portcntr_7322()
4823 ret -= ppd->cpspec->ibsymdelta; in qib_portcntr_7322()
4825 if (ppd->cpspec->ibdeltainprog) in qib_portcntr_7322()
4826 ret -= ret - ppd->cpspec->iblnkerrsnap; in qib_portcntr_7322()
4827 ret -= ppd->cpspec->iblnkerrdelta; in qib_portcntr_7322()
4829 ret -= ppd->cpspec->ibmalfdelta; in qib_portcntr_7322()
4831 ret += ppd->cpspec->iblnkdowndelta; in qib_portcntr_7322()
4837 * Device counter names (not port-specific), one line per stat,
4842 * Non-error counters are first.
4902 * same as cntr7322names and cntr7322indices, but for port-specific counters.
4914 "TxDmaDesc\n" /* 7220 and 7322-only */
4915 "E RxDlidFltr\n" /* 7220 and 7322-only */
4938 "RxLclPhyErr\n" /* 7220 and 7322-only from here down */
4942 "RxQPBadCtxt\n" /* 7322-only from here down */
4992 for (i = 0, s = (char *)cntr7322names; s && j <= dd->cfgctxts; in init_7322_cntrnames()
5001 dd->cspec->ncntrs = i; in init_7322_cntrnames()
5004 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1; in init_7322_cntrnames()
5006 dd->cspec->cntrnamelen = 1 + s - cntr7322names; in init_7322_cntrnames()
5007 dd->cspec->cntrs = kmalloc_array(dd->cspec->ncntrs, sizeof(u64), in init_7322_cntrnames()
5012 dd->cspec->nportcntrs = i - 1; in init_7322_cntrnames()
5013 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1; in init_7322_cntrnames()
5014 for (i = 0; i < dd->num_pports; ++i) { in init_7322_cntrnames()
5015 dd->pport[i].cpspec->portcntrs = in init_7322_cntrnames()
5016 kmalloc_array(dd->cspec->nportcntrs, sizeof(u64), in init_7322_cntrnames()
5027 ret = dd->cspec->cntrnamelen; in qib_read_7322cntrs()
5033 u64 *cntr = dd->cspec->cntrs; in qib_read_7322cntrs()
5036 ret = dd->cspec->ncntrs * sizeof(u64); in qib_read_7322cntrs()
5043 for (i = 0; i < dd->cspec->ncntrs; i++) in qib_read_7322cntrs()
5062 ret = dd->cspec->portcntrnamelen; in qib_read_7322portcntrs()
5068 struct qib_pportdata *ppd = &dd->pport[port]; in qib_read_7322portcntrs()
5069 u64 *cntr = ppd->cpspec->portcntrs; in qib_read_7322portcntrs()
5072 ret = dd->cspec->nportcntrs * sizeof(u64); in qib_read_7322portcntrs()
5079 for (i = 0; i < dd->cspec->nportcntrs; i++) { in qib_read_7322portcntrs()
5098 * qib_get_7322_faststats - get word counters from chip before they overflow
5099 * @opaque - contains a pointer to the qlogic_ib device qib_devdata
5104 * which we don;t have, yet, for 7322-based boards.
5116 for (pidx = 0; pidx < dd->num_pports; ++pidx) { in qib_get_7322_faststats()
5117 ppd = dd->pport + pidx; in qib_get_7322_faststats()
5124 if (!ppd->link_speed_supported || !(dd->flags & QIB_INITTED) in qib_get_7322_faststats()
5125 || dd->diag_client) in qib_get_7322_faststats()
5130 * exceeding a threshold, so we need to check the word-counts in qib_get_7322_faststats()
5131 * even if they are 64-bit. in qib_get_7322_faststats()
5135 spin_lock_irqsave(&ppd->dd->eep_st_lock, flags); in qib_get_7322_faststats()
5136 traffic_wds -= ppd->dd->traffic_wds; in qib_get_7322_faststats()
5137 ppd->dd->traffic_wds += traffic_wds; in qib_get_7322_faststats()
5138 spin_unlock_irqrestore(&ppd->dd->eep_st_lock, flags); in qib_get_7322_faststats()
5139 if (ppd->cpspec->qdr_dfe_on && (ppd->link_speed_active & in qib_get_7322_faststats()
5141 (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | in qib_get_7322_faststats()
5143 ppd->cpspec->qdr_dfe_time && in qib_get_7322_faststats()
5144 time_is_before_jiffies(ppd->cpspec->qdr_dfe_time)) { in qib_get_7322_faststats()
5145 ppd->cpspec->qdr_dfe_on = 0; in qib_get_7322_faststats()
5148 ppd->dd->cspec->r1 ? in qib_get_7322_faststats()
5154 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER); in qib_get_7322_faststats()
5162 if (!dd->cspec->num_msix_entries) in qib_7322_intr_fallback()
5165 qib_devinfo(dd->pcidev, in qib_7322_intr_fallback()
5168 if (pci_alloc_irq_vectors(dd->pcidev, 1, 1, PCI_IRQ_LEGACY) < 0) in qib_7322_intr_fallback()
5180 * of cpspec->ibcctrl_a as part of it's operation, so if that changes,
5186 struct qib_devdata *dd = ppd->dd; in qib_7322_mini_pcs_reset()
5193 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop)); in qib_7322_mini_pcs_reset()
5195 ppd->cpspec->ibcctrl_a & in qib_7322_mini_pcs_reset()
5201 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a); in qib_7322_mini_pcs_reset()
5205 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_7322_mini_pcs_reset()
5209 * This code for non-IBTA-compliant IB speed negotiation is only known to
5212 * actual knowledge of the non-compliant speed negotiation.
5213 * It has a number of hard-coded fields, since the hope is to rewrite this
5223 struct qib_devdata *dd = ppd->dd; in autoneg_7322_sendpkt()
5235 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_DIS1, NULL); in autoneg_7322_sendpkt()
5240 if (dd->flags & QIB_USE_SPCL_TRIG) { in autoneg_7322_sendpkt()
5241 u32 spcl_off = (pnum >= dd->piobcnt2k) ? 2047 : 1023; in autoneg_7322_sendpkt()
5248 /* and re-enable hdr check */ in autoneg_7322_sendpkt()
5249 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_ENAB1, NULL); in autoneg_7322_sendpkt()
5257 struct qib_devdata *dd = ppd->dd; in qib_autoneg_7322_send()
5317 newctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_SPEED_MASK | in set_7322_ibspeed_fast()
5321 if (speed & (speed - 1)) /* multiple speeds */ in set_7322_ibspeed_fast()
5331 if (newctrlb == ppd->cpspec->ibcctrl_b) in set_7322_ibspeed_fast()
5334 ppd->cpspec->ibcctrl_b = newctrlb; in set_7322_ibspeed_fast()
5335 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b); in set_7322_ibspeed_fast()
5336 qib_write_kreg(ppd->dd, kr_scratch, 0); in set_7322_ibspeed_fast()
5341 * IB 1.2-compliant device that we think can do DDR.
5343 * 1.2-compliant devices go directly to DDR prior to reaching INIT
5349 spin_lock_irqsave(&ppd->lflags_lock, flags); in try_7322_autoneg()
5350 ppd->lflags |= QIBL_IB_AUTONEG_INPROG; in try_7322_autoneg()
5351 spin_unlock_irqrestore(&ppd->lflags_lock, flags); in try_7322_autoneg()
5356 queue_delayed_work(ib_wq, &ppd->cpspec->autoneg_work, in try_7322_autoneg()
5361 * Handle the empirically determined mechanism for auto-negotiation
5371 autoneg_work.work)->ppd; in autoneg_7322_work()
5378 if (SYM_FIELD(ppd->lastibcstat, IBCStatusA_0, LinkState) in autoneg_7322_work()
5386 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) in autoneg_7322_work()
5390 if (wait_event_timeout(ppd->cpspec->autoneg_wait, in autoneg_7322_work()
5391 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG), in autoneg_7322_work()
5397 if (wait_event_timeout(ppd->cpspec->autoneg_wait, in autoneg_7322_work()
5398 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG), in autoneg_7322_work()
5409 wait_event_timeout(ppd->cpspec->autoneg_wait, in autoneg_7322_work()
5410 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG), in autoneg_7322_work()
5413 if (ppd->lflags & QIBL_IB_AUTONEG_INPROG) { in autoneg_7322_work()
5414 spin_lock_irqsave(&ppd->lflags_lock, flags); in autoneg_7322_work()
5415 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG; in autoneg_7322_work()
5416 if (ppd->cpspec->autoneg_tries == AUTONEG_TRIES) { in autoneg_7322_work()
5417 ppd->lflags |= QIBL_IB_AUTONEG_FAILED; in autoneg_7322_work()
5418 ppd->cpspec->autoneg_tries = 0; in autoneg_7322_work()
5420 spin_unlock_irqrestore(&ppd->lflags_lock, flags); in autoneg_7322_work()
5421 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled); in autoneg_7322_work()
5431 struct qib_ibport *ibp = &ppd->ibport_data; in try_7322_ipg()
5438 agent = ibp->rvp.send_agent; in try_7322_ipg()
5448 if (!ibp->smi_ah) { in try_7322_ipg()
5455 send_buf->ah = ah; in try_7322_ipg()
5456 ibp->smi_ah = ibah_to_rvtah(ah); in try_7322_ipg()
5460 send_buf->ah = &ibp->smi_ah->ibah; in try_7322_ipg()
5464 smp = send_buf->mad; in try_7322_ipg()
5465 smp->base_version = IB_MGMT_BASE_VERSION; in try_7322_ipg()
5466 smp->mgmt_class = IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE; in try_7322_ipg()
5467 smp->class_version = 1; in try_7322_ipg()
5468 smp->method = IB_MGMT_METHOD_SEND; in try_7322_ipg()
5469 smp->hop_cnt = 1; in try_7322_ipg()
5470 smp->attr_id = QIB_VENDOR_IPG; in try_7322_ipg()
5471 smp->attr_mod = 0; in try_7322_ipg()
5478 delay = 2 << ppd->cpspec->ipg_tries; in try_7322_ipg()
5479 queue_delayed_work(ib_wq, &ppd->cpspec->ipg_work, in try_7322_ipg()
5492 ipg_work.work)->ppd; in ipg_7322_work()
5493 if ((ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | QIBL_LINKACTIVE)) in ipg_7322_work()
5494 && ++ppd->cpspec->ipg_tries <= 10) in ipg_7322_work()
5535 spin_lock_irqsave(&ppd->lflags_lock, flags); in qib_7322_ib_updown()
5536 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY; in qib_7322_ib_updown()
5537 spin_unlock_irqrestore(&ppd->lflags_lock, flags); in qib_7322_ib_updown()
5541 ppd->link_speed_active = QIB_IB_QDR; in qib_7322_ib_updown()
5544 ppd->link_speed_active = QIB_IB_DDR; in qib_7322_ib_updown()
5547 ppd->link_speed_active = QIB_IB_SDR; in qib_7322_ib_updown()
5551 ppd->link_width_active = IB_WIDTH_4X; in qib_7322_ib_updown()
5554 ppd->link_width_active = IB_WIDTH_1X; in qib_7322_ib_updown()
5555 ppd->delay_mult = ib_rate_to_delay[mult_to_ib_rate(mult)]; in qib_7322_ib_updown()
5562 ppd->cpspec->ipg_tries = 0; in qib_7322_ib_updown()
5568 if (!(ppd->lflags & (QIBL_IB_AUTONEG_FAILED | in qib_7322_ib_updown()
5570 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled); in qib_7322_ib_updown()
5571 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) { in qib_7322_ib_updown()
5573 &ppd->cpspec->qsfp_data; in qib_7322_ib_updown()
5583 if (ppd->dd->flags & QIB_HAS_QSFP) { in qib_7322_ib_updown()
5584 qd->t_insert = jiffies; in qib_7322_ib_updown()
5585 queue_work(ib_wq, &qd->work); in qib_7322_ib_updown()
5587 spin_lock_irqsave(&ppd->sdma_lock, flags); in qib_7322_ib_updown()
5591 spin_unlock_irqrestore(&ppd->sdma_lock, flags); in qib_7322_ib_updown()
5594 if (clr == ppd->cpspec->iblnkdownsnap) in qib_7322_ib_updown()
5595 ppd->cpspec->iblnkdowndelta++; in qib_7322_ib_updown()
5598 !(ppd->lflags & (QIBL_IB_AUTONEG_FAILED | in qib_7322_ib_updown()
5600 ppd->link_speed_active == QIB_IB_SDR && in qib_7322_ib_updown()
5601 (ppd->link_speed_enabled & QIB_IB_DDR) in qib_7322_ib_updown()
5602 && ppd->cpspec->autoneg_tries < AUTONEG_TRIES) { in qib_7322_ib_updown()
5603 /* we are SDR, and auto-negotiation enabled */ in qib_7322_ib_updown()
5604 ++ppd->cpspec->autoneg_tries; in qib_7322_ib_updown()
5605 if (!ppd->cpspec->ibdeltainprog) { in qib_7322_ib_updown()
5606 ppd->cpspec->ibdeltainprog = 1; in qib_7322_ib_updown()
5607 ppd->cpspec->ibsymdelta += in qib_7322_ib_updown()
5609 crp_ibsymbolerr) - in qib_7322_ib_updown()
5610 ppd->cpspec->ibsymsnap; in qib_7322_ib_updown()
5611 ppd->cpspec->iblnkerrdelta += in qib_7322_ib_updown()
5613 crp_iblinkerrrecov) - in qib_7322_ib_updown()
5614 ppd->cpspec->iblnkerrsnap; in qib_7322_ib_updown()
5618 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) && in qib_7322_ib_updown()
5619 ppd->link_speed_active == QIB_IB_SDR) { in qib_7322_ib_updown()
5625 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) && in qib_7322_ib_updown()
5626 (ppd->link_speed_active & QIB_IB_DDR)) { in qib_7322_ib_updown()
5627 spin_lock_irqsave(&ppd->lflags_lock, flags); in qib_7322_ib_updown()
5628 ppd->lflags &= ~(QIBL_IB_AUTONEG_INPROG | in qib_7322_ib_updown()
5630 spin_unlock_irqrestore(&ppd->lflags_lock, flags); in qib_7322_ib_updown()
5631 ppd->cpspec->autoneg_tries = 0; in qib_7322_ib_updown()
5632 /* re-enable SDR, for next link down */ in qib_7322_ib_updown()
5633 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled); in qib_7322_ib_updown()
5634 wake_up(&ppd->cpspec->autoneg_wait); in qib_7322_ib_updown()
5636 } else if (ppd->lflags & QIBL_IB_AUTONEG_FAILED) { in qib_7322_ib_updown()
5643 spin_lock_irqsave(&ppd->lflags_lock, flags); in qib_7322_ib_updown()
5644 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED; in qib_7322_ib_updown()
5645 spin_unlock_irqrestore(&ppd->lflags_lock, flags); in qib_7322_ib_updown()
5646 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_IBTA_1_2_MASK; in qib_7322_ib_updown()
5649 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) { in qib_7322_ib_updown()
5651 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10) in qib_7322_ib_updown()
5653 if (!ppd->cpspec->recovery_init) in qib_7322_ib_updown()
5655 ppd->cpspec->qdr_dfe_time = jiffies + in qib_7322_ib_updown()
5658 ppd->cpspec->ibmalfusesnap = 0; in qib_7322_ib_updown()
5659 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd, in qib_7322_ib_updown()
5663 ppd->cpspec->iblnkdownsnap = in qib_7322_ib_updown()
5665 if (ppd->cpspec->ibdeltainprog) { in qib_7322_ib_updown()
5666 ppd->cpspec->ibdeltainprog = 0; in qib_7322_ib_updown()
5667 ppd->cpspec->ibsymdelta += read_7322_creg32_port(ppd, in qib_7322_ib_updown()
5668 crp_ibsymbolerr) - ppd->cpspec->ibsymsnap; in qib_7322_ib_updown()
5669 ppd->cpspec->iblnkerrdelta += read_7322_creg32_port(ppd, in qib_7322_ib_updown()
5670 crp_iblinkerrrecov) - ppd->cpspec->iblnkerrsnap; in qib_7322_ib_updown()
5673 !ppd->cpspec->ibdeltainprog && in qib_7322_ib_updown()
5674 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) { in qib_7322_ib_updown()
5675 ppd->cpspec->ibdeltainprog = 1; in qib_7322_ib_updown()
5676 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd, in qib_7322_ib_updown()
5678 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd, in qib_7322_ib_updown()
5703 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in gpio_7322_mod()
5704 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe)); in gpio_7322_mod()
5705 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe)); in gpio_7322_mod()
5706 new_out = (dd->cspec->gpio_out & ~mask) | out; in gpio_7322_mod()
5708 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); in gpio_7322_mod()
5710 dd->cspec->gpio_out = new_out; in gpio_7322_mod()
5711 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in gpio_7322_mod()
5749 dd->palign = qib_read_kreg32(dd, kr_pagealign); in get_7322_chip_params()
5751 dd->uregbase = qib_read_kreg32(dd, kr_userregbase); in get_7322_chip_params()
5753 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt); in get_7322_chip_params()
5754 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase); in get_7322_chip_params()
5755 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase); in get_7322_chip_params()
5756 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase); in get_7322_chip_params()
5757 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff; in get_7322_chip_params()
5760 dd->piobcnt2k = val & ~0U; in get_7322_chip_params()
5761 dd->piobcnt4k = val >> 32; in get_7322_chip_params()
5763 dd->piosize2k = val & ~0U; in get_7322_chip_params()
5764 dd->piosize4k = val >> 32; in get_7322_chip_params()
5767 if (mtu == -1) in get_7322_chip_params()
5769 dd->pport[0].ibmtu = (u32)mtu; in get_7322_chip_params()
5770 dd->pport[1].ibmtu = (u32)mtu; in get_7322_chip_params()
5773 dd->pio2kbase = (u32 __iomem *) in get_7322_chip_params()
5774 ((char __iomem *) dd->kregbase + dd->pio2k_bufbase); in get_7322_chip_params()
5775 dd->pio4kbase = (u32 __iomem *) in get_7322_chip_params()
5776 ((char __iomem *) dd->kregbase + in get_7322_chip_params()
5777 (dd->piobufbase >> 32)); in get_7322_chip_params()
5783 dd->align4k = ALIGN(dd->piosize4k, dd->palign); in get_7322_chip_params()
5785 piobufs = dd->piobcnt4k + dd->piobcnt2k + NUM_VL15_BUFS; in get_7322_chip_params()
5787 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) / in get_7322_chip_params()
5802 dd->cspec->cregbase = (u64 __iomem *)(cregbase + in qib_7322_set_baseaddrs()
5803 (char __iomem *)dd->kregbase); in qib_7322_set_baseaddrs()
5805 dd->egrtidbase = (u64 __iomem *) in qib_7322_set_baseaddrs()
5806 ((char __iomem *) dd->kregbase + dd->rcvegrbase); in qib_7322_set_baseaddrs()
5809 dd->pport[0].cpspec->kpregbase = in qib_7322_set_baseaddrs()
5810 (u64 __iomem *)((char __iomem *)dd->kregbase); in qib_7322_set_baseaddrs()
5811 dd->pport[1].cpspec->kpregbase = in qib_7322_set_baseaddrs()
5812 (u64 __iomem *)(dd->palign + in qib_7322_set_baseaddrs()
5813 (char __iomem *)dd->kregbase); in qib_7322_set_baseaddrs()
5814 dd->pport[0].cpspec->cpregbase = in qib_7322_set_baseaddrs()
5815 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[0], in qib_7322_set_baseaddrs()
5816 kr_counterregbase) + (char __iomem *)dd->kregbase); in qib_7322_set_baseaddrs()
5817 dd->pport[1].cpspec->cpregbase = in qib_7322_set_baseaddrs()
5818 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[1], in qib_7322_set_baseaddrs()
5819 kr_counterregbase) + (char __iomem *)dd->kregbase); in qib_7322_set_baseaddrs()
5823 * This is a fairly special-purpose observer, so we only support
5824 * the port-specific parts of SendCtrl
5851 for (pidx = 0; pidx < dd->num_pports; ++pidx) { in sendctrl_hook()
5855 ppd = dd->pport + pidx; in sendctrl_hook()
5856 if (!ppd->cpspec->kpregbase) in sendctrl_hook()
5859 psptr = ppd->cpspec->kpregbase + krp_sendctrl; in sendctrl_hook()
5860 psoffs = (u32) (psptr - dd->kregbase) * sizeof(*psptr); in sendctrl_hook()
5866 if (pidx >= dd->num_pports) in sendctrl_hook()
5876 spin_lock_irqsave(&dd->sendctrl_lock, flags); in sendctrl_hook()
5881 * reg or shadow. First-cut: read reg, and complain in sendctrl_hook()
5903 sval = ppd->p_sendctrl & ~mask; in sendctrl_hook()
5905 ppd->p_sendctrl = sval; in sendctrl_hook()
5912 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in sendctrl_hook()
5943 ppd = qd->ppd; in qsfp_7322_event()
5944 pwrup = qd->t_insert + in qsfp_7322_event()
5945 msecs_to_jiffies(QSFP_PWR_LAG_MSEC - QSFP_MODPRS_LAG_MSEC); in qsfp_7322_event()
5951 ppd->cpspec->qsfp_data.modpresent = 0; in qsfp_7322_event()
5955 spin_lock_irqsave(&ppd->lflags_lock, flags); in qsfp_7322_event()
5956 ppd->lflags &= ~QIBL_LINKV; in qsfp_7322_event()
5957 spin_unlock_irqrestore(&ppd->lflags_lock, flags); in qsfp_7322_event()
5960 * Some QSFP's not only do not respond until the full power-up in qsfp_7322_event()
5970 ret = qib_refresh_qsfp_cache(ppd, &qd->cache); in qsfp_7322_event()
5978 if (!ret && !ppd->dd->cspec->r1) { in qsfp_7322_event()
5979 if (QSFP_IS_ACTIVE_FAR(qd->cache.tech)) in qsfp_7322_event()
5981 else if (qd->cache.atten[1] >= qib_long_atten && in qsfp_7322_event()
5982 QSFP_IS_CU(qd->cache.tech)) in qsfp_7322_event()
5996 /* The physical link is being re-enabled only when the in qsfp_7322_event()
6000 if (!ppd->cpspec->qsfp_data.modpresent && in qsfp_7322_event()
6001 (ppd->lflags & (QIBL_LINKV | QIBL_IB_LINK_DISABLED))) { in qsfp_7322_event()
6002 ppd->cpspec->qsfp_data.modpresent = 1; in qsfp_7322_event()
6005 spin_lock_irqsave(&ppd->lflags_lock, flags); in qsfp_7322_event()
6006 ppd->lflags |= QIBL_LINKV; in qsfp_7322_event()
6007 spin_unlock_irqrestore(&ppd->lflags_lock, flags); in qsfp_7322_event()
6019 struct qib_qsfp_data *qd = &ppd->cpspec->qsfp_data; in qib_init_7322_qsfp()
6020 struct qib_devdata *dd = ppd->dd; in qib_init_7322_qsfp()
6023 mod_prs_bit <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx); in qib_init_7322_qsfp()
6024 qd->ppd = ppd; in qib_init_7322_qsfp()
6026 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in qib_init_7322_qsfp()
6027 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert)); in qib_init_7322_qsfp()
6028 dd->cspec->gpio_mask |= mod_prs_bit; in qib_init_7322_qsfp()
6029 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); in qib_init_7322_qsfp()
6030 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); in qib_init_7322_qsfp()
6031 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in qib_init_7322_qsfp()
6059 for (pidx = 0; pidx < dd->num_pports; ++pidx) in set_no_qsfp_atten()
6060 dd->pport[pidx].cpspec->no_eep = deflt; in set_no_qsfp_atten()
6101 for (pidx = 0; dd->unit == unit && pidx < dd->num_pports; in set_no_qsfp_atten()
6103 struct qib_pportdata *ppd = &dd->pport[pidx]; in set_no_qsfp_atten()
6105 if (ppd->port != port || !ppd->link_speed_supported) in set_no_qsfp_atten()
6107 ppd->cpspec->no_eep = val; in set_no_qsfp_atten()
6109 ppd->cpspec->h1_val = h1; in set_no_qsfp_atten()
6112 /* Re-enable the physical state machine on mezz boards in set_no_qsfp_atten()
6128 for (pidx = 0; pidx < dd->num_pports; ++pidx) in set_no_qsfp_atten()
6129 if (dd->pport[pidx].link_speed_supported) in set_no_qsfp_atten()
6130 init_txdds_table(&dd->pport[pidx], 0); in set_no_qsfp_atten()
6143 return -ENOSPC; in setup_txselect()
6150 return -EINVAL; in setup_txselect()
6152 strncpy(txselect_list, str, ARRAY_SIZE(txselect_list) - 1); in setup_txselect()
6155 if (dd->deviceid == PCI_DEVICE_ID_QLOGIC_IB_7322) in setup_txselect()
6170 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize); in qib_late_7322_initreg()
6171 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize); in qib_late_7322_initreg()
6172 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt); in qib_late_7322_initreg()
6173 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys); in qib_late_7322_initreg()
6175 if (val != dd->pioavailregs_phys) { in qib_late_7322_initreg()
6178 (unsigned long) dd->pioavailregs_phys, in qib_late_7322_initreg()
6180 ret = -EINVAL; in qib_late_7322_initreg()
6183 n = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS; in qib_late_7322_initreg()
6191 dd->control &= ~QLOGIC_IB_C_SDMAFETCHPRIOEN; in qib_late_7322_initreg()
6192 qib_write_kreg(dd, kr_control, dd->control); in qib_late_7322_initreg()
6200 for (n = 0; n < dd->num_pports; ++n) { in qib_late_7322_initreg()
6201 struct qib_pportdata *ppd = dd->pport + n; in qib_late_7322_initreg()
6206 if (dd->flags & QIB_HAS_QSFP) in qib_late_7322_initreg()
6209 dd->control |= QLOGIC_IB_C_SDMAFETCHPRIOEN; in qib_late_7322_initreg()
6210 qib_write_kreg(dd, kr_control, dd->control); in qib_late_7322_initreg()
6224 * Write the initialization per-port registers that need to be done at
6234 if (!ppd->link_speed_supported) { in write_7322_init_portregs()
6239 qib_write_kreg(ppd->dd, kr_scratch, 0); in write_7322_init_portregs()
6249 val |= (u64)(ppd->vls_supported - 1) << in write_7322_init_portregs()
6270 if (ppd->dd->cspec->r1) in write_7322_init_portregs()
6271 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, ForceCreditUpToDate); in write_7322_init_portregs()
6275 * Write the initialization per-device registers that need to be done at
6277 * of other init procedures called from qib_init.c). Also write per-port
6290 for (pidx = 0; pidx < dd->num_pports; ++pidx) { in write_7322_initregs()
6294 if (dd->n_krcv_queues < 2 || in write_7322_initregs()
6295 !dd->pport[pidx].link_speed_supported) in write_7322_initregs()
6298 ppd = &dd->pport[pidx]; in write_7322_initregs()
6301 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in write_7322_initregs()
6302 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvQPMapEnable); in write_7322_initregs()
6303 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in write_7322_initregs()
6308 if (dd->num_pports > 1) in write_7322_initregs()
6309 n = dd->first_user_ctxt / dd->num_pports; in write_7322_initregs()
6311 n = dd->first_user_ctxt - 1; in write_7322_initregs()
6315 if (dd->num_pports > 1) in write_7322_initregs()
6316 ctxt = (i % n) * dd->num_pports + pidx; in write_7322_initregs()
6320 ctxt = ppd->hw_pidx; in write_7322_initregs()
6338 for (i = 0; i < dd->first_user_ctxt; i++) { in write_7322_initregs()
6339 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout; in write_7322_initregs()
6349 for (i = 0; i < dd->cfgctxts; i++) { in write_7322_initregs()
6361 if (dd->num_pports) in write_7322_initregs()
6362 setup_7322_link_recovery(dd->pport, dd->num_pports > 1); in write_7322_initregs()
6375 dd->pport = ppd; in qib_init_7322_variables()
6379 dd->cspec = (struct qib_chip_specific *)(ppd + 2); in qib_init_7322_variables()
6381 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1); in qib_init_7322_variables()
6383 ppd[0].cpspec->ppd = &ppd[0]; /* for autoneg_7322_work() */ in qib_init_7322_variables()
6384 ppd[1].cpspec->ppd = &ppd[1]; /* for autoneg_7322_work() */ in qib_init_7322_variables()
6386 spin_lock_init(&dd->cspec->rcvmod_lock); in qib_init_7322_variables()
6387 spin_lock_init(&dd->cspec->gpio_lock); in qib_init_7322_variables()
6390 dd->revision = readq(&dd->kregbase[kr_revision]); in qib_init_7322_variables()
6392 if ((dd->revision & 0xffffffffU) == 0xffffffffU) { in qib_init_7322_variables()
6395 ret = -ENODEV; in qib_init_7322_variables()
6398 dd->flags |= QIB_PRESENT; /* now register routines work */ in qib_init_7322_variables()
6400 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMajor); in qib_init_7322_variables()
6401 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMinor); in qib_init_7322_variables()
6402 dd->cspec->r1 = dd->minrev == 1; in qib_init_7322_variables()
6408 sbufcnt = dd->piobcnt2k + dd->piobcnt4k + in qib_init_7322_variables()
6409 NUM_VL15_BUFS + BITS_PER_LONG - 1; in qib_init_7322_variables()
6411 dd->cspec->sendchkenable = in qib_init_7322_variables()
6412 kmalloc_array(sbufcnt, sizeof(*dd->cspec->sendchkenable), in qib_init_7322_variables()
6414 dd->cspec->sendgrhchk = in qib_init_7322_variables()
6415 kmalloc_array(sbufcnt, sizeof(*dd->cspec->sendgrhchk), in qib_init_7322_variables()
6417 dd->cspec->sendibchk = in qib_init_7322_variables()
6418 kmalloc_array(sbufcnt, sizeof(*dd->cspec->sendibchk), in qib_init_7322_variables()
6420 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk || in qib_init_7322_variables()
6421 !dd->cspec->sendibchk) { in qib_init_7322_variables()
6422 ret = -ENOMEM; in qib_init_7322_variables()
6426 ppd = dd->pport; in qib_init_7322_variables()
6432 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM; in qib_init_7322_variables()
6433 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM; in qib_init_7322_variables()
6434 dd->twsi_eeprom_dev = QIB_TWSI_EEPROM_DEV; in qib_init_7322_variables()
6436 dd->flags |= QIB_HAS_INTX | QIB_HAS_LINK_LATENCY | in qib_init_7322_variables()
6440 dd->flags |= qib_special_trigger ? in qib_init_7322_variables()
6450 if (mtu == -1) in qib_init_7322_variables()
6453 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT; in qib_init_7322_variables()
6455 dd->cspec->hwerrmask = ~0ULL; in qib_init_7322_variables()
6458 dd->cspec->hwerrmask &= in qib_init_7322_variables()
6464 struct qib_chippport_specific *cp = ppd->cpspec; in qib_init_7322_variables()
6466 ppd->link_speed_supported = features & PORT_SPD_CAP; in qib_init_7322_variables()
6468 if (!ppd->link_speed_supported) { in qib_init_7322_variables()
6470 dd->skip_kctxt_mask |= 1 << pidx; in qib_init_7322_variables()
6476 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask, in qib_init_7322_variables()
6480 dd->cspec->int_enable_mask &= ~( in qib_init_7322_variables()
6491 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask, in qib_init_7322_variables()
6495 dd->cspec->int_enable_mask &= ~( in qib_init_7322_variables()
6506 dd->num_pports++; in qib_init_7322_variables()
6507 ret = qib_init_pportdata(ppd, dd, pidx, dd->num_pports); in qib_init_7322_variables()
6509 dd->num_pports--; in qib_init_7322_variables()
6513 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X; in qib_init_7322_variables()
6514 ppd->link_width_enabled = IB_WIDTH_4X; in qib_init_7322_variables()
6515 ppd->link_speed_enabled = ppd->link_speed_supported; in qib_init_7322_variables()
6520 ppd->link_width_active = IB_WIDTH_4X; in qib_init_7322_variables()
6521 ppd->link_speed_active = QIB_IB_SDR; in qib_init_7322_variables()
6522 ppd->delay_mult = ib_rate_to_delay[IB_RATE_10_GBPS]; in qib_init_7322_variables()
6525 ppd->vls_supported = IB_VL_VL0; in qib_init_7322_variables()
6528 ppd->vls_supported = IB_VL_VL0_1; in qib_init_7322_variables()
6531 qib_devinfo(dd->pcidev, in qib_init_7322_variables()
6537 ppd->vls_supported = IB_VL_VL0_3; in qib_init_7322_variables()
6541 ppd->vls_supported = IB_VL_VL0_7; in qib_init_7322_variables()
6543 qib_devinfo(dd->pcidev, in qib_init_7322_variables()
6546 ppd->vls_supported = IB_VL_VL0_3; in qib_init_7322_variables()
6551 ppd->vls_operational = ppd->vls_supported; in qib_init_7322_variables()
6553 init_waitqueue_head(&cp->autoneg_wait); in qib_init_7322_variables()
6554 INIT_DELAYED_WORK(&cp->autoneg_work, in qib_init_7322_variables()
6556 if (ppd->dd->cspec->r1) in qib_init_7322_variables()
6557 INIT_DELAYED_WORK(&cp->ipg_work, ipg_7322_work); in qib_init_7322_variables()
6562 * in adapter-specific routines. in qib_init_7322_variables()
6564 if (!(dd->flags & QIB_HAS_QSFP)) { in qib_init_7322_variables()
6566 qib_devinfo(dd->pcidev, in qib_init_7322_variables()
6568 dd->unit, ppd->port); in qib_init_7322_variables()
6569 cp->h1_val = IS_QMH(dd) ? H1_FORCE_QMH : H1_FORCE_QME; in qib_init_7322_variables()
6574 ppd->cpspec->no_eep = IS_QMH(dd) ? in qib_init_7322_variables()
6577 cp->h1_val = H1_FORCE_VAL; in qib_init_7322_variables()
6583 timer_setup(&cp->chase_timer, reenable_chase, 0); in qib_init_7322_variables()
6588 dd->rcvhdrentsize = qib_rcvhdrentsize ? in qib_init_7322_variables()
6590 dd->rcvhdrsize = qib_rcvhdrsize ? in qib_init_7322_variables()
6592 dd->rhf_offset = dd->rcvhdrentsize - sizeof(u64) / sizeof(u32); in qib_init_7322_variables()
6595 dd->rcvegrbufsize = max(mtu, 2048); in qib_init_7322_variables()
6596 dd->rcvegrbufsize_shift = ilog2(dd->rcvegrbufsize); in qib_init_7322_variables()
6604 dd->rhdrhead_intr_off = in qib_init_7322_variables()
6608 timer_setup(&dd->stats_timer, qib_get_7322_faststats, 0); in qib_init_7322_variables()
6610 dd->ureg_align = 0x10000; /* 64KB alignment */ in qib_init_7322_variables()
6612 dd->piosize2kmax_dwords = dd->piosize2k >> 2; in qib_init_7322_variables()
6620 * interrupt-flushed store buffers, so we need in qib_init_7322_variables()
6629 vl15off = dd->physaddr + (dd->piobufbase >> 32) + in qib_init_7322_variables()
6630 dd->piobcnt4k * dd->align4k; in qib_init_7322_variables()
6631 dd->piovl15base = ioremap(vl15off, in qib_init_7322_variables()
6632 NUM_VL15_BUFS * dd->align4k); in qib_init_7322_variables()
6633 if (!dd->piovl15base) { in qib_init_7322_variables()
6634 ret = -ENOMEM; in qib_init_7322_variables()
6643 if (!dd->num_pports) { in qib_init_7322_variables()
6664 if (dd->flags & QIB_HAS_SEND_DMA) { in qib_init_7322_variables()
6665 dd->cspec->sdmabufcnt = dd->piobcnt4k; in qib_init_7322_variables()
6668 dd->cspec->sdmabufcnt = 0; in qib_init_7322_variables()
6669 sbufs = dd->piobcnt4k; in qib_init_7322_variables()
6671 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k - in qib_init_7322_variables()
6672 dd->cspec->sdmabufcnt; in qib_init_7322_variables()
6673 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs; in qib_init_7322_variables()
6674 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */ in qib_init_7322_variables()
6675 dd->last_pio = dd->cspec->lastbuf_for_pio; in qib_init_7322_variables()
6676 dd->pbufsctxt = (dd->cfgctxts > dd->first_user_ctxt) ? in qib_init_7322_variables()
6677 dd->lastctxt_piobuf / (dd->cfgctxts - dd->first_user_ctxt) : 0; in qib_init_7322_variables()
6685 if (dd->pbufsctxt >= 2 && dd->pbufsctxt - 2 < updthresh) in qib_init_7322_variables()
6686 updthresh = dd->pbufsctxt - 2; in qib_init_7322_variables()
6687 dd->cspec->updthresh_dflt = updthresh; in qib_init_7322_variables()
6688 dd->cspec->updthresh = updthresh; in qib_init_7322_variables()
6691 dd->sendctrl |= ((updthresh & SYM_RMASK(SendCtrl, AvailUpdThld)) in qib_init_7322_variables()
6695 dd->psxmitwait_supported = 1; in qib_init_7322_variables()
6696 dd->psxmitwait_check_rate = QIB_7322_PSXMITWAIT_CHECK_RATE; in qib_init_7322_variables()
6698 if (!dd->ctxtcnt) in qib_init_7322_variables()
6699 dd->ctxtcnt = 1; /* for other initialization code */ in qib_init_7322_variables()
6708 struct qib_devdata *dd = ppd->dd; in qib_7322_getsendbuf()
6712 first = dd->piobcnt2k + dd->piobcnt4k + ppd->hw_pidx; in qib_7322_getsendbuf()
6715 if ((plen + 1) > dd->piosize2kmax_dwords) in qib_7322_getsendbuf()
6716 first = dd->piobcnt2k; in qib_7322_getsendbuf()
6719 last = dd->cspec->lastbuf_for_pio; in qib_7322_getsendbuf()
6747 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6751 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6755 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6761 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6765 /* get bufuse bits, clear them, and print them again if non-zero */ in dump_sdma_7322_state()
6773 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6780 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6785 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6789 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6793 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6797 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6801 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6805 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6809 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6813 qib_dev_porterr(ppd->dd, ppd->port, in dump_sdma_7322_state()
6868 ppd->sdma_state.set_state_action = sdma_7322_action_table; in qib_7322_sdma_init_early()
6873 struct qib_devdata *dd = ppd->dd; in init_sdma_7322_regs()
6878 qib_write_kreg_port(ppd, krp_senddmabase, ppd->sdma_descq_phys); in init_sdma_7322_regs()
6883 qib_write_kreg_port(ppd, krp_senddmaheadaddr, ppd->sdma_head_phys); in init_sdma_7322_regs()
6885 if (dd->num_pports) in init_sdma_7322_regs()
6886 n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */ in init_sdma_7322_regs()
6888 n = dd->cspec->sdmabufcnt; /* failsafe for init */ in init_sdma_7322_regs()
6889 erstbuf = (dd->piobcnt2k + dd->piobcnt4k) - in init_sdma_7322_regs()
6890 ((dd->num_pports == 1 || ppd->port == 2) ? n : in init_sdma_7322_regs()
6891 dd->cspec->sdmabufcnt); in init_sdma_7322_regs()
6894 ppd->sdma_state.first_sendbuf = erstbuf; in init_sdma_7322_regs()
6895 ppd->sdma_state.last_sendbuf = lastbuf; in init_sdma_7322_regs()
6898 unsigned bit = erstbuf & (BITS_PER_LONG - 1); in init_sdma_7322_regs()
6911 struct qib_devdata *dd = ppd->dd; in qib_sdma_7322_gethead()
6920 (dd->flags & QIB_HAS_SDMA_TIMEOUT); in qib_sdma_7322_gethead()
6923 (u16) le64_to_cpu(*ppd->sdma_head_dma) : in qib_sdma_7322_gethead()
6926 swhead = ppd->sdma_descq_head; in qib_sdma_7322_gethead()
6927 swtail = ppd->sdma_descq_tail; in qib_sdma_7322_gethead()
6928 cnt = ppd->sdma_descq_cnt; in qib_sdma_7322_gethead()
6973 u8 snd_mult = ppd->delay_mult; in qib_7322_setpbc_control()
6984 ret |= ((u32)(ppd->hw_pidx)) << PBC_PORT_SEL_LSB; in qib_7322_setpbc_control()
6990 * Enable the per-port VL15 send buffers for use.
7000 vl15bufs = dd->piobcnt2k + dd->piobcnt4k; in qib_7322_initvl15_bufs()
7007 if (rcd->ctxt < NUM_IB_PORTS) { in qib_7322_init_ctxt()
7008 if (rcd->dd->num_pports > 1) { in qib_7322_init_ctxt()
7009 rcd->rcvegrcnt = KCTXT0_EGRCNT / 2; in qib_7322_init_ctxt()
7010 rcd->rcvegr_tid_base = rcd->ctxt ? rcd->rcvegrcnt : 0; in qib_7322_init_ctxt()
7012 rcd->rcvegrcnt = KCTXT0_EGRCNT; in qib_7322_init_ctxt()
7013 rcd->rcvegr_tid_base = 0; in qib_7322_init_ctxt()
7016 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt; in qib_7322_init_ctxt()
7017 rcd->rcvegr_tid_base = KCTXT0_EGRCNT + in qib_7322_init_ctxt()
7018 (rcd->ctxt - NUM_IB_PORTS) * rcd->rcvegrcnt; in qib_7322_init_ctxt()
7027 const int last = start + len - 1; in qib_7322_txchk_change()
7035 int cstart, previ = -1; in qib_7322_txchk_change()
7050 le64_to_cpu(dd->pioavailregs_dma[i]); in qib_7322_txchk_change()
7065 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP); in qib_7322_txchk_change()
7077 clear_bit(i, dd->cspec->sendchkenable); in qib_7322_txchk_change()
7089 set_bit(i, dd->cspec->sendchkenable); in qib_7322_txchk_change()
7095 set_bit(i, dd->cspec->sendibchk); in qib_7322_txchk_change()
7096 clear_bit(i, dd->cspec->sendgrhchk); in qib_7322_txchk_change()
7098 spin_lock_irqsave(&dd->uctxt_lock, flags); in qib_7322_txchk_change()
7100 for (i = dd->first_user_ctxt; in qib_7322_txchk_change()
7101 dd->cspec->updthresh != dd->cspec->updthresh_dflt in qib_7322_txchk_change()
7102 && i < dd->cfgctxts; i++) in qib_7322_txchk_change()
7103 if (dd->rcd[i] && dd->rcd[i]->subctxt_cnt && in qib_7322_txchk_change()
7104 ((dd->rcd[i]->piocnt / dd->rcd[i]->subctxt_cnt) - 1) in qib_7322_txchk_change()
7105 < dd->cspec->updthresh_dflt) in qib_7322_txchk_change()
7107 spin_unlock_irqrestore(&dd->uctxt_lock, flags); in qib_7322_txchk_change()
7108 if (i == dd->cfgctxts) { in qib_7322_txchk_change()
7109 spin_lock_irqsave(&dd->sendctrl_lock, flags); in qib_7322_txchk_change()
7110 dd->cspec->updthresh = dd->cspec->updthresh_dflt; in qib_7322_txchk_change()
7111 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld); in qib_7322_txchk_change()
7112 dd->sendctrl |= (dd->cspec->updthresh & in qib_7322_txchk_change()
7115 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in qib_7322_txchk_change()
7116 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP); in qib_7322_txchk_change()
7123 clear_bit(i, dd->cspec->sendibchk); in qib_7322_txchk_change()
7124 set_bit(i, dd->cspec->sendgrhchk); in qib_7322_txchk_change()
7126 spin_lock_irqsave(&dd->sendctrl_lock, flags); in qib_7322_txchk_change()
7127 if (rcd && rcd->subctxt_cnt && ((rcd->piocnt in qib_7322_txchk_change()
7128 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) { in qib_7322_txchk_change()
7129 dd->cspec->updthresh = (rcd->piocnt / in qib_7322_txchk_change()
7130 rcd->subctxt_cnt) - 1; in qib_7322_txchk_change()
7131 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld); in qib_7322_txchk_change()
7132 dd->sendctrl |= (dd->cspec->updthresh & in qib_7322_txchk_change()
7135 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in qib_7322_txchk_change()
7136 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP); in qib_7322_txchk_change()
7138 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in qib_7322_txchk_change()
7147 dd->cspec->sendchkenable[i]); in qib_7322_txchk_change()
7151 dd->cspec->sendgrhchk[i]); in qib_7322_txchk_change()
7153 dd->cspec->sendibchk[i]); in qib_7322_txchk_change()
7173 return -ENXIO; in qib_7322_tempsense_rd()
7177 * qib_init_iba7322_funcs - set up the chip-specific function pointers
7185 * chip-specific function pointers for later use.
7201 dd->f_bringup_serdes = qib_7322_bringup_serdes; in qib_init_iba7322_funcs()
7202 dd->f_cleanup = qib_setup_7322_cleanup; in qib_init_iba7322_funcs()
7203 dd->f_clear_tids = qib_7322_clear_tids; in qib_init_iba7322_funcs()
7204 dd->f_free_irq = qib_7322_free_irq; in qib_init_iba7322_funcs()
7205 dd->f_get_base_info = qib_7322_get_base_info; in qib_init_iba7322_funcs()
7206 dd->f_get_msgheader = qib_7322_get_msgheader; in qib_init_iba7322_funcs()
7207 dd->f_getsendbuf = qib_7322_getsendbuf; in qib_init_iba7322_funcs()
7208 dd->f_gpio_mod = gpio_7322_mod; in qib_init_iba7322_funcs()
7209 dd->f_eeprom_wen = qib_7322_eeprom_wen; in qib_init_iba7322_funcs()
7210 dd->f_hdrqempty = qib_7322_hdrqempty; in qib_init_iba7322_funcs()
7211 dd->f_ib_updown = qib_7322_ib_updown; in qib_init_iba7322_funcs()
7212 dd->f_init_ctxt = qib_7322_init_ctxt; in qib_init_iba7322_funcs()
7213 dd->f_initvl15_bufs = qib_7322_initvl15_bufs; in qib_init_iba7322_funcs()
7214 dd->f_intr_fallback = qib_7322_intr_fallback; in qib_init_iba7322_funcs()
7215 dd->f_late_initreg = qib_late_7322_initreg; in qib_init_iba7322_funcs()
7216 dd->f_setpbc_control = qib_7322_setpbc_control; in qib_init_iba7322_funcs()
7217 dd->f_portcntr = qib_portcntr_7322; in qib_init_iba7322_funcs()
7218 dd->f_put_tid = qib_7322_put_tid; in qib_init_iba7322_funcs()
7219 dd->f_quiet_serdes = qib_7322_mini_quiet_serdes; in qib_init_iba7322_funcs()
7220 dd->f_rcvctrl = rcvctrl_7322_mod; in qib_init_iba7322_funcs()
7221 dd->f_read_cntrs = qib_read_7322cntrs; in qib_init_iba7322_funcs()
7222 dd->f_read_portcntrs = qib_read_7322portcntrs; in qib_init_iba7322_funcs()
7223 dd->f_reset = qib_do_7322_reset; in qib_init_iba7322_funcs()
7224 dd->f_init_sdma_regs = init_sdma_7322_regs; in qib_init_iba7322_funcs()
7225 dd->f_sdma_busy = qib_sdma_7322_busy; in qib_init_iba7322_funcs()
7226 dd->f_sdma_gethead = qib_sdma_7322_gethead; in qib_init_iba7322_funcs()
7227 dd->f_sdma_sendctrl = qib_7322_sdma_sendctrl; in qib_init_iba7322_funcs()
7228 dd->f_sdma_set_desc_cnt = qib_sdma_set_7322_desc_cnt; in qib_init_iba7322_funcs()
7229 dd->f_sdma_update_tail = qib_sdma_update_7322_tail; in qib_init_iba7322_funcs()
7230 dd->f_sendctrl = sendctrl_7322_mod; in qib_init_iba7322_funcs()
7231 dd->f_set_armlaunch = qib_set_7322_armlaunch; in qib_init_iba7322_funcs()
7232 dd->f_set_cntr_sample = qib_set_cntr_7322_sample; in qib_init_iba7322_funcs()
7233 dd->f_iblink_state = qib_7322_iblink_state; in qib_init_iba7322_funcs()
7234 dd->f_ibphys_portstate = qib_7322_phys_portstate; in qib_init_iba7322_funcs()
7235 dd->f_get_ib_cfg = qib_7322_get_ib_cfg; in qib_init_iba7322_funcs()
7236 dd->f_set_ib_cfg = qib_7322_set_ib_cfg; in qib_init_iba7322_funcs()
7237 dd->f_set_ib_loopback = qib_7322_set_loopback; in qib_init_iba7322_funcs()
7238 dd->f_get_ib_table = qib_7322_get_ib_table; in qib_init_iba7322_funcs()
7239 dd->f_set_ib_table = qib_7322_set_ib_table; in qib_init_iba7322_funcs()
7240 dd->f_set_intr_state = qib_7322_set_intr_state; in qib_init_iba7322_funcs()
7241 dd->f_setextled = qib_setup_7322_setextled; in qib_init_iba7322_funcs()
7242 dd->f_txchk_change = qib_7322_txchk_change; in qib_init_iba7322_funcs()
7243 dd->f_update_usrhead = qib_update_7322_usrhead; in qib_init_iba7322_funcs()
7244 dd->f_wantpiobuf_intr = qib_wantpiobuf_7322_intr; in qib_init_iba7322_funcs()
7245 dd->f_xgxs_reset = qib_7322_mini_pcs_reset; in qib_init_iba7322_funcs()
7246 dd->f_sdma_hw_clean_up = qib_7322_sdma_hw_clean_up; in qib_init_iba7322_funcs()
7247 dd->f_sdma_hw_start_up = qib_7322_sdma_hw_start_up; in qib_init_iba7322_funcs()
7248 dd->f_sdma_init_early = qib_7322_sdma_init_early; in qib_init_iba7322_funcs()
7249 dd->f_writescratch = writescratch; in qib_init_iba7322_funcs()
7250 dd->f_tempsense_rd = qib_7322_tempsense_rd; in qib_init_iba7322_funcs()
7252 dd->f_notify_dca = qib_7322_notify_dca; in qib_init_iba7322_funcs()
7264 /* initialize chip-specific variables */ in qib_init_iba7322_funcs()
7269 if (qib_mini_init || !dd->num_pports) in qib_init_iba7322_funcs()
7278 tabsize = dd->first_user_ctxt + ARRAY_SIZE(irq_table); in qib_init_iba7322_funcs()
7281 irq_table[i].port <= dd->num_pports) || in qib_init_iba7322_funcs()
7283 dd->rcd[i - ARRAY_SIZE(irq_table)])) in qib_init_iba7322_funcs()
7287 actual_cnt -= dd->num_pports; in qib_init_iba7322_funcs()
7290 dd->cspec->msix_entries = kcalloc(tabsize, in qib_init_iba7322_funcs()
7293 if (!dd->cspec->msix_entries) in qib_init_iba7322_funcs()
7300 dd->cspec->num_msix_entries = tabsize; in qib_init_iba7322_funcs()
7308 if (!dca_add_requester(&pdev->dev)) { in qib_init_iba7322_funcs()
7309 qib_devinfo(dd->pcidev, "DCA enabled\n"); in qib_init_iba7322_funcs()
7310 dd->flags |= QIB_DCA_ENABLED; in qib_init_iba7322_funcs()
7346 struct qib_devdata *dd = ppd->dd; in set_txdds()
7350 /* Get correct offset in chip-space, and in source table */ in set_txdds()
7357 if (ppd->hw_pidx) in set_txdds()
7358 regidx += (dd->palign / sizeof(u64)); in set_txdds()
7360 pack_ent = tp->amp << DDS_ENT_AMP_LSB; in set_txdds()
7361 pack_ent |= tp->main << DDS_ENT_MAIN_LSB; in set_txdds()
7362 pack_ent |= tp->pre << DDS_ENT_PRE_LSB; in set_txdds()
7363 pack_ent |= tp->post << DDS_ENT_POST_LSB; in set_txdds()
7365 /* Prevent back-to-back writes by hitting scratch */ in set_txdds()
7366 qib_write_kreg(ppd->dd, kr_scratch, 0); in set_txdds()
7379 { 0x00, 0x90, 0x65 }, "FCBG410QB1C03-QL",
7383 { 0x00, 0x90, 0x65 }, "FCBG410QB1C30-QL",
7391 { 0x00, 0x21, 0x77 }, "QSN3300-1 ",
7395 { 0x00, 0x21, 0x77 }, "QSN3300-2 ",
7399 { 0x00, 0x21, 0x77 }, "QSN3800-1 ",
7403 { 0x00, 0x21, 0x77 }, "QSN3800-3 ",
7407 { 0x00, 0x21, 0x77 }, "QSN7000-5 ",
7411 { 0x00, 0x21, 0x77 }, "QSN7000-7 ",
7415 { 0x00, 0x21, 0x77 }, "QSN7600-5 ",
7419 { 0x00, 0x21, 0x77 }, "QSN7600-7 ",
7447 { 0x00, 0x09, 0x3A }, "74763-0025 ",
7451 { 0x00, 0x09, 0x3A }, "74757-2201 ",
7604 atten = TXDDS_TABLE_SZ - 1; in get_atten_table()
7606 atten--; in get_atten_table()
7619 struct qib_qsfp_cache *qd = &ppd->cpspec->qsfp_data.cache; in find_best_ent()
7626 if (!memcmp(v->oui, qd->oui, QSFP_VOUI_LEN) && in find_best_ent()
7627 (!v->partnum || in find_best_ent()
7628 !memcmp(v->partnum, qd->partnum, QSFP_PN_LEN))) { in find_best_ent()
7629 *sdr_dds = &v->sdr; in find_best_ent()
7630 *ddr_dds = &v->ddr; in find_best_ent()
7631 *qdr_dds = &v->qdr; in find_best_ent()
7638 if (!override && QSFP_IS_ACTIVE(qd->tech)) { in find_best_ent()
7639 *sdr_dds = txdds_sdr + ppd->dd->board_atten; in find_best_ent()
7640 *ddr_dds = txdds_ddr + ppd->dd->board_atten; in find_best_ent()
7641 *qdr_dds = txdds_qdr + ppd->dd->board_atten; in find_best_ent()
7645 if (!override && QSFP_HAS_ATTEN(qd->tech) && (qd->atten[0] || in find_best_ent()
7646 qd->atten[1])) { in find_best_ent()
7647 *sdr_dds = get_atten_table(txdds_sdr, qd->atten[0]); in find_best_ent()
7648 *ddr_dds = get_atten_table(txdds_ddr, qd->atten[0]); in find_best_ent()
7649 *qdr_dds = get_atten_table(txdds_qdr, qd->atten[1]); in find_best_ent()
7651 } else if (ppd->cpspec->no_eep < TXDDS_TABLE_SZ) { in find_best_ent()
7658 idx = ppd->cpspec->no_eep; in find_best_ent()
7662 } else if (ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)) { in find_best_ent()
7664 idx = ppd->cpspec->no_eep - TXDDS_TABLE_SZ; in find_best_ent()
7668 } else if ((IS_QME(ppd->dd) || IS_QMH(ppd->dd)) && in find_best_ent()
7669 ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + in find_best_ent()
7671 idx = ppd->cpspec->no_eep - (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ); in find_best_ent()
7673 ppd->dd->unit, ppd->port, idx); in find_best_ent()
7695 if (!(ppd->dd->flags & QIB_HAS_QSFP) || override) in init_txdds_table()
7702 if (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | in init_txdds_table()
7704 dds = (struct txdds_ent *)(ppd->link_speed_active == in init_txdds_table()
7706 (ppd->link_speed_active == in init_txdds_table()
7760 sz_mask = (1UL << ((quad == 1) ? 32 : 16)) - 1; in ahb_mod()
7776 /* Re-read in case host split reads and read data first */ in ahb_mod()
7809 struct qib_devdata *dd = ppd->dd; in ibsd_wr_allchans()
7813 ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr, in ibsd_wr_allchans()
7815 ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr, in ibsd_wr_allchans()
7827 ppd->dd->unit, ppd->port); in serdes_7322_los_enable()
7831 ppd->dd->unit, ppd->port); in serdes_7322_los_enable()
7841 if (ppd->dd->cspec->r1) in serdes_7322_init()
7873 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT; in serdes_7322_init_old()
7877 le_val = IS_QME(ppd->dd) ? 0 : 1; in serdes_7322_init_old()
7880 /* Clear cmode-override, may be set from older driver */ in serdes_7322_init_old()
7881 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14); in serdes_7322_init_old()
7887 /* LoS filter threshold_count on, ch 0-3, set to 8 */ in serdes_7322_init_old()
7888 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11)); in serdes_7322_init_old()
7889 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4)); in serdes_7322_init_old()
7890 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11)); in serdes_7322_init_old()
7891 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4)); in serdes_7322_init_old()
7893 /* LoS filter threshold_count off, ch 0-3, set to 4 */ in serdes_7322_init_old()
7894 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0)); in serdes_7322_init_old()
7895 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8)); in serdes_7322_init_old()
7896 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0)); in serdes_7322_init_old()
7897 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8)); in serdes_7322_init_old()
7900 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15); in serdes_7322_init_old()
7916 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac; in serdes_7322_init_old()
7926 ppd->dd->cspec->r1 ? in serdes_7322_init_old()
7928 ppd->cpspec->qdr_dfe_on = 1; in serdes_7322_init_old()
7936 if (!ppd->dd->cspec->r1) { in serdes_7322_init_old()
7951 int chan, chan_done = (1 << SERDES_CHANS) - 1; in serdes_7322_init_new()
7953 /* Clear cmode-override, may be set from older driver */ in serdes_7322_init_new()
7954 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14); in serdes_7322_init_new()
7962 /* Reset - Calibration Setup */ in serdes_7322_init_new()
7991 /* DFE Bandwidth [2:14-12] */ in serdes_7322_init_new()
7996 if (!ppd->dd->cspec->r1) { in serdes_7322_init_new()
8002 /* Baseline Wander Correction Gain [13:4-0] (leave as default) */ in serdes_7322_init_new()
8003 /* Baseline Wander Correction Gain [3:7-5] (leave as default) */ in serdes_7322_init_new()
8004 /* Data Rate Select [5:7-6] (leave as default) */ in serdes_7322_init_new()
8005 /* RX Parallel Word Width [3:10-8] (leave as default) */ in serdes_7322_init_new()
8008 /* Single- or Multi-channel reset */ in serdes_7322_init_new()
8021 /* LoS filter threshold_count on, ch 0-3, set to 8 */ in serdes_7322_init_new()
8022 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11)); in serdes_7322_init_new()
8023 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4)); in serdes_7322_init_new()
8024 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11)); in serdes_7322_init_new()
8025 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4)); in serdes_7322_init_new()
8027 /* LoS filter threshold_count off, ch 0-3, set to 4 */ in serdes_7322_init_new()
8028 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0)); in serdes_7322_init_new()
8029 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8)); in serdes_7322_init_new()
8030 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0)); in serdes_7322_init_new()
8031 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8)); in serdes_7322_init_new()
8034 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15); in serdes_7322_init_new()
8058 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), in serdes_7322_init_new()
8068 IBSD(ppd->hw_pidx), chan_done); in serdes_7322_init_new()
8071 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), in serdes_7322_init_new()
8076 IBSD(ppd->hw_pidx), chan); in serdes_7322_init_new()
8086 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT; in serdes_7322_init_new()
8096 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac; in serdes_7322_init_new()
8117 ppd->dd->cspec->r1 ? in serdes_7322_init_new()
8119 ppd->cpspec->qdr_dfe_on = 1; in serdes_7322_init_new()
8147 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), in set_man_code()
8155 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), in set_man_mode_h1()
8158 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), in set_man_mode_h1()
8165 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), in clock_man()
8167 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), in clock_man()
8169 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), in clock_man()
8171 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), in clock_man()
8194 deemph |= (txdds->amp & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, in write_tx_serdes_param()
8197 deemph |= (txdds->main & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, in write_tx_serdes_param()
8200 deemph |= (txdds->post & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, in write_tx_serdes_param()
8203 deemph |= (txdds->pre & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, in write_tx_serdes_param()
8220 dds = (struct txdds_ent *)(ppd->link_speed_active == QIB_IB_QDR ? in adj_tx_serdes()
8221 qdr_dds : (ppd->link_speed_active == QIB_IB_DDR ? in adj_tx_serdes()
8231 ppd->cpspec->qdr_reforce = 0; in force_h1()
8232 if (!ppd->dd->cspec->r1) in force_h1()
8237 set_man_code(ppd, chan, ppd->cpspec->h1_val); in force_h1()
8276 return -1; in qib_r_wait_for_rdy()
8340 #define BIT2BYTE(x) (((x) + BITS_PER_BYTE - 1) / BITS_PER_BYTE)
8431 struct qib_devdata *dd = ppd->dd; in setup_7322_link_recovery()
8433 if (!ppd->dd->cspec->r1) in setup_7322_link_recovery()
8436 dd->cspec->recovery_ports_initted++; in setup_7322_link_recovery()
8437 ppd->cpspec->recovery_init = 1; in setup_7322_link_recovery()
8439 if (!both && dd->cspec->recovery_ports_initted == 1) { in setup_7322_link_recovery()
8440 portsel = ppd->port == 1 ? portsel_port1 : portsel_port2; in setup_7322_link_recovery()
8464 struct qib_devdata *dd = ppd->dd; in check_7322_rxe_status()
8467 if (dd->cspec->recovery_ports_initted != 1) in check_7322_rxe_status()
8469 qib_write_kreg(dd, kr_control, dd->control | in check_7322_rxe_status()
8480 ppd->dd->cspec->stay_in_freeze = 1; in check_7322_rxe_status()
8481 qib_7322_set_intr_state(ppd->dd, 0); in check_7322_rxe_status()
8487 qib_write_kreg(ppd->dd, kr_hwerrclear, in check_7322_rxe_status()
8491 qib_write_kreg(dd, kr_control, dd->control); in check_7322_rxe_status()
8494 if (ppd->link_speed_supported) { in check_7322_rxe_status()
8495 ppd->cpspec->ibcctrl_a &= in check_7322_rxe_status()
8498 ppd->cpspec->ibcctrl_a); in check_7322_rxe_status()
8500 if (ppd->lflags & QIBL_IB_LINK_DISABLED) in check_7322_rxe_status()