Lines Matching refs:dd
306 static inline u32 qib_read_ureg32(const struct qib_devdata *dd, in qib_read_ureg32() argument
309 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) in qib_read_ureg32()
312 if (dd->userbase) in qib_read_ureg32()
314 ((char __iomem *)dd->userbase + in qib_read_ureg32()
315 dd->ureg_align * ctxt)); in qib_read_ureg32()
318 (dd->uregbase + in qib_read_ureg32()
319 (char __iomem *)dd->kregbase + in qib_read_ureg32()
320 dd->ureg_align * ctxt)); in qib_read_ureg32()
332 static inline void qib_write_ureg(const struct qib_devdata *dd, in qib_write_ureg() argument
337 if (dd->userbase) in qib_write_ureg()
339 ((char __iomem *) dd->userbase + in qib_write_ureg()
340 dd->ureg_align * ctxt); in qib_write_ureg()
343 (dd->uregbase + in qib_write_ureg()
344 (char __iomem *) dd->kregbase + in qib_write_ureg()
345 dd->ureg_align * ctxt); in qib_write_ureg()
347 if (dd->kregbase && (dd->flags & QIB_PRESENT)) in qib_write_ureg()
351 static inline u32 qib_read_kreg32(const struct qib_devdata *dd, in qib_read_kreg32() argument
354 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) in qib_read_kreg32()
356 return readl((u32 __iomem *)&dd->kregbase[regno]); in qib_read_kreg32()
359 static inline u64 qib_read_kreg64(const struct qib_devdata *dd, in qib_read_kreg64() argument
362 if (!dd->kregbase || !(dd->flags & QIB_PRESENT)) in qib_read_kreg64()
365 return readq(&dd->kregbase[regno]); in qib_read_kreg64()
368 static inline void qib_write_kreg(const struct qib_devdata *dd, in qib_write_kreg() argument
371 if (dd->kregbase && (dd->flags & QIB_PRESENT)) in qib_write_kreg()
372 writeq(value, &dd->kregbase[regno]); in qib_write_kreg()
382 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd, in qib_write_kreg_ctxt() argument
386 qib_write_kreg(dd, regno + ctxt, value); in qib_write_kreg_ctxt()
389 static inline void write_6120_creg(const struct qib_devdata *dd, in write_6120_creg() argument
392 if (dd->cspec->cregbase && (dd->flags & QIB_PRESENT)) in write_6120_creg()
393 writeq(value, &dd->cspec->cregbase[regno]); in write_6120_creg()
396 static inline u64 read_6120_creg(const struct qib_devdata *dd, u16 regno) in read_6120_creg() argument
398 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) in read_6120_creg()
400 return readq(&dd->cspec->cregbase[regno]); in read_6120_creg()
403 static inline u32 read_6120_creg32(const struct qib_devdata *dd, u16 regno) in read_6120_creg32() argument
405 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) in read_6120_creg32()
407 return readl(&dd->cspec->cregbase[regno]); in read_6120_creg32()
670 static void qib_6120_txe_recover(struct qib_devdata *dd) in qib_6120_txe_recover() argument
673 qib_devinfo(dd->pcidev, in qib_6120_txe_recover()
678 static void qib_6120_set_intr_state(struct qib_devdata *dd, u32 enable) in qib_6120_set_intr_state() argument
681 if (dd->flags & QIB_BADINTR) in qib_6120_set_intr_state()
683 qib_write_kreg(dd, kr_intmask, ~0ULL); in qib_6120_set_intr_state()
685 qib_write_kreg(dd, kr_intclear, 0ULL); in qib_6120_set_intr_state()
687 qib_write_kreg(dd, kr_intmask, 0ULL); in qib_6120_set_intr_state()
705 static void qib_6120_clear_freeze(struct qib_devdata *dd) in qib_6120_clear_freeze() argument
708 qib_write_kreg(dd, kr_errmask, 0ULL); in qib_6120_clear_freeze()
711 qib_6120_set_intr_state(dd, 0); in qib_6120_clear_freeze()
713 qib_cancel_sends(dd->pport); in qib_6120_clear_freeze()
716 qib_write_kreg(dd, kr_control, dd->control); in qib_6120_clear_freeze()
717 qib_read_kreg32(dd, kr_scratch); in qib_6120_clear_freeze()
720 qib_force_pio_avail_update(dd); in qib_6120_clear_freeze()
728 qib_write_kreg(dd, kr_hwerrclear, 0ULL); in qib_6120_clear_freeze()
729 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE); in qib_6120_clear_freeze()
730 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); in qib_6120_clear_freeze()
731 qib_6120_set_intr_state(dd, 1); in qib_6120_clear_freeze()
745 static void qib_handle_6120_hwerrors(struct qib_devdata *dd, char *msg, in qib_handle_6120_hwerrors() argument
753 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus); in qib_handle_6120_hwerrors()
757 qib_dev_err(dd, in qib_handle_6120_hwerrors()
768 qib_write_kreg(dd, kr_hwerrclear, in qib_handle_6120_hwerrors()
771 hwerrs &= dd->cspec->hwerrmask; in qib_handle_6120_hwerrors()
778 qib_devinfo(dd->pcidev, in qib_handle_6120_hwerrors()
783 qib_dev_err(dd, in qib_handle_6120_hwerrors()
787 ctrl = qib_read_kreg32(dd, kr_control); in qib_handle_6120_hwerrors()
788 if ((ctrl & QLOGIC_IB_C_FREEZEMODE) && !dd->diag_client) { in qib_handle_6120_hwerrors()
798 qib_6120_txe_recover(dd); in qib_handle_6120_hwerrors()
806 qib_6120_clear_freeze(dd); in qib_handle_6120_hwerrors()
819 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed); in qib_handle_6120_hwerrors()
820 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_handle_6120_hwerrors()
826 bitsmsg = dd->cspec->bitsmsgbuf; in qib_handle_6120_hwerrors()
832 snprintf(bitsmsg, sizeof(dd->cspec->bitsmsgbuf), in qib_handle_6120_hwerrors()
839 snprintf(bitsmsg, sizeof(dd->cspec->bitsmsgbuf), in qib_handle_6120_hwerrors()
844 dd->cspec->hwerrmask &= ~(hwerrs & _QIB_PLL_FAIL); in qib_handle_6120_hwerrors()
845 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_handle_6120_hwerrors()
853 dd->cspec->hwerrmask &= ~QLOGIC_IB_HWE_SERDESPLLFAILED; in qib_handle_6120_hwerrors()
854 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_handle_6120_hwerrors()
864 qib_dev_err(dd, "%s hardware error\n", msg); in qib_handle_6120_hwerrors()
868 if (isfatal && !dd->diag_client) { in qib_handle_6120_hwerrors()
869 qib_dev_err(dd, in qib_handle_6120_hwerrors()
871 dd->serial); in qib_handle_6120_hwerrors()
876 if (dd->freezemsg) in qib_handle_6120_hwerrors()
877 snprintf(dd->freezemsg, dd->freezelen, in qib_handle_6120_hwerrors()
879 qib_disable_after_error(dd); in qib_handle_6120_hwerrors()
889 static int qib_decode_6120_err(struct qib_devdata *dd, char *buf, size_t blen, in qib_decode_6120_err() argument
965 struct qib_devdata *dd = ppd->dd; in qib_disarm_6120_senderrbufs() local
971 sbuf[0] = qib_read_kreg64(dd, kr_sendbuffererror); in qib_disarm_6120_senderrbufs()
972 sbuf[1] = qib_read_kreg64(dd, kr_sendbuffererror + 1); in qib_disarm_6120_senderrbufs()
975 qib_disarm_piobufs_set(dd, sbuf, in qib_disarm_6120_senderrbufs()
976 dd->piobcnt2k + dd->piobcnt4k); in qib_disarm_6120_senderrbufs()
979 static int chk_6120_linkrecovery(struct qib_devdata *dd, u64 ibcs) in chk_6120_linkrecovery() argument
983 u32 linkrecov = read_6120_creg32(dd, cr_iblinkerrrecov); in chk_6120_linkrecovery()
985 if (linkrecov != dd->cspec->lastlinkrecov) { in chk_6120_linkrecovery()
987 dd->cspec->lastlinkrecov = 0; in chk_6120_linkrecovery()
988 qib_set_linkstate(dd->pport, QIB_IB_LINKDOWN); in chk_6120_linkrecovery()
992 dd->cspec->lastlinkrecov = in chk_6120_linkrecovery()
993 read_6120_creg32(dd, cr_iblinkerrrecov); in chk_6120_linkrecovery()
997 static void handle_6120_errors(struct qib_devdata *dd, u64 errs) in handle_6120_errors() argument
1002 struct qib_pportdata *ppd = dd->pport; in handle_6120_errors()
1006 errs &= dd->cspec->errormask; in handle_6120_errors()
1007 msg = dd->cspec->emsgbuf; in handle_6120_errors()
1011 qib_handle_6120_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf)); in handle_6120_errors()
1014 qib_dev_err(dd, in handle_6120_errors()
1043 qib_write_kreg(dd, kr_errclear, errs); in handle_6120_errors()
1055 qib_decode_6120_err(dd, msg, sizeof(dd->cspec->emsgbuf), errs & ~mask); in handle_6120_errors()
1065 u64 ibcs = qib_read_kreg64(dd, kr_ibcstatus); in handle_6120_errors()
1069 if (ibstate != IB_PORT_INIT && dd->cspec->lastlinkrecov) in handle_6120_errors()
1070 handle = chk_6120_linkrecovery(dd, ibcs); in handle_6120_errors()
1086 qib_dev_err(dd, in handle_6120_errors()
1088 dd->flags &= ~QIB_INITTED; /* needs re-init */ in handle_6120_errors()
1090 *dd->devstatusp |= QIB_STATUS_HWERROR; in handle_6120_errors()
1091 *dd->pport->statusp &= ~QIB_STATUS_IB_CONF; in handle_6120_errors()
1095 qib_dev_porterr(dd, ppd->port, "%s error\n", msg); in handle_6120_errors()
1108 qib_handle_urcv(dd, ~0U); in handle_6120_errors()
1128 static void qib_6120_init_hwerrors(struct qib_devdata *dd) in qib_6120_init_hwerrors() argument
1133 extsval = qib_read_kreg64(dd, kr_extstatus); in qib_6120_init_hwerrors()
1136 qib_dev_err(dd, "MemBIST did not complete!\n"); in qib_6120_init_hwerrors()
1140 if (dd->minrev < 2) { in qib_6120_init_hwerrors()
1150 dd->cspec->hwerrmask = val; in qib_6120_init_hwerrors()
1152 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed)); in qib_6120_init_hwerrors()
1153 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_6120_init_hwerrors()
1156 qib_write_kreg(dd, kr_errclear, ~0ULL); in qib_6120_init_hwerrors()
1158 qib_write_kreg(dd, kr_errmask, ~0ULL); in qib_6120_init_hwerrors()
1159 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask); in qib_6120_init_hwerrors()
1161 qib_write_kreg(dd, kr_intclear, ~0ULL); in qib_6120_init_hwerrors()
1163 qib_write_kreg(dd, kr_rcvbthqp, in qib_6120_init_hwerrors()
1164 dd->qpn_mask << (QIB_6120_RcvBTHQP_BTHQP_Mask_LSB - 1) | in qib_6120_init_hwerrors()
1174 static void qib_set_6120_armlaunch(struct qib_devdata *dd, u32 enable) in qib_set_6120_armlaunch() argument
1177 qib_write_kreg(dd, kr_errclear, in qib_set_6120_armlaunch()
1179 dd->cspec->errormask |= ERR_MASK(SendPioArmLaunchErr); in qib_set_6120_armlaunch()
1181 dd->cspec->errormask &= ~ERR_MASK(SendPioArmLaunchErr); in qib_set_6120_armlaunch()
1182 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); in qib_set_6120_armlaunch()
1194 struct qib_devdata *dd = ppd->dd; in qib_set_ib_6120_lstate() local
1219 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl | mod_wd); in qib_set_ib_6120_lstate()
1221 qib_write_kreg(dd, kr_scratch, 0); in qib_set_ib_6120_lstate()
1230 struct qib_devdata *dd = ppd->dd; in qib_6120_bringup_serdes() local
1234 dd->control &= ~QLOGIC_IB_C_LINKENABLE; in qib_6120_bringup_serdes()
1235 qib_write_kreg(dd, kr_control, 0ULL); in qib_6120_bringup_serdes()
1237 dd->cspec->ibdeltainprog = 1; in qib_6120_bringup_serdes()
1238 dd->cspec->ibsymsnap = read_6120_creg32(dd, cr_ibsymbolerr); in qib_6120_bringup_serdes()
1239 dd->cspec->iblnkerrsnap = read_6120_creg32(dd, cr_iblinkerrrecov); in qib_6120_bringup_serdes()
1250 dd->cspec->lli_thresh = 0xf; in qib_6120_bringup_serdes()
1251 ibc |= (u64) dd->cspec->lli_thresh << SYM_LSB(IBCCtrl, PhyerrThreshold); in qib_6120_bringup_serdes()
1261 dd->cspec->ibcctrl = ibc; /* without linkcmd or linkinitcmd! */ in qib_6120_bringup_serdes()
1264 val = dd->cspec->ibcctrl | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE << in qib_6120_bringup_serdes()
1266 qib_write_kreg(dd, kr_ibcctrl, val); in qib_6120_bringup_serdes()
1268 val = qib_read_kreg64(dd, kr_serdes_cfg0); in qib_6120_bringup_serdes()
1269 config1 = qib_read_kreg64(dd, kr_serdes_cfg1); in qib_6120_bringup_serdes()
1283 qib_write_kreg(dd, kr_serdes_cfg0, val); in qib_6120_bringup_serdes()
1285 qib_read_kreg64(dd, kr_scratch); in qib_6120_bringup_serdes()
1303 qib_write_kreg(dd, kr_serdes_cfg0, val); in qib_6120_bringup_serdes()
1305 (void) qib_read_kreg64(dd, kr_scratch); in qib_6120_bringup_serdes()
1315 qib_write_kreg(dd, kr_serdes_cfg0, val); in qib_6120_bringup_serdes()
1317 (void) qib_read_kreg64(dd, kr_scratch); in qib_6120_bringup_serdes()
1319 val = qib_read_kreg64(dd, kr_xgxs_cfg); in qib_6120_bringup_serdes()
1329 qib_write_kreg(dd, kr_xgxs_cfg, val); in qib_6120_bringup_serdes()
1331 val = qib_read_kreg64(dd, kr_serdes_cfg0); in qib_6120_bringup_serdes()
1339 qib_write_kreg(dd, kr_serdes_cfg1, config1); in qib_6120_bringup_serdes()
1342 ppd->guid = dd->base_guid; in qib_6120_bringup_serdes()
1349 hwstat = qib_read_kreg64(dd, kr_hwerrstatus); in qib_6120_bringup_serdes()
1352 qib_write_kreg(dd, kr_hwerrclear, hwstat); in qib_6120_bringup_serdes()
1353 qib_write_kreg(dd, kr_errclear, ERR_MASK(HardwareErr)); in qib_6120_bringup_serdes()
1356 dd->control |= QLOGIC_IB_C_LINKENABLE; in qib_6120_bringup_serdes()
1357 dd->control &= ~QLOGIC_IB_C_FREEZEMODE; in qib_6120_bringup_serdes()
1358 qib_write_kreg(dd, kr_control, dd->control); in qib_6120_bringup_serdes()
1370 struct qib_devdata *dd = ppd->dd; in qib_6120_quiet_serdes() local
1376 dd->control &= ~QLOGIC_IB_C_LINKENABLE; in qib_6120_quiet_serdes()
1377 qib_write_kreg(dd, kr_control, in qib_6120_quiet_serdes()
1378 dd->control | QLOGIC_IB_C_FREEZEMODE); in qib_6120_quiet_serdes()
1380 if (dd->cspec->ibsymdelta || dd->cspec->iblnkerrdelta || in qib_6120_quiet_serdes()
1381 dd->cspec->ibdeltainprog) { in qib_6120_quiet_serdes()
1385 diagc = qib_read_kreg64(dd, kr_hwdiagctrl); in qib_6120_quiet_serdes()
1386 qib_write_kreg(dd, kr_hwdiagctrl, in qib_6120_quiet_serdes()
1389 if (dd->cspec->ibsymdelta || dd->cspec->ibdeltainprog) { in qib_6120_quiet_serdes()
1390 val = read_6120_creg32(dd, cr_ibsymbolerr); in qib_6120_quiet_serdes()
1391 if (dd->cspec->ibdeltainprog) in qib_6120_quiet_serdes()
1392 val -= val - dd->cspec->ibsymsnap; in qib_6120_quiet_serdes()
1393 val -= dd->cspec->ibsymdelta; in qib_6120_quiet_serdes()
1394 write_6120_creg(dd, cr_ibsymbolerr, val); in qib_6120_quiet_serdes()
1396 if (dd->cspec->iblnkerrdelta || dd->cspec->ibdeltainprog) { in qib_6120_quiet_serdes()
1397 val = read_6120_creg32(dd, cr_iblinkerrrecov); in qib_6120_quiet_serdes()
1398 if (dd->cspec->ibdeltainprog) in qib_6120_quiet_serdes()
1399 val -= val - dd->cspec->iblnkerrsnap; in qib_6120_quiet_serdes()
1400 val -= dd->cspec->iblnkerrdelta; in qib_6120_quiet_serdes()
1401 write_6120_creg(dd, cr_iblinkerrrecov, val); in qib_6120_quiet_serdes()
1405 qib_write_kreg(dd, kr_hwdiagctrl, diagc); in qib_6120_quiet_serdes()
1408 val = qib_read_kreg64(dd, kr_serdes_cfg0); in qib_6120_quiet_serdes()
1410 qib_write_kreg(dd, kr_serdes_cfg0, val); in qib_6120_quiet_serdes()
1439 struct qib_devdata *dd = ppd->dd; in qib_6120_setup_setextled() local
1445 if (dd->diag_client) in qib_6120_setup_setextled()
1455 val = qib_read_kreg64(dd, kr_ibcstatus); in qib_6120_setup_setextled()
1463 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in qib_6120_setup_setextled()
1464 extctl = dd->cspec->extctrl & ~(SYM_MASK(EXTCtrl, LEDPriPortGreenOn) | in qib_6120_setup_setextled()
1471 dd->cspec->extctrl = extctl; in qib_6120_setup_setextled()
1472 qib_write_kreg(dd, kr_extctrl, extctl); in qib_6120_setup_setextled()
1473 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in qib_6120_setup_setextled()
1482 static void qib_6120_setup_cleanup(struct qib_devdata *dd) in qib_6120_setup_cleanup() argument
1484 qib_free_irq(dd); in qib_6120_setup_cleanup()
1485 kfree(dd->cspec->cntrs); in qib_6120_setup_cleanup()
1486 kfree(dd->cspec->portcntrs); in qib_6120_setup_cleanup()
1487 if (dd->cspec->dummy_hdrq) { in qib_6120_setup_cleanup()
1488 dma_free_coherent(&dd->pcidev->dev, in qib_6120_setup_cleanup()
1489 ALIGN(dd->rcvhdrcnt * in qib_6120_setup_cleanup()
1490 dd->rcvhdrentsize * in qib_6120_setup_cleanup()
1492 dd->cspec->dummy_hdrq, in qib_6120_setup_cleanup()
1493 dd->cspec->dummy_hdrq_phys); in qib_6120_setup_cleanup()
1494 dd->cspec->dummy_hdrq = NULL; in qib_6120_setup_cleanup()
1498 static void qib_wantpiobuf_6120_intr(struct qib_devdata *dd, u32 needint) in qib_wantpiobuf_6120_intr() argument
1502 spin_lock_irqsave(&dd->sendctrl_lock, flags); in qib_wantpiobuf_6120_intr()
1504 dd->sendctrl |= SYM_MASK(SendCtrl, PIOIntBufAvail); in qib_wantpiobuf_6120_intr()
1506 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOIntBufAvail); in qib_wantpiobuf_6120_intr()
1507 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl); in qib_wantpiobuf_6120_intr()
1508 qib_write_kreg(dd, kr_scratch, 0ULL); in qib_wantpiobuf_6120_intr()
1509 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in qib_wantpiobuf_6120_intr()
1516 static noinline void unlikely_6120_intr(struct qib_devdata *dd, u64 istat) in unlikely_6120_intr() argument
1519 qib_dev_err(dd, "interrupt with unknown interrupts %Lx set\n", in unlikely_6120_intr()
1526 estat = qib_read_kreg64(dd, kr_errstatus); in unlikely_6120_intr()
1528 qib_devinfo(dd->pcidev, in unlikely_6120_intr()
1531 handle_6120_errors(dd, estat); in unlikely_6120_intr()
1542 gpiostatus = qib_read_kreg32(dd, kr_gpio_status); in unlikely_6120_intr()
1553 dd->cspec->rxfc_unsupvl_errs++; in unlikely_6120_intr()
1555 dd->cspec->overrun_thresh_errs++; in unlikely_6120_intr()
1557 dd->cspec->lli_errs++; in unlikely_6120_intr()
1567 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask); in unlikely_6120_intr()
1576 dd->cspec->gpio_mask &= ~(gpiostatus & mask); in unlikely_6120_intr()
1577 qib_write_kreg(dd, kr_gpio_mask, in unlikely_6120_intr()
1578 dd->cspec->gpio_mask); in unlikely_6120_intr()
1582 qib_write_kreg(dd, kr_gpio_clear, (u64) to_clear); in unlikely_6120_intr()
1588 struct qib_devdata *dd = data; in qib_6120intr() local
1593 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) { in qib_6120intr()
1604 istat = qib_read_kreg32(dd, kr_intstatus); in qib_6120intr()
1611 qib_bad_intrstatus(dd); in qib_6120intr()
1617 this_cpu_inc(*dd->int_counter); in qib_6120intr()
1621 unlikely_6120_intr(dd, istat); in qib_6120intr()
1629 qib_write_kreg(dd, kr_intclear, istat); in qib_6120intr()
1642 for (i = 0; i < dd->first_user_ctxt; i++) { in qib_6120intr()
1645 crcs += qib_kreceive(dd->rcd[i], in qib_6120intr()
1646 &dd->cspec->lli_counter, in qib_6120intr()
1652 u32 cntr = dd->cspec->lli_counter; in qib_6120intr()
1656 if (cntr > dd->cspec->lli_thresh) { in qib_6120intr()
1657 dd->cspec->lli_counter = 0; in qib_6120intr()
1658 dd->cspec->lli_errs++; in qib_6120intr()
1660 dd->cspec->lli_counter += cntr; in qib_6120intr()
1669 qib_handle_urcv(dd, ctxtrbits); in qib_6120intr()
1673 if ((istat & QLOGIC_IB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED)) in qib_6120intr()
1674 qib_ib_piobufavail(dd); in qib_6120intr()
1686 static void qib_setup_6120_interrupt(struct qib_devdata *dd) in qib_setup_6120_interrupt() argument
1696 if (SYM_FIELD(dd->revision, Revision_R, in qib_setup_6120_interrupt()
1699 dd->cspec->gpio_mask |= GPIO_ERRINTR_MASK; in qib_setup_6120_interrupt()
1700 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); in qib_setup_6120_interrupt()
1703 ret = pci_request_irq(dd->pcidev, 0, qib_6120intr, NULL, dd, in qib_setup_6120_interrupt()
1706 qib_dev_err(dd, in qib_setup_6120_interrupt()
1708 pci_irq_vector(dd->pcidev, 0), ret); in qib_setup_6120_interrupt()
1717 static void pe_boardname(struct qib_devdata *dd) in pe_boardname() argument
1721 boardid = SYM_FIELD(dd->revision, Revision, in pe_boardname()
1726 dd->boardname = "InfiniPath_QLE7140"; in pe_boardname()
1729 qib_dev_err(dd, "Unknown 6120 board with ID %u\n", boardid); in pe_boardname()
1730 dd->boardname = "Unknown_InfiniPath_6120"; in pe_boardname()
1734 if (dd->majrev != 4 || !dd->minrev || dd->minrev > 2) in pe_boardname()
1735 qib_dev_err(dd, in pe_boardname()
1737 dd->majrev, dd->minrev); in pe_boardname()
1739 snprintf(dd->boardversion, sizeof(dd->boardversion), in pe_boardname()
1741 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname, in pe_boardname()
1742 (unsigned int)SYM_FIELD(dd->revision, Revision_R, Arch), in pe_boardname()
1743 dd->majrev, dd->minrev, in pe_boardname()
1744 (unsigned int)SYM_FIELD(dd->revision, Revision_R, SW)); in pe_boardname()
1752 static int qib_6120_setup_reset(struct qib_devdata *dd) in qib_6120_setup_reset() argument
1760 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz); in qib_6120_setup_reset()
1763 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit); in qib_6120_setup_reset()
1766 qib_6120_set_intr_state(dd, 0); in qib_6120_setup_reset()
1768 dd->cspec->ibdeltainprog = 0; in qib_6120_setup_reset()
1769 dd->cspec->ibsymdelta = 0; in qib_6120_setup_reset()
1770 dd->cspec->iblnkerrdelta = 0; in qib_6120_setup_reset()
1777 dd->flags &= ~(QIB_INITTED | QIB_PRESENT); in qib_6120_setup_reset()
1779 dd->z_int_counter = qib_int_counter(dd); in qib_6120_setup_reset()
1780 val = dd->control | QLOGIC_IB_C_RESET; in qib_6120_setup_reset()
1781 writeq(val, &dd->kregbase[kr_control]); in qib_6120_setup_reset()
1792 qib_pcie_reenable(dd, cmdval, int_line, clinesz); in qib_6120_setup_reset()
1798 val = readq(&dd->kregbase[kr_revision]); in qib_6120_setup_reset()
1799 if (val == dd->revision) { in qib_6120_setup_reset()
1800 dd->flags |= QIB_PRESENT; /* it's back */ in qib_6120_setup_reset()
1801 ret = qib_reinit_intr(dd); in qib_6120_setup_reset()
1809 if (qib_pcie_params(dd, dd->lbus_width, NULL)) in qib_6120_setup_reset()
1810 qib_dev_err(dd, in qib_6120_setup_reset()
1813 qib_6120_init_hwerrors(dd); in qib_6120_setup_reset()
1815 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); in qib_6120_setup_reset()
1817 qib_6120_init_hwerrors(dd); in qib_6120_setup_reset()
1834 static void qib_6120_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr, in qib_6120_put_tid() argument
1842 if (!dd->kregbase) in qib_6120_put_tid()
1845 if (pa != dd->tidinvalid) { in qib_6120_put_tid()
1847 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n", in qib_6120_put_tid()
1853 qib_dev_err(dd, in qib_6120_put_tid()
1860 pa |= dd->tidtemplate; in qib_6120_put_tid()
1878 tidx = tidptr - dd->egrtidbase; in qib_6120_put_tid()
1880 tidlockp = (type == RCVHQ_RCV_TYPE_EAGER && tidx < dd->rcvhdrcnt) in qib_6120_put_tid()
1881 ? &dd->cspec->kernel_tid_lock : &dd->cspec->user_tid_lock; in qib_6120_put_tid()
1883 qib_write_kreg(dd, kr_scratch, 0xfeeddeaf); in qib_6120_put_tid()
1885 qib_write_kreg(dd, kr_scratch, 0xdeadbeef); in qib_6120_put_tid()
1901 static void qib_6120_put_tid_2(struct qib_devdata *dd, u64 __iomem *tidptr, in qib_6120_put_tid_2() argument
1906 if (!dd->kregbase) in qib_6120_put_tid_2()
1909 if (pa != dd->tidinvalid) { in qib_6120_put_tid_2()
1911 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n", in qib_6120_put_tid_2()
1917 qib_dev_err(dd, in qib_6120_put_tid_2()
1924 pa |= dd->tidtemplate; in qib_6120_put_tid_2()
1942 static void qib_6120_clear_tids(struct qib_devdata *dd, in qib_6120_clear_tids() argument
1950 if (!dd->kregbase || !rcd) in qib_6120_clear_tids()
1955 tidinv = dd->tidinvalid; in qib_6120_clear_tids()
1957 ((char __iomem *)(dd->kregbase) + in qib_6120_clear_tids()
1958 dd->rcvtidbase + in qib_6120_clear_tids()
1959 ctxt * dd->rcvtidcnt * sizeof(*tidbase)); in qib_6120_clear_tids()
1961 for (i = 0; i < dd->rcvtidcnt; i++) in qib_6120_clear_tids()
1963 dd->f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED, in qib_6120_clear_tids()
1967 ((char __iomem *)(dd->kregbase) + in qib_6120_clear_tids()
1968 dd->rcvegrbase + in qib_6120_clear_tids()
1973 dd->f_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER, in qib_6120_clear_tids()
1983 static void qib_6120_tidtemplate(struct qib_devdata *dd) in qib_6120_tidtemplate() argument
1985 u32 egrsize = dd->rcvegrbufsize; in qib_6120_tidtemplate()
1997 dd->tidtemplate = 1U << 29; in qib_6120_tidtemplate()
1999 dd->tidtemplate = 2U << 29; in qib_6120_tidtemplate()
2000 dd->tidinvalid = 0; in qib_6120_tidtemplate()
2029 qib_6120_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr) in qib_6120_get_msgheader() argument
2035 static void qib_6120_config_ctxts(struct qib_devdata *dd) in qib_6120_config_ctxts() argument
2037 dd->ctxtcnt = qib_read_kreg32(dd, kr_portcnt); in qib_6120_config_ctxts()
2039 dd->first_user_ctxt = qib_n_krcv_queues * dd->num_pports; in qib_6120_config_ctxts()
2040 if (dd->first_user_ctxt > dd->ctxtcnt) in qib_6120_config_ctxts()
2041 dd->first_user_ctxt = dd->ctxtcnt; in qib_6120_config_ctxts()
2042 dd->qpn_mask = dd->first_user_ctxt <= 2 ? 2 : 6; in qib_6120_config_ctxts()
2044 dd->first_user_ctxt = dd->num_pports; in qib_6120_config_ctxts()
2045 dd->n_krcv_queues = dd->first_user_ctxt; in qib_6120_config_ctxts()
2052 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt); in qib_update_6120_usrhead()
2053 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt); in qib_update_6120_usrhead()
2060 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt); in qib_6120_hdrqempty()
2064 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt); in qib_6120_hdrqempty()
2073 static void alloc_dummy_hdrq(struct qib_devdata *dd) in alloc_dummy_hdrq() argument
2075 dd->cspec->dummy_hdrq = dma_alloc_coherent(&dd->pcidev->dev, in alloc_dummy_hdrq()
2076 dd->rcd[0]->rcvhdrq_size, in alloc_dummy_hdrq()
2077 &dd->cspec->dummy_hdrq_phys, in alloc_dummy_hdrq()
2079 if (!dd->cspec->dummy_hdrq) { in alloc_dummy_hdrq()
2080 qib_devinfo(dd->pcidev, "Couldn't allocate dummy hdrq\n"); in alloc_dummy_hdrq()
2082 dd->cspec->dummy_hdrq_phys = 0UL; in alloc_dummy_hdrq()
2096 struct qib_devdata *dd = ppd->dd; in rcvctrl_6120_mod() local
2100 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in rcvctrl_6120_mod()
2103 dd->rcvctrl |= (1ULL << QLOGIC_IB_R_TAILUPD_SHIFT); in rcvctrl_6120_mod()
2105 dd->rcvctrl &= ~(1ULL << QLOGIC_IB_R_TAILUPD_SHIFT); in rcvctrl_6120_mod()
2107 dd->rcvctrl &= ~(1ULL << IBA6120_R_PKEY_DIS_SHIFT); in rcvctrl_6120_mod()
2109 dd->rcvctrl |= (1ULL << IBA6120_R_PKEY_DIS_SHIFT); in rcvctrl_6120_mod()
2111 mask = (1ULL << dd->ctxtcnt) - 1; in rcvctrl_6120_mod()
2116 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, PortEnable)); in rcvctrl_6120_mod()
2117 if (!(dd->flags & QIB_NODMA_RTAIL)) in rcvctrl_6120_mod()
2118 dd->rcvctrl |= 1ULL << QLOGIC_IB_R_TAILUPD_SHIFT; in rcvctrl_6120_mod()
2120 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, ctxt, in rcvctrl_6120_mod()
2121 dd->rcd[ctxt]->rcvhdrqtailaddr_phys); in rcvctrl_6120_mod()
2122 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, ctxt, in rcvctrl_6120_mod()
2123 dd->rcd[ctxt]->rcvhdrq_phys); in rcvctrl_6120_mod()
2125 if (ctxt == 0 && !dd->cspec->dummy_hdrq) in rcvctrl_6120_mod()
2126 alloc_dummy_hdrq(dd); in rcvctrl_6120_mod()
2129 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, PortEnable)); in rcvctrl_6120_mod()
2131 dd->rcvctrl |= (mask << QLOGIC_IB_R_INTRAVAIL_SHIFT); in rcvctrl_6120_mod()
2133 dd->rcvctrl &= ~(mask << QLOGIC_IB_R_INTRAVAIL_SHIFT); in rcvctrl_6120_mod()
2134 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl); in rcvctrl_6120_mod()
2135 if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) && dd->rhdrhead_intr_off) { in rcvctrl_6120_mod()
2137 val = qib_read_ureg32(dd, ur_rcvhdrhead, ctxt) | in rcvctrl_6120_mod()
2138 dd->rhdrhead_intr_off; in rcvctrl_6120_mod()
2139 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt); in rcvctrl_6120_mod()
2148 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt); in rcvctrl_6120_mod()
2149 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt); in rcvctrl_6120_mod()
2151 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt); in rcvctrl_6120_mod()
2152 dd->rcd[ctxt]->head = val; in rcvctrl_6120_mod()
2154 if (ctxt < dd->first_user_ctxt) in rcvctrl_6120_mod()
2155 val |= dd->rhdrhead_intr_off; in rcvctrl_6120_mod()
2156 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt); in rcvctrl_6120_mod()
2169 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, ctxt, in rcvctrl_6120_mod()
2170 dd->cspec->dummy_hdrq_phys); in rcvctrl_6120_mod()
2171 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, ctxt, in rcvctrl_6120_mod()
2172 dd->cspec->dummy_hdrq_phys); in rcvctrl_6120_mod()
2176 for (i = 0; i < dd->cfgctxts; i++) { in rcvctrl_6120_mod()
2177 qib_write_kreg_ctxt(dd, kr_rcvhdrtailaddr, in rcvctrl_6120_mod()
2178 i, dd->cspec->dummy_hdrq_phys); in rcvctrl_6120_mod()
2179 qib_write_kreg_ctxt(dd, kr_rcvhdraddr, in rcvctrl_6120_mod()
2180 i, dd->cspec->dummy_hdrq_phys); in rcvctrl_6120_mod()
2184 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in rcvctrl_6120_mod()
2197 struct qib_devdata *dd = ppd->dd; in sendctrl_6120_mod() local
2201 spin_lock_irqsave(&dd->sendctrl_lock, flags); in sendctrl_6120_mod()
2205 dd->sendctrl = 0; in sendctrl_6120_mod()
2207 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOEnable); in sendctrl_6120_mod()
2209 dd->sendctrl |= SYM_MASK(SendCtrl, PIOEnable); in sendctrl_6120_mod()
2211 dd->sendctrl &= ~SYM_MASK(SendCtrl, PIOBufAvailUpd); in sendctrl_6120_mod()
2213 dd->sendctrl |= SYM_MASK(SendCtrl, PIOBufAvailUpd); in sendctrl_6120_mod()
2218 tmp_dd_sendctrl = dd->sendctrl; in sendctrl_6120_mod()
2223 last = dd->piobcnt2k + dd->piobcnt4k; in sendctrl_6120_mod()
2228 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl | in sendctrl_6120_mod()
2230 qib_write_kreg(dd, kr_scratch, 0); in sendctrl_6120_mod()
2234 tmp_dd_sendctrl = dd->sendctrl; in sendctrl_6120_mod()
2245 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl); in sendctrl_6120_mod()
2246 qib_write_kreg(dd, kr_scratch, 0); in sendctrl_6120_mod()
2249 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl); in sendctrl_6120_mod()
2250 qib_write_kreg(dd, kr_scratch, 0); in sendctrl_6120_mod()
2253 spin_unlock_irqrestore(&dd->sendctrl_lock, flags); in sendctrl_6120_mod()
2263 v = qib_read_kreg32(dd, kr_scratch); in sendctrl_6120_mod()
2264 qib_write_kreg(dd, kr_scratch, v); in sendctrl_6120_mod()
2265 v = qib_read_kreg32(dd, kr_scratch); in sendctrl_6120_mod()
2266 qib_write_kreg(dd, kr_scratch, v); in sendctrl_6120_mod()
2267 qib_read_kreg32(dd, kr_scratch); in sendctrl_6120_mod()
2279 struct qib_devdata *dd = ppd->dd; in qib_portcntr_6120() local
2320 qib_devinfo(ppd->dd->pcidev, in qib_portcntr_6120()
2328 ret = dd->cspec->lli_errs; in qib_portcntr_6120()
2330 ret = dd->cspec->overrun_thresh_errs; in qib_portcntr_6120()
2335 for (i = 0; i < dd->first_user_ctxt; i++) in qib_portcntr_6120()
2336 ret += read_6120_creg32(dd, cr_portovfl + i); in qib_portcntr_6120()
2338 ret = dd->cspec->pma_sample_status; in qib_portcntr_6120()
2348 ret = read_6120_creg(dd, creg); in qib_portcntr_6120()
2350 ret = read_6120_creg32(dd, creg); in qib_portcntr_6120()
2352 if (dd->cspec->ibdeltainprog) in qib_portcntr_6120()
2353 ret -= ret - dd->cspec->ibsymsnap; in qib_portcntr_6120()
2354 ret -= dd->cspec->ibsymdelta; in qib_portcntr_6120()
2356 if (dd->cspec->ibdeltainprog) in qib_portcntr_6120()
2357 ret -= ret - dd->cspec->iblnkerrsnap; in qib_portcntr_6120()
2358 ret -= dd->cspec->iblnkerrdelta; in qib_portcntr_6120()
2361 ret += dd->cspec->rxfc_unsupvl_errs; in qib_portcntr_6120()
2474 static void init_6120_cntrnames(struct qib_devdata *dd) in init_6120_cntrnames() argument
2479 for (i = 0, s = (char *)cntr6120names; s && j <= dd->cfgctxts; in init_6120_cntrnames()
2488 dd->cspec->ncntrs = i; in init_6120_cntrnames()
2491 dd->cspec->cntrnamelen = sizeof(cntr6120names) - 1; in init_6120_cntrnames()
2493 dd->cspec->cntrnamelen = 1 + s - cntr6120names; in init_6120_cntrnames()
2494 dd->cspec->cntrs = kmalloc_array(dd->cspec->ncntrs, sizeof(u64), in init_6120_cntrnames()
2499 dd->cspec->nportcntrs = i - 1; in init_6120_cntrnames()
2500 dd->cspec->portcntrnamelen = sizeof(portcntr6120names) - 1; in init_6120_cntrnames()
2501 dd->cspec->portcntrs = kmalloc_array(dd->cspec->nportcntrs, in init_6120_cntrnames()
2506 static u32 qib_read_6120cntrs(struct qib_devdata *dd, loff_t pos, char **namep, in qib_read_6120cntrs() argument
2512 ret = dd->cspec->cntrnamelen; in qib_read_6120cntrs()
2518 u64 *cntr = dd->cspec->cntrs; in qib_read_6120cntrs()
2521 ret = dd->cspec->ncntrs * sizeof(u64); in qib_read_6120cntrs()
2532 for (i = 0; i < dd->cspec->ncntrs; i++) in qib_read_6120cntrs()
2533 *cntr++ = read_6120_creg32(dd, cntr6120indices[i]); in qib_read_6120cntrs()
2539 static u32 qib_read_6120portcntrs(struct qib_devdata *dd, loff_t pos, u32 port, in qib_read_6120portcntrs() argument
2545 ret = dd->cspec->portcntrnamelen; in qib_read_6120portcntrs()
2551 u64 *cntr = dd->cspec->portcntrs; in qib_read_6120portcntrs()
2552 struct qib_pportdata *ppd = &dd->pport[port]; in qib_read_6120portcntrs()
2555 ret = dd->cspec->nportcntrs * sizeof(u64); in qib_read_6120portcntrs()
2562 for (i = 0; i < dd->cspec->nportcntrs; i++) { in qib_read_6120portcntrs()
2568 *cntr++ = read_6120_creg32(dd, in qib_read_6120portcntrs()
2576 static void qib_chk_6120_errormask(struct qib_devdata *dd) in qib_chk_6120_errormask() argument
2583 if (!dd->cspec->errormask || !(dd->flags & QIB_INITTED)) in qib_chk_6120_errormask()
2586 errormask = qib_read_kreg64(dd, kr_errmask); in qib_chk_6120_errormask()
2588 if (errormask == dd->cspec->errormask) in qib_chk_6120_errormask()
2592 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus); in qib_chk_6120_errormask()
2593 ctrl = qib_read_kreg32(dd, kr_control); in qib_chk_6120_errormask()
2595 qib_write_kreg(dd, kr_errmask, in qib_chk_6120_errormask()
2596 dd->cspec->errormask); in qib_chk_6120_errormask()
2598 if ((hwerrs & dd->cspec->hwerrmask) || in qib_chk_6120_errormask()
2600 qib_write_kreg(dd, kr_hwerrclear, 0ULL); in qib_chk_6120_errormask()
2601 qib_write_kreg(dd, kr_errclear, 0ULL); in qib_chk_6120_errormask()
2603 qib_write_kreg(dd, kr_intclear, 0ULL); in qib_chk_6120_errormask()
2604 qib_devinfo(dd->pcidev, in qib_chk_6120_errormask()
2606 fixed, errormask, (unsigned long)dd->cspec->errormask, in qib_chk_6120_errormask()
2621 struct qib_devdata *dd = from_timer(dd, t, stats_timer); in qib_get_6120_faststats() local
2622 struct qib_pportdata *ppd = dd->pport; in qib_get_6120_faststats()
2630 if (!(dd->flags & QIB_INITTED) || dd->diag_client) in qib_get_6120_faststats()
2641 spin_lock_irqsave(&dd->eep_st_lock, flags); in qib_get_6120_faststats()
2642 traffic_wds -= dd->traffic_wds; in qib_get_6120_faststats()
2643 dd->traffic_wds += traffic_wds; in qib_get_6120_faststats()
2644 spin_unlock_irqrestore(&dd->eep_st_lock, flags); in qib_get_6120_faststats()
2646 qib_chk_6120_errormask(dd); in qib_get_6120_faststats()
2648 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER); in qib_get_6120_faststats()
2652 static int qib_6120_nointr_fallback(struct qib_devdata *dd) in qib_6120_nointr_fallback() argument
2666 struct qib_devdata *dd = ppd->dd; in qib_6120_xgxs_reset() local
2668 prev_val = qib_read_kreg64(dd, kr_xgxs_cfg); in qib_6120_xgxs_reset()
2671 qib_write_kreg(dd, kr_control, in qib_6120_xgxs_reset()
2672 dd->control & ~QLOGIC_IB_C_LINKENABLE); in qib_6120_xgxs_reset()
2673 qib_write_kreg(dd, kr_xgxs_cfg, val); in qib_6120_xgxs_reset()
2674 qib_read_kreg32(dd, kr_scratch); in qib_6120_xgxs_reset()
2675 qib_write_kreg(dd, kr_xgxs_cfg, prev_val); in qib_6120_xgxs_reset()
2676 qib_write_kreg(dd, kr_control, dd->control); in qib_6120_xgxs_reset()
2713 ret = SYM_FIELD(ppd->dd->cspec->ibcctrl, IBCCtrl, in qib_6120_get_ib_cfg()
2718 ret = SYM_FIELD(ppd->dd->cspec->ibcctrl, IBCCtrl, in qib_6120_get_ib_cfg()
2724 ret = (ppd->dd->cspec->ibcctrl & in qib_6120_get_ib_cfg()
2749 struct qib_devdata *dd = ppd->dd; in qib_6120_set_ib_cfg() local
2764 val64 = SYM_FIELD(dd->cspec->ibcctrl, IBCCtrl, in qib_6120_set_ib_cfg()
2767 dd->cspec->ibcctrl &= in qib_6120_set_ib_cfg()
2769 dd->cspec->ibcctrl |= (u64) val << in qib_6120_set_ib_cfg()
2771 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl); in qib_6120_set_ib_cfg()
2772 qib_write_kreg(dd, kr_scratch, 0); in qib_6120_set_ib_cfg()
2777 val64 = SYM_FIELD(dd->cspec->ibcctrl, IBCCtrl, in qib_6120_set_ib_cfg()
2780 dd->cspec->ibcctrl &= in qib_6120_set_ib_cfg()
2782 dd->cspec->ibcctrl |= (u64) val << in qib_6120_set_ib_cfg()
2784 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl); in qib_6120_set_ib_cfg()
2785 qib_write_kreg(dd, kr_scratch, 0); in qib_6120_set_ib_cfg()
2793 qib_write_kreg(dd, kr_partitionkey, val64); in qib_6120_set_ib_cfg()
2799 dd->cspec->ibcctrl &= in qib_6120_set_ib_cfg()
2802 dd->cspec->ibcctrl |= in qib_6120_set_ib_cfg()
2804 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl); in qib_6120_set_ib_cfg()
2805 qib_write_kreg(dd, kr_scratch, 0); in qib_6120_set_ib_cfg()
2817 dd->cspec->ibcctrl &= ~SYM_MASK(IBCCtrl, MaxPktLen); in qib_6120_set_ib_cfg()
2818 dd->cspec->ibcctrl |= (u64)val << in qib_6120_set_ib_cfg()
2820 qib_write_kreg(dd, kr_ibcctrl, dd->cspec->ibcctrl); in qib_6120_set_ib_cfg()
2821 qib_write_kreg(dd, kr_scratch, 0); in qib_6120_set_ib_cfg()
2828 if (!dd->cspec->ibdeltainprog) { in qib_6120_set_ib_cfg()
2829 dd->cspec->ibdeltainprog = 1; in qib_6120_set_ib_cfg()
2830 dd->cspec->ibsymsnap = in qib_6120_set_ib_cfg()
2831 read_6120_creg32(dd, cr_ibsymbolerr); in qib_6120_set_ib_cfg()
2832 dd->cspec->iblnkerrsnap = in qib_6120_set_ib_cfg()
2833 read_6120_creg32(dd, cr_iblinkerrrecov); in qib_6120_set_ib_cfg()
2847 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16); in qib_6120_set_ib_cfg()
2869 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n", in qib_6120_set_ib_cfg()
2892 ppd->dd->cspec->ibcctrl |= SYM_MASK(IBCCtrl, Loopback); in qib_6120_set_loopback()
2893 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n", in qib_6120_set_loopback()
2894 ppd->dd->unit, ppd->port); in qib_6120_set_loopback()
2896 ppd->dd->cspec->ibcctrl &= ~SYM_MASK(IBCCtrl, Loopback); in qib_6120_set_loopback()
2897 qib_devinfo(ppd->dd->pcidev, in qib_6120_set_loopback()
2899 ppd->dd->unit, ppd->port); in qib_6120_set_loopback()
2903 qib_write_kreg(ppd->dd, kr_ibcctrl, ppd->dd->cspec->ibcctrl); in qib_6120_set_loopback()
2904 qib_write_kreg(ppd->dd, kr_scratch, 0); in qib_6120_set_loopback()
2944 struct qib_chip_specific *cs = ppd->dd->cspec; in qib_set_cntr_6120_sample()
3004 if (ppd->dd->cspec->ibdeltainprog) { in qib_6120_ib_updown()
3005 ppd->dd->cspec->ibdeltainprog = 0; in qib_6120_ib_updown()
3006 ppd->dd->cspec->ibsymdelta += in qib_6120_ib_updown()
3007 read_6120_creg32(ppd->dd, cr_ibsymbolerr) - in qib_6120_ib_updown()
3008 ppd->dd->cspec->ibsymsnap; in qib_6120_ib_updown()
3009 ppd->dd->cspec->iblnkerrdelta += in qib_6120_ib_updown()
3010 read_6120_creg32(ppd->dd, cr_iblinkerrrecov) - in qib_6120_ib_updown()
3011 ppd->dd->cspec->iblnkerrsnap; in qib_6120_ib_updown()
3015 ppd->dd->cspec->lli_counter = 0; in qib_6120_ib_updown()
3016 if (!ppd->dd->cspec->ibdeltainprog) { in qib_6120_ib_updown()
3017 ppd->dd->cspec->ibdeltainprog = 1; in qib_6120_ib_updown()
3018 ppd->dd->cspec->ibsymsnap = in qib_6120_ib_updown()
3019 read_6120_creg32(ppd->dd, cr_ibsymbolerr); in qib_6120_ib_updown()
3020 ppd->dd->cspec->iblnkerrsnap = in qib_6120_ib_updown()
3021 read_6120_creg32(ppd->dd, cr_iblinkerrrecov); in qib_6120_ib_updown()
3037 static int gpio_6120_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask) in gpio_6120_mod() argument
3046 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in gpio_6120_mod()
3047 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe)); in gpio_6120_mod()
3048 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe)); in gpio_6120_mod()
3049 new_out = (dd->cspec->gpio_out & ~mask) | out; in gpio_6120_mod()
3051 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); in gpio_6120_mod()
3052 qib_write_kreg(dd, kr_gpio_out, new_out); in gpio_6120_mod()
3053 dd->cspec->gpio_out = new_out; in gpio_6120_mod()
3054 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in gpio_6120_mod()
3064 read_val = qib_read_kreg64(dd, kr_extstatus); in gpio_6120_mod()
3073 static void get_6120_chip_params(struct qib_devdata *dd) in get_6120_chip_params() argument
3079 dd->uregbase = qib_read_kreg32(dd, kr_userregbase); in get_6120_chip_params()
3081 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt); in get_6120_chip_params()
3082 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase); in get_6120_chip_params()
3083 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase); in get_6120_chip_params()
3084 dd->palign = qib_read_kreg32(dd, kr_palign); in get_6120_chip_params()
3085 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase); in get_6120_chip_params()
3086 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff; in get_6120_chip_params()
3088 dd->rcvhdrcnt = qib_read_kreg32(dd, kr_rcvegrcnt); in get_6120_chip_params()
3090 val = qib_read_kreg64(dd, kr_sendpiosize); in get_6120_chip_params()
3091 dd->piosize2k = val & ~0U; in get_6120_chip_params()
3092 dd->piosize4k = val >> 32; in get_6120_chip_params()
3097 dd->pport->ibmtu = (u32)mtu; in get_6120_chip_params()
3099 val = qib_read_kreg64(dd, kr_sendpiobufcnt); in get_6120_chip_params()
3100 dd->piobcnt2k = val & ~0U; in get_6120_chip_params()
3101 dd->piobcnt4k = val >> 32; in get_6120_chip_params()
3102 dd->last_pio = dd->piobcnt4k + dd->piobcnt2k - 1; in get_6120_chip_params()
3104 dd->pio2kbase = (u32 __iomem *) in get_6120_chip_params()
3105 (((char __iomem *)dd->kregbase) + dd->pio2k_bufbase); in get_6120_chip_params()
3106 if (dd->piobcnt4k) { in get_6120_chip_params()
3107 dd->pio4kbase = (u32 __iomem *) in get_6120_chip_params()
3108 (((char __iomem *) dd->kregbase) + in get_6120_chip_params()
3109 (dd->piobufbase >> 32)); in get_6120_chip_params()
3115 dd->align4k = ALIGN(dd->piosize4k, dd->palign); in get_6120_chip_params()
3118 piobufs = dd->piobcnt4k + dd->piobcnt2k; in get_6120_chip_params()
3120 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) / in get_6120_chip_params()
3129 static void set_6120_baseaddrs(struct qib_devdata *dd) in set_6120_baseaddrs() argument
3133 cregbase = qib_read_kreg32(dd, kr_counterregbase); in set_6120_baseaddrs()
3134 dd->cspec->cregbase = (u64 __iomem *) in set_6120_baseaddrs()
3135 ((char __iomem *) dd->kregbase + cregbase); in set_6120_baseaddrs()
3137 dd->egrtidbase = (u64 __iomem *) in set_6120_baseaddrs()
3138 ((char __iomem *) dd->kregbase + dd->rcvegrbase); in set_6120_baseaddrs()
3146 static int qib_late_6120_initreg(struct qib_devdata *dd) in qib_late_6120_initreg() argument
3151 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize); in qib_late_6120_initreg()
3152 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize); in qib_late_6120_initreg()
3153 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt); in qib_late_6120_initreg()
3154 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys); in qib_late_6120_initreg()
3155 val = qib_read_kreg64(dd, kr_sendpioavailaddr); in qib_late_6120_initreg()
3156 if (val != dd->pioavailregs_phys) { in qib_late_6120_initreg()
3157 qib_dev_err(dd, in qib_late_6120_initreg()
3159 (unsigned long) dd->pioavailregs_phys, in qib_late_6120_initreg()
3166 static int init_6120_variables(struct qib_devdata *dd) in init_6120_variables() argument
3172 ppd = (struct qib_pportdata *)(dd + 1); in init_6120_variables()
3173 dd->pport = ppd; in init_6120_variables()
3174 dd->num_pports = 1; in init_6120_variables()
3176 dd->cspec = (struct qib_chip_specific *)(ppd + dd->num_pports); in init_6120_variables()
3177 dd->cspec->ppd = ppd; in init_6120_variables()
3180 spin_lock_init(&dd->cspec->kernel_tid_lock); in init_6120_variables()
3181 spin_lock_init(&dd->cspec->user_tid_lock); in init_6120_variables()
3182 spin_lock_init(&dd->cspec->rcvmod_lock); in init_6120_variables()
3183 spin_lock_init(&dd->cspec->gpio_lock); in init_6120_variables()
3186 dd->revision = readq(&dd->kregbase[kr_revision]); in init_6120_variables()
3188 if ((dd->revision & 0xffffffffU) == 0xffffffffU) { in init_6120_variables()
3189 qib_dev_err(dd, in init_6120_variables()
3194 dd->flags |= QIB_PRESENT; /* now register routines work */ in init_6120_variables()
3196 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R, in init_6120_variables()
3198 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R, in init_6120_variables()
3201 get_6120_chip_params(dd); in init_6120_variables()
3202 pe_boardname(dd); /* fill in boardname */ in init_6120_variables()
3208 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM; in init_6120_variables()
3209 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM; in init_6120_variables()
3210 dd->twsi_eeprom_dev = QIB_TWSI_NO_DEV; in init_6120_variables()
3213 dd->flags |= QIB_PIO_FLUSH_WC; in init_6120_variables()
3215 ret = qib_init_pportdata(ppd, dd, 0, 1); in init_6120_variables()
3228 dd->rcvhdrentsize = QIB_RCVHDR_ENTSIZE; in init_6120_variables()
3229 dd->rcvhdrsize = QIB_DFLT_RCVHDRSIZE; in init_6120_variables()
3230 dd->rhf_offset = 0; in init_6120_variables()
3234 dd->rcvegrbufsize = ret != -1 ? max(ret, 2048) : QIB_DEFAULT_MTU; in init_6120_variables()
3235 dd->rcvegrbufsize_shift = ilog2(dd->rcvegrbufsize); in init_6120_variables()
3237 qib_6120_tidtemplate(dd); in init_6120_variables()
3244 dd->rhdrhead_intr_off = 1ULL << 32; in init_6120_variables()
3247 timer_setup(&dd->stats_timer, qib_get_6120_faststats, 0); in init_6120_variables()
3248 timer_setup(&dd->cspec->pma_timer, pma_6120_timer, 0); in init_6120_variables()
3250 dd->ureg_align = qib_read_kreg32(dd, kr_palign); in init_6120_variables()
3252 dd->piosize2kmax_dwords = dd->piosize2k >> 2; in init_6120_variables()
3253 qib_6120_config_ctxts(dd); in init_6120_variables()
3254 qib_set_ctxtcnt(dd); in init_6120_variables()
3256 ret = init_chip_wc_pat(dd, 0); in init_6120_variables()
3259 set_6120_baseaddrs(dd); /* set chip access pointers now */ in init_6120_variables()
3267 ret = qib_create_ctxts(dd); in init_6120_variables()
3268 init_6120_cntrnames(dd); in init_6120_variables()
3271 sbufs = dd->piobcnt4k ? dd->piobcnt4k : 16; in init_6120_variables()
3273 dd->lastctxt_piobuf = dd->piobcnt2k + dd->piobcnt4k - sbufs; in init_6120_variables()
3274 dd->pbufsctxt = dd->lastctxt_piobuf / in init_6120_variables()
3275 (dd->cfgctxts - dd->first_user_ctxt); in init_6120_variables()
3301 u32 lbuf = ppd->dd->piobcnt2k + ppd->dd->piobcnt4k - 1; in get_6120_link_buf()
3307 sendctrl_6120_mod(ppd->dd->pport, QIB_SENDCTRL_AVAIL_BLIP); in get_6120_link_buf()
3308 qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */ in get_6120_link_buf()
3309 buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf); in get_6120_link_buf()
3315 ppd->dd->upd_pio_shadow = 1; /* update our idea of what's busy */ in get_6120_link_buf()
3316 qib_read_kreg64(ppd->dd, kr_scratch); /* extra chip flush */ in get_6120_link_buf()
3317 buf = qib_getsendbuf_range(ppd->dd, bnum, lbuf, lbuf); in get_6120_link_buf()
3326 struct qib_devdata *dd = ppd->dd; in qib_6120_getsendbuf() local
3334 if ((plen + 1) > dd->piosize2kmax_dwords) in qib_6120_getsendbuf()
3335 first = dd->piobcnt2k; in qib_6120_getsendbuf()
3339 last = dd->piobcnt2k + dd->piobcnt4k - 1; in qib_6120_getsendbuf()
3340 buf = qib_getsendbuf_range(dd, pbufnum, first, last); in qib_6120_getsendbuf()
3382 static void qib_6120_initvl15_bufs(struct qib_devdata *dd) in qib_6120_initvl15_bufs() argument
3388 rcd->rcvegrcnt = rcd->dd->rcvhdrcnt; in qib_6120_init_ctxt()
3392 static void qib_6120_txchk_change(struct qib_devdata *dd, u32 start, in qib_6120_txchk_change() argument
3397 static void writescratch(struct qib_devdata *dd, u32 val) in writescratch() argument
3399 (void) qib_write_kreg(dd, kr_scratch, val); in writescratch()
3402 static int qib_6120_tempsense_rd(struct qib_devdata *dd, int regnum) in qib_6120_tempsense_rd() argument
3408 static int qib_6120_notify_dca(struct qib_devdata *dd, unsigned long event) in qib_6120_notify_dca() argument
3415 static int qib_6120_eeprom_wen(struct qib_devdata *dd, int wen) in qib_6120_eeprom_wen() argument
3434 struct qib_devdata *dd; in qib_init_iba6120_funcs() local
3437 dd = qib_alloc_devdata(pdev, sizeof(struct qib_pportdata) + in qib_init_iba6120_funcs()
3439 if (IS_ERR(dd)) in qib_init_iba6120_funcs()
3442 dd->f_bringup_serdes = qib_6120_bringup_serdes; in qib_init_iba6120_funcs()
3443 dd->f_cleanup = qib_6120_setup_cleanup; in qib_init_iba6120_funcs()
3444 dd->f_clear_tids = qib_6120_clear_tids; in qib_init_iba6120_funcs()
3445 dd->f_free_irq = qib_free_irq; in qib_init_iba6120_funcs()
3446 dd->f_get_base_info = qib_6120_get_base_info; in qib_init_iba6120_funcs()
3447 dd->f_get_msgheader = qib_6120_get_msgheader; in qib_init_iba6120_funcs()
3448 dd->f_getsendbuf = qib_6120_getsendbuf; in qib_init_iba6120_funcs()
3449 dd->f_gpio_mod = gpio_6120_mod; in qib_init_iba6120_funcs()
3450 dd->f_eeprom_wen = qib_6120_eeprom_wen; in qib_init_iba6120_funcs()
3451 dd->f_hdrqempty = qib_6120_hdrqempty; in qib_init_iba6120_funcs()
3452 dd->f_ib_updown = qib_6120_ib_updown; in qib_init_iba6120_funcs()
3453 dd->f_init_ctxt = qib_6120_init_ctxt; in qib_init_iba6120_funcs()
3454 dd->f_initvl15_bufs = qib_6120_initvl15_bufs; in qib_init_iba6120_funcs()
3455 dd->f_intr_fallback = qib_6120_nointr_fallback; in qib_init_iba6120_funcs()
3456 dd->f_late_initreg = qib_late_6120_initreg; in qib_init_iba6120_funcs()
3457 dd->f_setpbc_control = qib_6120_setpbc_control; in qib_init_iba6120_funcs()
3458 dd->f_portcntr = qib_portcntr_6120; in qib_init_iba6120_funcs()
3459 dd->f_put_tid = (dd->minrev >= 2) ? in qib_init_iba6120_funcs()
3462 dd->f_quiet_serdes = qib_6120_quiet_serdes; in qib_init_iba6120_funcs()
3463 dd->f_rcvctrl = rcvctrl_6120_mod; in qib_init_iba6120_funcs()
3464 dd->f_read_cntrs = qib_read_6120cntrs; in qib_init_iba6120_funcs()
3465 dd->f_read_portcntrs = qib_read_6120portcntrs; in qib_init_iba6120_funcs()
3466 dd->f_reset = qib_6120_setup_reset; in qib_init_iba6120_funcs()
3467 dd->f_init_sdma_regs = init_sdma_6120_regs; in qib_init_iba6120_funcs()
3468 dd->f_sdma_busy = qib_sdma_6120_busy; in qib_init_iba6120_funcs()
3469 dd->f_sdma_gethead = qib_sdma_6120_gethead; in qib_init_iba6120_funcs()
3470 dd->f_sdma_sendctrl = qib_6120_sdma_sendctrl; in qib_init_iba6120_funcs()
3471 dd->f_sdma_set_desc_cnt = qib_sdma_set_6120_desc_cnt; in qib_init_iba6120_funcs()
3472 dd->f_sdma_update_tail = qib_sdma_update_6120_tail; in qib_init_iba6120_funcs()
3473 dd->f_sendctrl = sendctrl_6120_mod; in qib_init_iba6120_funcs()
3474 dd->f_set_armlaunch = qib_set_6120_armlaunch; in qib_init_iba6120_funcs()
3475 dd->f_set_cntr_sample = qib_set_cntr_6120_sample; in qib_init_iba6120_funcs()
3476 dd->f_iblink_state = qib_6120_iblink_state; in qib_init_iba6120_funcs()
3477 dd->f_ibphys_portstate = qib_6120_phys_portstate; in qib_init_iba6120_funcs()
3478 dd->f_get_ib_cfg = qib_6120_get_ib_cfg; in qib_init_iba6120_funcs()
3479 dd->f_set_ib_cfg = qib_6120_set_ib_cfg; in qib_init_iba6120_funcs()
3480 dd->f_set_ib_loopback = qib_6120_set_loopback; in qib_init_iba6120_funcs()
3481 dd->f_set_intr_state = qib_6120_set_intr_state; in qib_init_iba6120_funcs()
3482 dd->f_setextled = qib_6120_setup_setextled; in qib_init_iba6120_funcs()
3483 dd->f_txchk_change = qib_6120_txchk_change; in qib_init_iba6120_funcs()
3484 dd->f_update_usrhead = qib_update_6120_usrhead; in qib_init_iba6120_funcs()
3485 dd->f_wantpiobuf_intr = qib_wantpiobuf_6120_intr; in qib_init_iba6120_funcs()
3486 dd->f_xgxs_reset = qib_6120_xgxs_reset; in qib_init_iba6120_funcs()
3487 dd->f_writescratch = writescratch; in qib_init_iba6120_funcs()
3488 dd->f_tempsense_rd = qib_6120_tempsense_rd; in qib_init_iba6120_funcs()
3490 dd->f_notify_dca = qib_6120_notify_dca; in qib_init_iba6120_funcs()
3499 ret = qib_pcie_ddinit(dd, pdev, ent); in qib_init_iba6120_funcs()
3504 ret = init_6120_variables(dd); in qib_init_iba6120_funcs()
3511 if (qib_pcie_params(dd, 8, NULL)) in qib_init_iba6120_funcs()
3512 qib_dev_err(dd, in qib_init_iba6120_funcs()
3515 qib_write_kreg(dd, kr_hwdiagctrl, 0); in qib_init_iba6120_funcs()
3517 if (qib_read_kreg64(dd, kr_hwerrstatus) & in qib_init_iba6120_funcs()
3519 qib_write_kreg(dd, kr_hwerrclear, in qib_init_iba6120_funcs()
3523 qib_setup_6120_interrupt(dd); in qib_init_iba6120_funcs()
3525 qib_6120_init_hwerrors(dd); in qib_init_iba6120_funcs()
3530 qib_pcie_ddcleanup(dd); in qib_init_iba6120_funcs()
3532 qib_free_devdata(dd); in qib_init_iba6120_funcs()
3533 dd = ERR_PTR(ret); in qib_init_iba6120_funcs()
3535 return dd; in qib_init_iba6120_funcs()