Lines Matching +full:0 +full:x1
50 #define RDMA_CQE_RESPONDER_TOGGLE_BIT_MASK 0x1
51 #define RDMA_CQE_RESPONDER_TOGGLE_BIT_SHIFT 0
52 #define RDMA_CQE_RESPONDER_TYPE_MASK 0x3
54 #define RDMA_CQE_RESPONDER_INV_FLG_MASK 0x1
56 #define RDMA_CQE_RESPONDER_IMM_FLG_MASK 0x1
58 #define RDMA_CQE_RESPONDER_RDMA_FLG_MASK 0x1
60 #define RDMA_CQE_RESPONDER_RESERVED2_MASK 0x3
74 #define RDMA_CQE_REQUESTER_TOGGLE_BIT_MASK 0x1
75 #define RDMA_CQE_REQUESTER_TOGGLE_BIT_SHIFT 0
76 #define RDMA_CQE_REQUESTER_TYPE_MASK 0x3
78 #define RDMA_CQE_REQUESTER_RESERVED5_MASK 0x1F
88 #define RDMA_CQE_COMMON_TOGGLE_BIT_MASK 0x1
89 #define RDMA_CQE_COMMON_TOGGLE_BIT_SHIFT 0
90 #define RDMA_CQE_COMMON_TYPE_MASK 0x3
92 #define RDMA_CQE_COMMON_RESERVED2_MASK 0x1F
156 #define RDMA_RQ_SGE_L_KEY_LO_MASK 0x3FFFFFF
157 #define RDMA_RQ_SGE_L_KEY_LO_SHIFT 0
158 #define RDMA_RQ_SGE_NUM_SGES_MASK 0x7
160 #define RDMA_RQ_SGE_L_KEY_HI_MASK 0x7
204 #define RDMA_PWM_VAL32_DATA_AGG_CMD_MASK 0x3
205 #define RDMA_PWM_VAL32_DATA_AGG_CMD_SHIFT 0
206 #define RDMA_PWM_VAL32_DATA_BYPASS_EN_MASK 0x1
208 #define RDMA_PWM_VAL32_DATA_CONN_TYPE_IS_IWARP_MASK 0x1
210 #define RDMA_PWM_VAL32_DATA_SET_16B_VAL_MASK 0x1
212 #define RDMA_PWM_VAL32_DATA_RESERVED_MASK 0x7
219 RDMA_DIF_BLOCK_512 = 0,
226 RDMA_DIF_CRC_SEED_0000 = 0,
236 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_CRC_MASK 0x1
237 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_CRC_SHIFT 0
238 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_APP_TAG_MASK 0x1
240 #define RDMA_DIF_ERROR_RESULT_DIF_ERROR_TYPE_REF_TAG_MASK 0x1
242 #define RDMA_DIF_ERROR_RESULT_RESERVED0_MASK 0xF
244 #define RDMA_DIF_ERROR_RESULT_TOGGLE_BIT_MASK 0x1
251 RDMA_DIF_DIR_RX = 0,
262 #define RDMA_DIF_PARAMS_IO_DIRECTION_FLG_MASK 0x1
263 #define RDMA_DIF_PARAMS_IO_DIRECTION_FLG_SHIFT 0
264 #define RDMA_DIF_PARAMS_BLOCK_SIZE_MASK 0x1
266 #define RDMA_DIF_PARAMS_RUNT_VALID_FLG_MASK 0x1
268 #define RDMA_DIF_PARAMS_VALIDATE_CRC_GUARD_MASK 0x1
270 #define RDMA_DIF_PARAMS_VALIDATE_REF_TAG_MASK 0x1
272 #define RDMA_DIF_PARAMS_VALIDATE_APP_TAG_MASK 0x1
274 #define RDMA_DIF_PARAMS_CRC_SEED_MASK 0x1
276 #define RDMA_DIF_PARAMS_RX_REF_TAG_CONST_MASK 0x1
278 #define RDMA_DIF_PARAMS_BLOCK_GUARD_TYPE_MASK 0x1
280 #define RDMA_DIF_PARAMS_APP_ESCAPE_MASK 0x1
282 #define RDMA_DIF_PARAMS_REF_ESCAPE_MASK 0x1
284 #define RDMA_DIF_PARAMS_RESERVED4_MASK 0x1F
296 #define RDMA_SQ_ATOMIC_WQE_COMP_FLG_MASK 0x1
297 #define RDMA_SQ_ATOMIC_WQE_COMP_FLG_SHIFT 0
298 #define RDMA_SQ_ATOMIC_WQE_RD_FENCE_FLG_MASK 0x1
300 #define RDMA_SQ_ATOMIC_WQE_INV_FENCE_FLG_MASK 0x1
302 #define RDMA_SQ_ATOMIC_WQE_SE_FLG_MASK 0x1
304 #define RDMA_SQ_ATOMIC_WQE_INLINE_FLG_MASK 0x1
306 #define RDMA_SQ_ATOMIC_WQE_DIF_ON_HOST_FLG_MASK 0x1
308 #define RDMA_SQ_ATOMIC_WQE_RESERVED0_MASK 0x3
326 #define RDMA_SQ_ATOMIC_WQE_1ST_COMP_FLG_MASK 0x1
327 #define RDMA_SQ_ATOMIC_WQE_1ST_COMP_FLG_SHIFT 0
328 #define RDMA_SQ_ATOMIC_WQE_1ST_RD_FENCE_FLG_MASK 0x1
330 #define RDMA_SQ_ATOMIC_WQE_1ST_INV_FENCE_FLG_MASK 0x1
332 #define RDMA_SQ_ATOMIC_WQE_1ST_SE_FLG_MASK 0x1
334 #define RDMA_SQ_ATOMIC_WQE_1ST_INLINE_FLG_MASK 0x1
336 #define RDMA_SQ_ATOMIC_WQE_1ST_RESERVED0_MASK 0x7
360 #define RDMA_SQ_BIND_WQE_COMP_FLG_MASK 0x1
361 #define RDMA_SQ_BIND_WQE_COMP_FLG_SHIFT 0
362 #define RDMA_SQ_BIND_WQE_RD_FENCE_FLG_MASK 0x1
364 #define RDMA_SQ_BIND_WQE_INV_FENCE_FLG_MASK 0x1
366 #define RDMA_SQ_BIND_WQE_SE_FLG_MASK 0x1
368 #define RDMA_SQ_BIND_WQE_INLINE_FLG_MASK 0x1
370 #define RDMA_SQ_BIND_WQE_DIF_ON_HOST_FLG_MASK 0x1
372 #define RDMA_SQ_BIND_WQE_RESERVED0_MASK 0x3
377 #define RDMA_SQ_BIND_WQE_ZERO_BASED_MASK 0x1
378 #define RDMA_SQ_BIND_WQE_ZERO_BASED_SHIFT 0
379 #define RDMA_SQ_BIND_WQE_RESERVED1_MASK 0x7F
382 #define RDMA_SQ_BIND_WQE_REMOTE_READ_MASK 0x1
383 #define RDMA_SQ_BIND_WQE_REMOTE_READ_SHIFT 0
384 #define RDMA_SQ_BIND_WQE_REMOTE_WRITE_MASK 0x1
386 #define RDMA_SQ_BIND_WQE_ENABLE_ATOMIC_MASK 0x1
388 #define RDMA_SQ_BIND_WQE_LOCAL_READ_MASK 0x1
390 #define RDMA_SQ_BIND_WQE_LOCAL_WRITE_MASK 0x1
392 #define RDMA_SQ_BIND_WQE_RESERVED2_MASK 0x7
408 #define RDMA_SQ_BIND_WQE_1ST_COMP_FLG_MASK 0x1
409 #define RDMA_SQ_BIND_WQE_1ST_COMP_FLG_SHIFT 0
410 #define RDMA_SQ_BIND_WQE_1ST_RD_FENCE_FLG_MASK 0x1
412 #define RDMA_SQ_BIND_WQE_1ST_INV_FENCE_FLG_MASK 0x1
414 #define RDMA_SQ_BIND_WQE_1ST_SE_FLG_MASK 0x1
416 #define RDMA_SQ_BIND_WQE_1ST_INLINE_FLG_MASK 0x1
418 #define RDMA_SQ_BIND_WQE_1ST_RESERVED0_MASK 0x7
427 #define RDMA_SQ_BIND_WQE_2ND_ZERO_BASED_MASK 0x1
428 #define RDMA_SQ_BIND_WQE_2ND_ZERO_BASED_SHIFT 0
429 #define RDMA_SQ_BIND_WQE_2ND_RESERVED1_MASK 0x7F
432 #define RDMA_SQ_BIND_WQE_2ND_REMOTE_READ_MASK 0x1
433 #define RDMA_SQ_BIND_WQE_2ND_REMOTE_READ_SHIFT 0
434 #define RDMA_SQ_BIND_WQE_2ND_REMOTE_WRITE_MASK 0x1
436 #define RDMA_SQ_BIND_WQE_2ND_ENABLE_ATOMIC_MASK 0x1
438 #define RDMA_SQ_BIND_WQE_2ND_LOCAL_READ_MASK 0x1
440 #define RDMA_SQ_BIND_WQE_2ND_LOCAL_WRITE_MASK 0x1
442 #define RDMA_SQ_BIND_WQE_2ND_RESERVED2_MASK 0x7
463 #define RDMA_SQ_COMMON_WQE_COMP_FLG_MASK 0x1
464 #define RDMA_SQ_COMMON_WQE_COMP_FLG_SHIFT 0
465 #define RDMA_SQ_COMMON_WQE_RD_FENCE_FLG_MASK 0x1
467 #define RDMA_SQ_COMMON_WQE_INV_FENCE_FLG_MASK 0x1
469 #define RDMA_SQ_COMMON_WQE_SE_FLG_MASK 0x1
471 #define RDMA_SQ_COMMON_WQE_INLINE_FLG_MASK 0x1
473 #define RDMA_SQ_COMMON_WQE_RESERVED0_MASK 0x7
484 #define RDMA_SQ_FMR_WQE_COMP_FLG_MASK 0x1
485 #define RDMA_SQ_FMR_WQE_COMP_FLG_SHIFT 0
486 #define RDMA_SQ_FMR_WQE_RD_FENCE_FLG_MASK 0x1
488 #define RDMA_SQ_FMR_WQE_INV_FENCE_FLG_MASK 0x1
490 #define RDMA_SQ_FMR_WQE_SE_FLG_MASK 0x1
492 #define RDMA_SQ_FMR_WQE_INLINE_FLG_MASK 0x1
494 #define RDMA_SQ_FMR_WQE_DIF_ON_HOST_FLG_MASK 0x1
496 #define RDMA_SQ_FMR_WQE_RESERVED0_MASK 0x3
501 #define RDMA_SQ_FMR_WQE_PAGE_SIZE_LOG_MASK 0x1F
502 #define RDMA_SQ_FMR_WQE_PAGE_SIZE_LOG_SHIFT 0
503 #define RDMA_SQ_FMR_WQE_ZERO_BASED_MASK 0x1
505 #define RDMA_SQ_FMR_WQE_BIND_EN_MASK 0x1
507 #define RDMA_SQ_FMR_WQE_RESERVED1_MASK 0x1
510 #define RDMA_SQ_FMR_WQE_REMOTE_READ_MASK 0x1
511 #define RDMA_SQ_FMR_WQE_REMOTE_READ_SHIFT 0
512 #define RDMA_SQ_FMR_WQE_REMOTE_WRITE_MASK 0x1
514 #define RDMA_SQ_FMR_WQE_ENABLE_ATOMIC_MASK 0x1
516 #define RDMA_SQ_FMR_WQE_LOCAL_READ_MASK 0x1
518 #define RDMA_SQ_FMR_WQE_LOCAL_WRITE_MASK 0x1
520 #define RDMA_SQ_FMR_WQE_RESERVED2_MASK 0x7
534 #define RDMA_SQ_FMR_WQE_1ST_COMP_FLG_MASK 0x1
535 #define RDMA_SQ_FMR_WQE_1ST_COMP_FLG_SHIFT 0
536 #define RDMA_SQ_FMR_WQE_1ST_RD_FENCE_FLG_MASK 0x1
538 #define RDMA_SQ_FMR_WQE_1ST_INV_FENCE_FLG_MASK 0x1
540 #define RDMA_SQ_FMR_WQE_1ST_SE_FLG_MASK 0x1
542 #define RDMA_SQ_FMR_WQE_1ST_INLINE_FLG_MASK 0x1
544 #define RDMA_SQ_FMR_WQE_1ST_DIF_ON_HOST_FLG_MASK 0x1
546 #define RDMA_SQ_FMR_WQE_1ST_RESERVED0_MASK 0x3
555 #define RDMA_SQ_FMR_WQE_2ND_PAGE_SIZE_LOG_MASK 0x1F
556 #define RDMA_SQ_FMR_WQE_2ND_PAGE_SIZE_LOG_SHIFT 0
557 #define RDMA_SQ_FMR_WQE_2ND_ZERO_BASED_MASK 0x1
559 #define RDMA_SQ_FMR_WQE_2ND_BIND_EN_MASK 0x1
561 #define RDMA_SQ_FMR_WQE_2ND_RESERVED1_MASK 0x1
564 #define RDMA_SQ_FMR_WQE_2ND_REMOTE_READ_MASK 0x1
565 #define RDMA_SQ_FMR_WQE_2ND_REMOTE_READ_SHIFT 0
566 #define RDMA_SQ_FMR_WQE_2ND_REMOTE_WRITE_MASK 0x1
568 #define RDMA_SQ_FMR_WQE_2ND_ENABLE_ATOMIC_MASK 0x1
570 #define RDMA_SQ_FMR_WQE_2ND_LOCAL_READ_MASK 0x1
572 #define RDMA_SQ_FMR_WQE_2ND_LOCAL_WRITE_MASK 0x1
574 #define RDMA_SQ_FMR_WQE_2ND_RESERVED2_MASK 0x7
588 #define RDMA_SQ_LOCAL_INV_WQE_COMP_FLG_MASK 0x1
589 #define RDMA_SQ_LOCAL_INV_WQE_COMP_FLG_SHIFT 0
590 #define RDMA_SQ_LOCAL_INV_WQE_RD_FENCE_FLG_MASK 0x1
592 #define RDMA_SQ_LOCAL_INV_WQE_INV_FENCE_FLG_MASK 0x1
594 #define RDMA_SQ_LOCAL_INV_WQE_SE_FLG_MASK 0x1
596 #define RDMA_SQ_LOCAL_INV_WQE_INLINE_FLG_MASK 0x1
598 #define RDMA_SQ_LOCAL_INV_WQE_DIF_ON_HOST_FLG_MASK 0x1
600 #define RDMA_SQ_LOCAL_INV_WQE_RESERVED0_MASK 0x3
612 #define RDMA_SQ_RDMA_WQE_COMP_FLG_MASK 0x1
613 #define RDMA_SQ_RDMA_WQE_COMP_FLG_SHIFT 0
614 #define RDMA_SQ_RDMA_WQE_RD_FENCE_FLG_MASK 0x1
616 #define RDMA_SQ_RDMA_WQE_INV_FENCE_FLG_MASK 0x1
618 #define RDMA_SQ_RDMA_WQE_SE_FLG_MASK 0x1
620 #define RDMA_SQ_RDMA_WQE_INLINE_FLG_MASK 0x1
622 #define RDMA_SQ_RDMA_WQE_DIF_ON_HOST_FLG_MASK 0x1
624 #define RDMA_SQ_RDMA_WQE_READ_INV_FLG_MASK 0x1
626 #define RDMA_SQ_RDMA_WQE_RESERVED1_MASK 0x1
633 #define RDMA_SQ_RDMA_WQE_DIF_BLOCK_SIZE_MASK 0x1
634 #define RDMA_SQ_RDMA_WQE_DIF_BLOCK_SIZE_SHIFT 0
635 #define RDMA_SQ_RDMA_WQE_RESERVED2_MASK 0x7F
647 #define RDMA_SQ_RDMA_WQE_1ST_COMP_FLG_MASK 0x1
648 #define RDMA_SQ_RDMA_WQE_1ST_COMP_FLG_SHIFT 0
649 #define RDMA_SQ_RDMA_WQE_1ST_RD_FENCE_FLG_MASK 0x1
651 #define RDMA_SQ_RDMA_WQE_1ST_INV_FENCE_FLG_MASK 0x1
653 #define RDMA_SQ_RDMA_WQE_1ST_SE_FLG_MASK 0x1
655 #define RDMA_SQ_RDMA_WQE_1ST_INLINE_FLG_MASK 0x1
657 #define RDMA_SQ_RDMA_WQE_1ST_DIF_ON_HOST_FLG_MASK 0x1
659 #define RDMA_SQ_RDMA_WQE_1ST_READ_INV_FLG_MASK 0x1
661 #define RDMA_SQ_RDMA_WQE_1ST_RESERVED0_MASK 0x1
672 #define RDMA_SQ_RDMA_WQE_2ND_DIF_BLOCK_SIZE_MASK 0x1
673 #define RDMA_SQ_RDMA_WQE_2ND_DIF_BLOCK_SIZE_SHIFT 0
674 #define RDMA_SQ_RDMA_WQE_2ND_DIF_FIRST_SEGMENT_FLG_MASK 0x1
676 #define RDMA_SQ_RDMA_WQE_2ND_DIF_LAST_SEGMENT_FLG_MASK 0x1
678 #define RDMA_SQ_RDMA_WQE_2ND_RESERVED1_MASK 0x1F
706 #define RDMA_SQ_SEND_WQE_COMP_FLG_MASK 0x1
707 #define RDMA_SQ_SEND_WQE_COMP_FLG_SHIFT 0
708 #define RDMA_SQ_SEND_WQE_RD_FENCE_FLG_MASK 0x1
710 #define RDMA_SQ_SEND_WQE_INV_FENCE_FLG_MASK 0x1
712 #define RDMA_SQ_SEND_WQE_SE_FLG_MASK 0x1
714 #define RDMA_SQ_SEND_WQE_INLINE_FLG_MASK 0x1
716 #define RDMA_SQ_SEND_WQE_DIF_ON_HOST_FLG_MASK 0x1
718 #define RDMA_SQ_SEND_WQE_RESERVED0_MASK 0x3
731 #define RDMA_SQ_SEND_WQE_1ST_COMP_FLG_MASK 0x1
732 #define RDMA_SQ_SEND_WQE_1ST_COMP_FLG_SHIFT 0
733 #define RDMA_SQ_SEND_WQE_1ST_RD_FENCE_FLG_MASK 0x1
735 #define RDMA_SQ_SEND_WQE_1ST_INV_FENCE_FLG_MASK 0x1
737 #define RDMA_SQ_SEND_WQE_1ST_SE_FLG_MASK 0x1
739 #define RDMA_SQ_SEND_WQE_1ST_INLINE_FLG_MASK 0x1
741 #define RDMA_SQ_SEND_WQE_1ST_RESERVED0_MASK 0x7