Lines Matching +full:rx +full:- +full:eq
2 * Copyright(c) 2015 - 2019 Intel Corporation.
24 * - Redistributions of source code must retain the above copyright
26 * - Redistributions in binary form must reproduce the above copyright
30 * - Neither the name of Intel Corporation nor the names of its
69 struct pci_dev *pdev = dd->pcidev; in hfi1_pcie_init()
85 dd_dev_err(dd, "pci enable failed: error %d\n", -ret); in hfi1_pcie_init()
91 dd_dev_err(dd, "pci_request_regions fails: err %d\n", -ret); in hfi1_pcie_init()
140 * fields required to re-initialize after a chip reset, or for
161 return -EINVAL; in hfi1_pcie_ddinit()
164 dd->kregbase1 = ioremap(addr, RCV_ARRAY); in hfi1_pcie_ddinit()
165 if (!dd->kregbase1) { in hfi1_pcie_ddinit()
167 return -ENOMEM; in hfi1_pcie_ddinit()
169 dd_dev_info(dd, "UC base1: %p for %x\n", dd->kregbase1, RCV_ARRAY); in hfi1_pcie_ddinit()
172 dd->revision = readq(dd->kregbase1 + CCE_REVISION); in hfi1_pcie_ddinit()
173 if (dd->revision == ~(u64)0) { in hfi1_pcie_ddinit()
178 rcv_array_count = readq(dd->kregbase1 + RCV_ARRAY_CNT); in hfi1_pcie_ddinit()
180 dd->base2_start = RCV_ARRAY + rcv_array_count * 8; in hfi1_pcie_ddinit()
182 dd->kregbase2 = ioremap( in hfi1_pcie_ddinit()
183 addr + dd->base2_start, in hfi1_pcie_ddinit()
184 TXE_PIO_SEND - dd->base2_start); in hfi1_pcie_ddinit()
185 if (!dd->kregbase2) { in hfi1_pcie_ddinit()
189 dd_dev_info(dd, "UC base2: %p for %x\n", dd->kregbase2, in hfi1_pcie_ddinit()
190 TXE_PIO_SEND - dd->base2_start); in hfi1_pcie_ddinit()
192 dd->piobase = ioremap_wc(addr + TXE_PIO_SEND, TXE_PIO_SIZE); in hfi1_pcie_ddinit()
193 if (!dd->piobase) { in hfi1_pcie_ddinit()
197 dd_dev_info(dd, "WC piobase: %p for %x\n", dd->piobase, TXE_PIO_SIZE); in hfi1_pcie_ddinit()
199 dd->physaddr = addr; /* used for io_remap, etc. */ in hfi1_pcie_ddinit()
202 * Map the chip's RcvArray as write-combining to allow us in hfi1_pcie_ddinit()
205 dd->rcvarray_wc = ioremap_wc(addr + RCV_ARRAY, in hfi1_pcie_ddinit()
207 if (!dd->rcvarray_wc) { in hfi1_pcie_ddinit()
212 dd->rcvarray_wc, rcv_array_count * 8); in hfi1_pcie_ddinit()
214 dd->flags |= HFI1_PRESENT; /* chip.c CSR routines now work */ in hfi1_pcie_ddinit()
217 ret = -ENOMEM; in hfi1_pcie_ddinit()
223 * Do PCIe cleanup related to dd, after chip-specific cleanup, etc. Just prior
229 dd->flags &= ~HFI1_PRESENT; in hfi1_pcie_ddcleanup()
230 if (dd->kregbase1) in hfi1_pcie_ddcleanup()
231 iounmap(dd->kregbase1); in hfi1_pcie_ddcleanup()
232 dd->kregbase1 = NULL; in hfi1_pcie_ddcleanup()
233 if (dd->kregbase2) in hfi1_pcie_ddcleanup()
234 iounmap(dd->kregbase2); in hfi1_pcie_ddcleanup()
235 dd->kregbase2 = NULL; in hfi1_pcie_ddcleanup()
236 if (dd->rcvarray_wc) in hfi1_pcie_ddcleanup()
237 iounmap(dd->rcvarray_wc); in hfi1_pcie_ddcleanup()
238 dd->rcvarray_wc = NULL; in hfi1_pcie_ddcleanup()
239 if (dd->piobase) in hfi1_pcie_ddcleanup()
240 iounmap(dd->piobase); in hfi1_pcie_ddcleanup()
241 dd->piobase = NULL; in hfi1_pcie_ddcleanup()
270 /* read the link status and set dd->{lbus_width,lbus_speed,lbus_info} */
276 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat); in update_lbus_info()
282 dd->lbus_width = extract_width(linkstat); in update_lbus_info()
283 dd->lbus_speed = extract_speed(linkstat); in update_lbus_info()
284 snprintf(dd->lbus_info, sizeof(dd->lbus_info), in update_lbus_info()
285 "PCIe,%uMHz,x%u", dd->lbus_speed, dd->lbus_width); in update_lbus_info()
295 struct pci_dev *parent = dd->pcidev->bus->self; in pcie_speeds()
298 if (!pci_is_pcie(dd->pcidev)) { in pcie_speeds()
300 return -EINVAL; in pcie_speeds()
304 dd->link_gen3_capable = 1; in pcie_speeds()
306 ret = pcie_capability_read_dword(dd->pcidev, PCI_EXP_LNKCAP, &linkcap); in pcie_speeds()
316 dd->link_gen3_capable = 0; in pcie_speeds()
320 * bus->max_bus_speed is set from the bridge's linkcap Max Link Speed in pcie_speeds()
323 (dd->pcidev->bus->max_bus_speed == PCIE_SPEED_2_5GT || in pcie_speeds()
324 dd->pcidev->bus->max_bus_speed == PCIE_SPEED_5_0GT)) { in pcie_speeds()
326 dd->link_gen3_capable = 0; in pcie_speeds()
332 dd_dev_info(dd, "%s\n", dd->lbus_info); in pcie_speeds()
346 ret = pci_write_config_word(dd->pcidev, PCI_COMMAND, dd->pci_command); in restore_pci_variables()
350 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, in restore_pci_variables()
351 dd->pcibar0); in restore_pci_variables()
355 ret = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, in restore_pci_variables()
356 dd->pcibar1); in restore_pci_variables()
360 ret = pci_write_config_dword(dd->pcidev, PCI_ROM_ADDRESS, dd->pci_rom); in restore_pci_variables()
364 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, in restore_pci_variables()
365 dd->pcie_devctl); in restore_pci_variables()
369 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL, in restore_pci_variables()
370 dd->pcie_lnkctl); in restore_pci_variables()
374 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL2, in restore_pci_variables()
375 dd->pcie_devctl2); in restore_pci_variables()
379 ret = pci_write_config_dword(dd->pcidev, PCI_CFG_MSIX0, dd->pci_msix0); in restore_pci_variables()
383 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) { in restore_pci_variables()
384 ret = pci_write_config_dword(dd->pcidev, PCIE_CFG_TPH2, in restore_pci_variables()
385 dd->pci_tph2); in restore_pci_variables()
405 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, in save_pci_variables()
406 &dd->pcibar0); in save_pci_variables()
410 ret = pci_read_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, in save_pci_variables()
411 &dd->pcibar1); in save_pci_variables()
415 ret = pci_read_config_dword(dd->pcidev, PCI_ROM_ADDRESS, &dd->pci_rom); in save_pci_variables()
419 ret = pci_read_config_word(dd->pcidev, PCI_COMMAND, &dd->pci_command); in save_pci_variables()
423 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, in save_pci_variables()
424 &dd->pcie_devctl); in save_pci_variables()
428 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL, in save_pci_variables()
429 &dd->pcie_lnkctl); in save_pci_variables()
433 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL2, in save_pci_variables()
434 &dd->pcie_devctl2); in save_pci_variables()
438 ret = pci_read_config_dword(dd->pcidev, PCI_CFG_MSIX0, &dd->pci_msix0); in save_pci_variables()
442 if (pci_find_ext_capability(dd->pcidev, PCI_EXT_CAP_ID_TPH)) { in save_pci_variables()
443 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_TPH2, in save_pci_variables()
444 &dd->pci_tph2); in save_pci_variables()
456 * BIOS may not set PCIe bus-utilization parameters for best performance.
464 * tune_pcie_caps() - Code to adjust PCIe capabilities.
479 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl); in tune_pcie_caps()
483 ret = pcie_capability_write_word(dd->pcidev, in tune_pcie_caps()
489 parent = dd->pcidev->bus->self; in tune_pcie_caps()
498 if (!pci_is_root_bus(parent->bus)) { in tune_pcie_caps()
506 if (!pci_is_pcie(dd->pcidev)) { in tune_pcie_caps()
510 rc_mpss = parent->pcie_mpss; in tune_pcie_caps()
511 rc_mps = ffs(pcie_get_mps(parent)) - 8; in tune_pcie_caps()
513 ep_mpss = dd->pcidev->pcie_mpss; in tune_pcie_caps()
514 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8; in tune_pcie_caps()
531 pcie_set_mps(dd->pcidev, 128 << ep_mps); in tune_pcie_caps()
537 * which is code '5' (log2(4096) - 7) in tune_pcie_caps()
545 ep_mrrs = pcie_get_readrq(dd->pcidev); in tune_pcie_caps()
553 pcie_set_readrq(dd->pcidev, ep_mrrs); in tune_pcie_caps()
584 dd->flags &= ~HFI1_PRESENT; in pci_error_detected()
606 if (dd && dd->pport) { in pci_mmio_enabled()
607 words = read_port_cntr(dd->pport, C_RX_WORDS, CNTR_INVALID_VL); in pci_mmio_enabled()
634 * unlike sysfs-requested reset. Better than in pci_resume()
637 hfi1_init(dd, 1); /* same as re-init after reset */ in pci_resume()
675 MODULE_PARM_DESC(pcie_target, "PCIe target speed (0 skip, 1-3 Gen1-3)");
690 MODULE_PARM_DESC(pcie_pset, "PCIe Eq Pset value to use, range is 0-10");
694 MODULE_PARM_DESC(pcie_ctle, "PCIe static CTLE mode, bit 0 - discrete on/off, bit 1 - integrated on/…
772 * Load the given EQ preset table into the PCIe hardware.
774 static int load_eq_table(struct hfi1_devdata *dd, const u8 eq[11][3], u8 fs, in load_eq_table()
777 struct pci_dev *pdev = dd->pcidev; in load_eq_table()
788 c_minus1 = eq[i][PREC] / div; in load_eq_table()
789 c0 = fs - (eq[i][PREC] / div) - (eq[i][POST] / div); in load_eq_table()
790 c_plus1 = eq[i][POST] / div; in load_eq_table()
793 /* check if these coefficients violate EQ rules */ in load_eq_table()
794 ret = pci_read_config_dword(dd->pcidev, in load_eq_table()
806 "Gen3 EQ Table Coefficient rule violations\n"); in load_eq_table()
810 i, (u32)eq[i][0], (u32)eq[i][1], in load_eq_table()
811 (u32)eq[i][2]); in load_eq_table()
818 return -EINVAL; in load_eq_table()
840 sbus_request(dd, pcie_pcs_addrs[dd->hfi1_id][i], in pcie_post_steps()
855 struct pci_dev *dev = dd->pcidev; in trigger_sbr()
859 if (!dev->bus->self) { in trigger_sbr()
861 return -ENOTTY; in trigger_sbr()
865 list_for_each_entry(pdev, &dev->bus->devices, bus_list) in trigger_sbr()
870 return -ENOTTY; in trigger_sbr()
878 return pci_bridge_secondary_bus_reset(dev->bus->self); in trigger_sbr()
899 reg = (((u64)1 << dd->hfi1_id) << in arm_gasket_logic()
901 ((u64)pcie_serdes_broadcast[dd->hfi1_id] << in arm_gasket_logic()
928 * Write xmt_margin for full-swing (WFR-B) or half-swing (WFR-C).
941 * For Discrete, use full-swing. in write_xmt_margin()
942 * - PCIe TX defaults to full-swing. in write_xmt_margin()
944 * For Integrated, use half-swing in write_xmt_margin()
945 * - Copy xmt_margin and xmt_margin_oe in write_xmt_margin()
948 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL1) { /* integrated */ in write_xmt_margin()
993 struct pci_dev *parent = dd->pcidev->bus->self; in do_pcie_gen3_transition()
1006 const u8 (*eq)[3]; in do_pcie_gen3_transition() local
1013 if (dd->icode != ICODE_RTL_SILICON) in do_pcie_gen3_transition()
1026 /* off or invalid target - skip */ in do_pcie_gen3_transition()
1032 if (dd->lbus_speed == target_speed) { in do_pcie_gen3_transition()
1035 pcie_force ? "re-doing anyway" : "skipping"); in do_pcie_gen3_transition()
1051 target_width = dd->lbus_width; in do_pcie_gen3_transition()
1061 if (pcie_target == 3 && !dd->link_gen3_capable) { in do_pcie_gen3_transition()
1063 ret = -ENOSYS; in do_pcie_gen3_transition()
1101 * PcieCfgSpcie1 - Link Control 3 in do_pcie_gen3_transition()
1102 * Leave at reset value. No need to set PerfEq - link equalization in do_pcie_gen3_transition()
1107 /* clear all 16 per-lane error bits (PCIe: Lane Error Status) */ in do_pcie_gen3_transition()
1108 pci_write_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, 0xffff); in do_pcie_gen3_transition()
1113 * PcieCfgRegPl2 - Port Force Link in do_pcie_gen3_transition()
1119 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32); in do_pcie_gen3_transition()
1122 * PcieCfgRegPl100 - Gen3 Control in do_pcie_gen3_transition()
1129 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32); in do_pcie_gen3_transition()
1132 * PcieCfgRegPl101 - Gen3 EQ FS and LF in do_pcie_gen3_transition()
1133 * PcieCfgRegPl102 - Gen3 EQ Presets to Coefficients Mapping in do_pcie_gen3_transition()
1134 * PcieCfgRegPl103 - Gen3 EQ Preset Index in do_pcie_gen3_transition()
1135 * PcieCfgRegPl105 - Gen3 EQ Status in do_pcie_gen3_transition()
1137 * Give initial EQ settings. in do_pcie_gen3_transition()
1139 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0) { /* discrete */ in do_pcie_gen3_transition()
1144 eq = discrete_preliminary_eq; in do_pcie_gen3_transition()
1147 /* bit 0 - discrete on/off */ in do_pcie_gen3_transition()
1154 eq = integrated_preliminary_eq; in do_pcie_gen3_transition()
1157 /* bit 1 - integrated on/off */ in do_pcie_gen3_transition()
1160 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL101, in do_pcie_gen3_transition()
1165 ret = load_eq_table(dd, eq, fs, div); in do_pcie_gen3_transition()
1170 * PcieCfgRegPl106 - Gen3 EQ Control in do_pcie_gen3_transition()
1176 if (pset > 10) { /* valid range is 0-10, inclusive */ in do_pcie_gen3_transition()
1177 dd_dev_err(dd, "%s: Invalid Eq Pset %u, setting to %d\n", in do_pcie_gen3_transition()
1181 dd_dev_info(dd, "%s: using EQ Pset %u\n", __func__, pset); in do_pcie_gen3_transition()
1182 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL106, in do_pcie_gen3_transition()
1197 /* set the Rx Bit Rate to REFCLK ratio */ in do_pcie_gen3_transition()
1199 /* disable pCal for PCIe Gen3 RX equalization */ in do_pcie_gen3_transition()
1204 * Enable iCal for PCIe Gen3 RX equalization, and set which in do_pcie_gen3_transition()
1282 ret = pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKCTL2, &lnkctl2); in do_pcie_gen3_transition()
1295 ret = pcie_capability_write_word(dd->pcidev, PCI_EXP_LNKCTL2, lnkctl2); in do_pcie_gen3_transition()
1333 ret = pci_read_config_word(dd->pcidev, PCI_VENDOR_ID, &vendor); in do_pcie_gen3_transition()
1344 ret = -EIO; in do_pcie_gen3_transition()
1368 * the SBR. Then check for any per-lane errors. Then look over in do_pcie_gen3_transition()
1374 dd_dev_err(dd, "SBR failed - unable to read from device\n"); in do_pcie_gen3_transition()
1376 ret = -ENOSYS; in do_pcie_gen3_transition()
1386 /* check for any per-lane errors */ in do_pcie_gen3_transition()
1387 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, ®32); in do_pcie_gen3_transition()
1394 dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32); in do_pcie_gen3_transition()
1399 if ((status & (1 << dd->hfi1_id)) == 0) { in do_pcie_gen3_transition()
1402 __func__, status, 1 << dd->hfi1_id); in do_pcie_gen3_transition()
1403 ret = -EIO; in do_pcie_gen3_transition()
1412 ret = -EIO; in do_pcie_gen3_transition()
1419 dd->lbus_info); in do_pcie_gen3_transition()
1421 if (dd->lbus_speed != target_speed || in do_pcie_gen3_transition()
1422 dd->lbus_width < target_width) { /* not target */ in do_pcie_gen3_transition()
1432 ret = -EIO; in do_pcie_gen3_transition()
1439 dd_dev_info(dd, "%s: Re-enable therm polling\n", in do_pcie_gen3_transition()