88 	writel(mmio_read_reg, edev->reg_bar + EFA_REGS_MMIO_REG_READ_OFF);  in efa_com_reg_read32()
141 	sq->db_addr = (u32 __iomem *)(edev->reg_bar + EFA_REGS_AQ_PROD_DB_OFF);  in efa_com_admin_init_sq()
146 	writel(addr_low, edev->reg_bar + EFA_REGS_AQ_BASE_LO_OFF);  in efa_com_admin_init_sq()
147 	writel(addr_high, edev->reg_bar + EFA_REGS_AQ_BASE_HI_OFF);  in efa_com_admin_init_sq()
153 	writel(aq_caps, edev->reg_bar + EFA_REGS_AQ_CAPS_OFF);  in efa_com_admin_init_sq()
180 	writel(addr_low, edev->reg_bar + EFA_REGS_ACQ_BASE_LO_OFF);  in efa_com_admin_init_cq()
181 	writel(addr_high, edev->reg_bar + EFA_REGS_ACQ_BASE_HI_OFF);  in efa_com_admin_init_cq()
189 	writel(acq_caps, edev->reg_bar + EFA_REGS_ACQ_CAPS_OFF);  in efa_com_admin_init_cq()
221 	writel(addr_low, edev->reg_bar + EFA_REGS_AENQ_BASE_LO_OFF);  in efa_com_admin_init_aenq()
222 	writel(addr_high, edev->reg_bar + EFA_REGS_AENQ_BASE_HI_OFF);  in efa_com_admin_init_aenq()
229 	writel(aenq_caps, edev->reg_bar + EFA_REGS_AENQ_CAPS_OFF);  in efa_com_admin_init_aenq()
235 	writel(edev->aenq.cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF);  in efa_com_admin_init_aenq()
695 	writel(mask_value, edev->reg_bar + EFA_REGS_INTR_MASK_OFF);  in efa_com_set_admin_polling_mode()
880 	writel(aenq->cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF);  in efa_com_aenq_intr_handler()
893 	writel(addr_high, edev->reg_bar + EFA_REGS_MMIO_RESP_HI_OFF);  in efa_com_mmio_reg_read_resp_addr_init()
894 	writel(addr_low, edev->reg_bar + EFA_REGS_MMIO_RESP_LO_OFF);  in efa_com_mmio_reg_read_resp_addr_init()
1063 	writel(reset_val, edev->reg_bar + EFA_REGS_DEV_CTL_OFF);  in efa_com_dev_reset()
1075 	writel(0, edev->reg_bar + EFA_REGS_DEV_CTL_OFF);  in efa_com_dev_reset()