Lines Matching +full:5 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
67 /* ODR suffixed by LN or LP are Low-Noise or Low-Power mode only */
86 /* Low-Noise mode sensor data filter (3rd order filter by default) */
89 /* Low-Power mode sensor data filter (averaging) */
100 #define INV_ICM42600_SENSOR_CONF_INIT {-1, -1, -1, -1}
115 * struct inv_icm42600_state - driver state variables
159 #define INV_ICM42600_DEVICE_CONFIG_SOFT_RESET BIT(0)
162 #define INV_ICM42600_DRIVE_CONFIG_I2C_MASK GENMASK(5, 3)
170 #define INV_ICM42600_INT_CONFIG_INT2_LATCHED BIT(5)
171 #define INV_ICM42600_INT_CONFIG_INT2_PUSH_PULL BIT(4)
172 #define INV_ICM42600_INT_CONFIG_INT2_ACTIVE_HIGH BIT(3)
174 #define INV_ICM42600_INT_CONFIG_INT1_LATCHED BIT(2)
175 #define INV_ICM42600_INT_CONFIG_INT1_PUSH_PULL BIT(1)
176 #define INV_ICM42600_INT_CONFIG_INT1_ACTIVE_HIGH BIT(0)
188 /* all sensor data are 16 bits (2 registers wide) in big-endian */
196 #define INV_ICM42600_DATA_INVALID -32768
199 #define INV_ICM42600_INT_STATUS_UI_FSYNC BIT(6)
200 #define INV_ICM42600_INT_STATUS_PLL_RDY BIT(5)
201 #define INV_ICM42600_INT_STATUS_RESET_DONE BIT(4)
202 #define INV_ICM42600_INT_STATUS_DATA_RDY BIT(3)
203 #define INV_ICM42600_INT_STATUS_FIFO_THS BIT(2)
204 #define INV_ICM42600_INT_STATUS_FIFO_FULL BIT(1)
205 #define INV_ICM42600_INT_STATUS_AGC_RDY BIT(0)
209 * FIFO count is 16 bits (2 registers) big-endian
216 #define INV_ICM42600_SIGNAL_PATH_RESET_DMP_INIT_EN BIT(6)
217 #define INV_ICM42600_SIGNAL_PATH_RESET_DMP_MEM_RESET BIT(5)
218 #define INV_ICM42600_SIGNAL_PATH_RESET_RESET BIT(3)
219 #define INV_ICM42600_SIGNAL_PATH_RESET_TMST_STROBE BIT(2)
220 #define INV_ICM42600_SIGNAL_PATH_RESET_FIFO_FLUSH BIT(1)
222 /* default configuration: all data big-endian and fifo count in bytes */
224 #define INV_ICM42600_INTF_CONFIG0_FIFO_HOLD_LAST_DATA BIT(7)
225 #define INV_ICM42600_INTF_CONFIG0_FIFO_COUNT_REC BIT(6)
226 #define INV_ICM42600_INTF_CONFIG0_FIFO_COUNT_ENDIAN BIT(5)
227 #define INV_ICM42600_INTF_CONFIG0_SENSOR_DATA_ENDIAN BIT(4)
235 #define INV_ICM42600_INTF_CONFIG1_ACCEL_LP_CLK_RC BIT(3)
238 #define INV_ICM42600_PWR_MGMT0_TEMP_DIS BIT(5)
239 #define INV_ICM42600_PWR_MGMT0_IDLE BIT(4)
247 FIELD_PREP(GENMASK(7, 5), (_fs))
253 FIELD_PREP(GENMASK(7, 5), (_fs))
265 #define INV_ICM42600_TMST_CONFIG_TMST_TO_REGS_EN BIT(4)
266 #define INV_ICM42600_TMST_CONFIG_TMST_RES_16US BIT(3)
267 #define INV_ICM42600_TMST_CONFIG_TMST_DELTA_EN BIT(2)
268 #define INV_ICM42600_TMST_CONFIG_TMST_FSYNC_EN BIT(1)
269 #define INV_ICM42600_TMST_CONFIG_TMST_EN BIT(0)
272 #define INV_ICM42600_FIFO_CONFIG1_RESUME_PARTIAL_RD BIT(6)
273 #define INV_ICM42600_FIFO_CONFIG1_WM_GT_TH BIT(5)
274 #define INV_ICM42600_FIFO_CONFIG1_TMST_FSYNC_EN BIT(3)
275 #define INV_ICM42600_FIFO_CONFIG1_TEMP_EN BIT(2)
276 #define INV_ICM42600_FIFO_CONFIG1_GYRO_EN BIT(1)
277 #define INV_ICM42600_FIFO_CONFIG1_ACCEL_EN BIT(0)
279 /* FIFO watermark is 16 bits (2 registers wide) in little-endian */
284 #define INV_ICM42600_FIFO_WATERMARK_MAX (2048 - 12 * 16)
287 #define INV_ICM42600_INT_CONFIG1_TPULSE_DURATION BIT(6)
288 #define INV_ICM42600_INT_CONFIG1_TDEASSERT_DISABLE BIT(5)
289 #define INV_ICM42600_INT_CONFIG1_ASYNC_RESET BIT(4)
292 #define INV_ICM42600_INT_SOURCE0_UI_FSYNC_INT1_EN BIT(6)
293 #define INV_ICM42600_INT_SOURCE0_PLL_RDY_INT1_EN BIT(5)
294 #define INV_ICM42600_INT_SOURCE0_RESET_DONE_INT1_EN BIT(4)
295 #define INV_ICM42600_INT_SOURCE0_UI_DRDY_INT1_EN BIT(3)
296 #define INV_ICM42600_INT_SOURCE0_FIFO_THS_INT1_EN BIT(2)
297 #define INV_ICM42600_INT_SOURCE0_FIFO_FULL_INT1_EN BIT(1)
298 #define INV_ICM42600_INT_SOURCE0_UI_AGC_RDY_INT1_EN BIT(0)
308 #define INV_ICM42600_SENSOR_CONFIG0_ZG_DISABLE BIT(5)
309 #define INV_ICM42600_SENSOR_CONFIG0_YG_DISABLE BIT(4)
310 #define INV_ICM42600_SENSOR_CONFIG0_XG_DISABLE BIT(3)
311 #define INV_ICM42600_SENSOR_CONFIG0_ZA_DISABLE BIT(2)
312 #define INV_ICM42600_SENSOR_CONFIG0_YA_DISABLE BIT(1)
313 #define INV_ICM42600_SENSOR_CONFIG0_XA_DISABLE BIT(0)
315 /* Timestamp value is 20 bits (3 registers) in little-endian */
320 #define INV_ICM42600_INTF_CONFIG4_I3C_BUS_ONLY BIT(6)
321 #define INV_ICM42600_INTF_CONFIG4_SPI_AP_4WIRE BIT(1)
325 #define INV_ICM42600_INTF_CONFIG6_I3C_EN BIT(4)
326 #define INV_ICM42600_INTF_CONFIG6_I3C_IBI_BYTE_EN BIT(3)
327 #define INV_ICM42600_INTF_CONFIG6_I3C_IBI_EN BIT(2)
328 #define INV_ICM42600_INTF_CONFIG6_I3C_DDR_EN BIT(1)
329 #define INV_ICM42600_INTF_CONFIG6_I3C_SDR_EN BIT(0)
333 #define INV_ICM42600_INT_SOURCE8_FSYNC_IBI_EN BIT(5)
334 #define INV_ICM42600_INT_SOURCE8_PLL_RDY_IBI_EN BIT(4)
335 #define INV_ICM42600_INT_SOURCE8_UI_DRDY_IBI_EN BIT(3)
336 #define INV_ICM42600_INT_SOURCE8_FIFO_THS_IBI_EN BIT(2)
337 #define INV_ICM42600_INT_SOURCE8_FIFO_FULL_IBI_EN BIT(1)
338 #define INV_ICM42600_INT_SOURCE8_AGC_RDY_IBI_EN BIT(0)