115 static void xadc_write_reg(struct xadc *xadc, unsigned int reg,  in xadc_write_reg()  argument
118 	writel(val, xadc->base + reg);  in xadc_write_reg()
121 static void xadc_read_reg(struct xadc *xadc, unsigned int reg,  in xadc_read_reg()  argument
124 	*val = readl(xadc->base + reg);  in xadc_read_reg()
137 static void xadc_zynq_write_fifo(struct xadc *xadc, uint32_t *cmd,  in xadc_zynq_write_fifo()  argument
143 		xadc_write_reg(xadc, XADC_ZYNQ_REG_CFIFO, cmd[i]);  in xadc_zynq_write_fifo()
146 static void xadc_zynq_drain_fifo(struct xadc *xadc)  in xadc_zynq_drain_fifo()  argument
150 	xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);  in xadc_zynq_drain_fifo()
153 		xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);  in xadc_zynq_drain_fifo()
154 		xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);  in xadc_zynq_drain_fifo()
158 static void xadc_zynq_update_intmsk(struct xadc *xadc, unsigned int mask,  in xadc_zynq_update_intmsk()  argument
161 	xadc->zynq_intmask &= ~mask;  in xadc_zynq_update_intmsk()
162 	xadc->zynq_intmask |= val;  in xadc_zynq_update_intmsk()
164 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK,  in xadc_zynq_update_intmsk()
165 		xadc->zynq_intmask | xadc->zynq_masked_alarm);  in xadc_zynq_update_intmsk()
168 static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg,  in xadc_zynq_write_adc_reg()  argument
175 	spin_lock_irq(&xadc->lock);  in xadc_zynq_write_adc_reg()
176 	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,  in xadc_zynq_write_adc_reg()
179 	reinit_completion(&xadc->completion);  in xadc_zynq_write_adc_reg()
182 	xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));  in xadc_zynq_write_adc_reg()
183 	xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);  in xadc_zynq_write_adc_reg()
186 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);  in xadc_zynq_write_adc_reg()
188 	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);  in xadc_zynq_write_adc_reg()
189 	spin_unlock_irq(&xadc->lock);  in xadc_zynq_write_adc_reg()
191 	ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);  in xadc_zynq_write_adc_reg()
197 	xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);  in xadc_zynq_write_adc_reg()
202 static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg,  in xadc_zynq_read_adc_reg()  argument
212 	spin_lock_irq(&xadc->lock);  in xadc_zynq_read_adc_reg()
213 	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,  in xadc_zynq_read_adc_reg()
215 	xadc_zynq_drain_fifo(xadc);  in xadc_zynq_read_adc_reg()
216 	reinit_completion(&xadc->completion);  in xadc_zynq_read_adc_reg()
218 	xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));  in xadc_zynq_read_adc_reg()
219 	xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);  in xadc_zynq_read_adc_reg()
222 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);  in xadc_zynq_read_adc_reg()
224 	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);  in xadc_zynq_read_adc_reg()
225 	spin_unlock_irq(&xadc->lock);  in xadc_zynq_read_adc_reg()
226 	ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);  in xadc_zynq_read_adc_reg()
232 	xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);  in xadc_zynq_read_adc_reg()
233 	xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);  in xadc_zynq_read_adc_reg()
257 	struct xadc *xadc = container_of(work, struct xadc, zynq_unmask_work.work);  in xadc_zynq_unmask_worker()  local
260 	xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &misc_sts);  in xadc_zynq_unmask_worker()
264 	spin_lock_irq(&xadc->lock);  in xadc_zynq_unmask_worker()
267 	unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm;  in xadc_zynq_unmask_worker()
268 	xadc->zynq_masked_alarm &= misc_sts;  in xadc_zynq_unmask_worker()
271 	xadc->zynq_masked_alarm &= ~xadc->zynq_intmask;  in xadc_zynq_unmask_worker()
274 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, unmask);  in xadc_zynq_unmask_worker()
276 	xadc_zynq_update_intmsk(xadc, 0, 0);  in xadc_zynq_unmask_worker()
278 	spin_unlock_irq(&xadc->lock);  in xadc_zynq_unmask_worker()
281 	if (xadc->zynq_masked_alarm) {  in xadc_zynq_unmask_worker()
282 		schedule_delayed_work(&xadc->zynq_unmask_work,  in xadc_zynq_unmask_worker()
291 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_zynq_interrupt_handler()  local
294 	xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);  in xadc_zynq_interrupt_handler()
296 	status &= ~(xadc->zynq_intmask | xadc->zynq_masked_alarm);  in xadc_zynq_interrupt_handler()
301 	spin_lock(&xadc->lock);  in xadc_zynq_interrupt_handler()
303 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status);  in xadc_zynq_interrupt_handler()
306 		xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,  in xadc_zynq_interrupt_handler()
308 		complete(&xadc->completion);  in xadc_zynq_interrupt_handler()
313 		xadc->zynq_masked_alarm |= status;  in xadc_zynq_interrupt_handler()
318 		xadc_zynq_update_intmsk(xadc, 0, 0);  in xadc_zynq_interrupt_handler()
324 		schedule_delayed_work(&xadc->zynq_unmask_work,  in xadc_zynq_interrupt_handler()
327 	spin_unlock(&xadc->lock);  in xadc_zynq_interrupt_handler()
339 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_zynq_setup()  local
351 	xadc->zynq_intmask = ~0;  in xadc_zynq_setup()
353 	pcap_rate = clk_get_rate(xadc->clk);  in xadc_zynq_setup()
358 		ret = clk_set_rate(xadc->clk,  in xadc_zynq_setup()
381 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, XADC_ZYNQ_CTL_RESET);  in xadc_zynq_setup()
382 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, 0);  in xadc_zynq_setup()
383 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0);  in xadc_zynq_setup()
384 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask);  in xadc_zynq_setup()
385 	xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE |  in xadc_zynq_setup()
390 		ret = clk_set_rate(xadc->clk, pcap_rate);  in xadc_zynq_setup()
398 static unsigned long xadc_zynq_get_dclk_rate(struct xadc *xadc)  in xadc_zynq_get_dclk_rate()  argument
403 	xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &val);  in xadc_zynq_get_dclk_rate()
420 	return clk_get_rate(xadc->clk) / div;  in xadc_zynq_get_dclk_rate()
423 static void xadc_zynq_update_alarm(struct xadc *xadc, unsigned int alarm)  in xadc_zynq_update_alarm()  argument
431 	spin_lock_irqsave(&xadc->lock, flags);  in xadc_zynq_update_alarm()
434 	xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);  in xadc_zynq_update_alarm()
435 	xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status & alarm);  in xadc_zynq_update_alarm()
437 	xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_ALARM_MASK,  in xadc_zynq_update_alarm()
440 	spin_unlock_irqrestore(&xadc->lock, flags);  in xadc_zynq_update_alarm()
452 static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg,  in xadc_axi_read_adc_reg()  argument
457 	xadc_read_reg(xadc, XADC_AXI_ADC_REG_OFFSET + reg * 4, &val32);  in xadc_axi_read_adc_reg()
463 static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg,  in xadc_axi_write_adc_reg()  argument
466 	xadc_write_reg(xadc, XADC_AXI_ADC_REG_OFFSET + reg * 4, val);  in xadc_axi_write_adc_reg()
474 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_axi_setup()  local
476 	xadc_write_reg(xadc, XADC_AXI_REG_RESET, XADC_AXI_RESET_MAGIC);  in xadc_axi_setup()
477 	xadc_write_reg(xadc, XADC_AXI_REG_GIER, XADC_AXI_GIER_ENABLE);  in xadc_axi_setup()
485 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_axi_interrupt_handler()  local
489 	xadc_read_reg(xadc, XADC_AXI_REG_IPISR, &status);  in xadc_axi_interrupt_handler()
490 	xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &mask);  in xadc_axi_interrupt_handler()
496 	if ((status & XADC_AXI_INT_EOS) && xadc->trigger)  in xadc_axi_interrupt_handler()
497 		iio_trigger_poll(xadc->trigger);  in xadc_axi_interrupt_handler()
512 	xadc_write_reg(xadc, XADC_AXI_REG_IPISR, status);  in xadc_axi_interrupt_handler()
517 static void xadc_axi_update_alarm(struct xadc *xadc, unsigned int alarm)  in xadc_axi_update_alarm()  argument
531 	spin_lock_irqsave(&xadc->lock, flags);  in xadc_axi_update_alarm()
532 	xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);  in xadc_axi_update_alarm()
535 	xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);  in xadc_axi_update_alarm()
536 	spin_unlock_irqrestore(&xadc->lock, flags);  in xadc_axi_update_alarm()
539 static unsigned long xadc_axi_get_dclk(struct xadc *xadc)  in xadc_axi_get_dclk()  argument
541 	return clk_get_rate(xadc->clk);  in xadc_axi_get_dclk()
554 static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,  in _xadc_update_adc_reg()  argument
560 	ret = _xadc_read_adc_reg(xadc, reg, &tmp);  in _xadc_update_adc_reg()
564 	return _xadc_write_adc_reg(xadc, reg, (tmp & ~mask) | val);  in _xadc_update_adc_reg()
567 static int xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,  in xadc_update_adc_reg()  argument
572 	mutex_lock(&xadc->mutex);  in xadc_update_adc_reg()
573 	ret = _xadc_update_adc_reg(xadc, reg, mask, val);  in xadc_update_adc_reg()
574 	mutex_unlock(&xadc->mutex);  in xadc_update_adc_reg()
579 static unsigned long xadc_get_dclk_rate(struct xadc *xadc)  in xadc_get_dclk_rate()  argument
581 	return xadc->ops->get_dclk_rate(xadc);  in xadc_get_dclk_rate()
587 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_update_scan_mode()  local
592 	kfree(xadc->data);  in xadc_update_scan_mode()
593 	xadc->data = kcalloc(n, sizeof(*xadc->data), GFP_KERNEL);  in xadc_update_scan_mode()
594 	if (!xadc->data)  in xadc_update_scan_mode()
632 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_trigger_handler()  local
636 	if (!xadc->data)  in xadc_trigger_handler()
643 		xadc_read_adc_reg(xadc, chan, &xadc->data[j]);  in xadc_trigger_handler()
647 	iio_push_to_buffers(indio_dev, xadc->data);  in xadc_trigger_handler()
657 	struct xadc *xadc = iio_trigger_get_drvdata(trigger);  in xadc_trigger_set_state()  local
663 	mutex_lock(&xadc->mutex);  in xadc_trigger_set_state()
667 		if (xadc->trigger != NULL) {  in xadc_trigger_set_state()
671 			xadc->trigger = trigger;  in xadc_trigger_set_state()
672 			if (trigger == xadc->convst_trigger)  in xadc_trigger_set_state()
677 		ret = _xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF0_EC,  in xadc_trigger_set_state()
682 		xadc->trigger = NULL;  in xadc_trigger_set_state()
685 	spin_lock_irqsave(&xadc->lock, flags);  in xadc_trigger_set_state()
686 	xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);  in xadc_trigger_set_state()
687 	xadc_write_reg(xadc, XADC_AXI_REG_IPISR, XADC_AXI_INT_EOS);  in xadc_trigger_set_state()
692 	xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);  in xadc_trigger_set_state()
693 	spin_unlock_irqrestore(&xadc->lock, flags);  in xadc_trigger_set_state()
696 	mutex_unlock(&xadc->mutex);  in xadc_trigger_set_state()
731 static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode)  in xadc_power_adc_b()  argument
746 	return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_PD_MASK,  in xadc_power_adc_b()
750 static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode)  in xadc_get_seq_mode()  argument
754 	if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_DUAL)  in xadc_get_seq_mode()
766 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_postdisable()  local
776 	ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);  in xadc_postdisable()
780 	ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);  in xadc_postdisable()
784 	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,  in xadc_postdisable()
789 	return xadc_power_adc_b(xadc, XADC_CONF1_SEQ_CONTINUOUS);  in xadc_postdisable()
794 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_preenable()  local
799 	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,  in xadc_preenable()
805 	seq_mode = xadc_get_seq_mode(xadc, scan_mask);  in xadc_preenable()
807 	ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);  in xadc_preenable()
821 	ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);  in xadc_preenable()
825 	ret = xadc_power_adc_b(xadc, seq_mode);  in xadc_preenable()
829 	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,  in xadc_preenable()
845 static int xadc_read_samplerate(struct xadc *xadc)  in xadc_read_samplerate()  argument
851 	ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16);  in xadc_read_samplerate()
859 	return xadc_get_dclk_rate(xadc) / div / 26;  in xadc_read_samplerate()
865 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_read_raw()  local
873 		ret = xadc_read_adc_reg(xadc, chan->address, &val16);  in xadc_read_raw()
918 		ret = xadc_read_samplerate(xadc);  in xadc_read_raw()
929 static int xadc_write_samplerate(struct xadc *xadc, int val)  in xadc_write_samplerate()  argument
931 	unsigned long clk_rate = xadc_get_dclk_rate(xadc);  in xadc_write_samplerate()
962 	return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_DIV_MASK,  in xadc_write_samplerate()
969 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_write_raw()  local
974 	return xadc_write_samplerate(xadc, val);  in xadc_write_raw()
1096 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_parse_dt()  local
1109 		xadc->external_mux_mode = XADC_EXTERNAL_MUX_NONE;  in xadc_parse_dt()
1111 		xadc->external_mux_mode = XADC_EXTERNAL_MUX_SINGLE;  in xadc_parse_dt()
1113 		xadc->external_mux_mode = XADC_EXTERNAL_MUX_DUAL;  in xadc_parse_dt()
1117 	if (xadc->external_mux_mode != XADC_EXTERNAL_MUX_NONE) {  in xadc_parse_dt()
1123 		if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_SINGLE) {  in xadc_parse_dt()
1193 	struct xadc *xadc;  in xadc_probe()  local
1209 	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*xadc));  in xadc_probe()
1213 	xadc = iio_priv(indio_dev);  in xadc_probe()
1214 	xadc->ops = id->data;  in xadc_probe()
1215 	xadc->irq = irq;  in xadc_probe()
1216 	init_completion(&xadc->completion);  in xadc_probe()
1217 	mutex_init(&xadc->mutex);  in xadc_probe()
1218 	spin_lock_init(&xadc->lock);  in xadc_probe()
1219 	INIT_DELAYED_WORK(&xadc->zynq_unmask_work, xadc_zynq_unmask_worker);  in xadc_probe()
1221 	xadc->base = devm_platform_ioremap_resource(pdev, 0);  in xadc_probe()
1222 	if (IS_ERR(xadc->base))  in xadc_probe()
1223 		return PTR_ERR(xadc->base);  in xadc_probe()
1233 	if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {  in xadc_probe()
1240 		xadc->convst_trigger = xadc_alloc_trigger(indio_dev, "convst");  in xadc_probe()
1241 		if (IS_ERR(xadc->convst_trigger)) {  in xadc_probe()
1242 			ret = PTR_ERR(xadc->convst_trigger);  in xadc_probe()
1245 		xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev,  in xadc_probe()
1247 		if (IS_ERR(xadc->samplerate_trigger)) {  in xadc_probe()
1248 			ret = PTR_ERR(xadc->samplerate_trigger);  in xadc_probe()
1253 	xadc->clk = devm_clk_get(&pdev->dev, NULL);  in xadc_probe()
1254 	if (IS_ERR(xadc->clk)) {  in xadc_probe()
1255 		ret = PTR_ERR(xadc->clk);  in xadc_probe()
1259 	ret = clk_prepare_enable(xadc->clk);  in xadc_probe()
1267 	if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {  in xadc_probe()
1268 		ret = xadc_read_samplerate(xadc);  in xadc_probe()
1272 			ret = xadc_write_samplerate(xadc, XADC_MAX_SAMPLERATE);  in xadc_probe()
1278 	ret = request_irq(xadc->irq, xadc->ops->interrupt_handler, 0,  in xadc_probe()
1283 	ret = xadc->ops->setup(pdev, indio_dev, xadc->irq);  in xadc_probe()
1288 		xadc_read_adc_reg(xadc, XADC_REG_THRESHOLD(i),  in xadc_probe()
1289 			&xadc->threshold[i]);  in xadc_probe()
1291 	ret = xadc_write_adc_reg(xadc, XADC_REG_CONF0, conf0);  in xadc_probe()
1301 	ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(0), bipolar_mask);  in xadc_probe()
1304 	ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(1),  in xadc_probe()
1310 	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_ALARM_MASK,  in xadc_probe()
1322 			xadc->threshold[i] = 0xffff;  in xadc_probe()
1324 			xadc->threshold[i] = 0;  in xadc_probe()
1325 		ret = xadc_write_adc_reg(xadc, XADC_REG_THRESHOLD(i),  in xadc_probe()
1326 			xadc->threshold[i]);  in xadc_probe()
1343 	free_irq(xadc->irq, indio_dev);  in xadc_probe()
1344 	cancel_delayed_work_sync(&xadc->zynq_unmask_work);  in xadc_probe()
1346 	clk_disable_unprepare(xadc->clk);  in xadc_probe()
1348 	if (xadc->ops->flags & XADC_FLAGS_BUFFERED)  in xadc_probe()
1349 		iio_trigger_free(xadc->samplerate_trigger);  in xadc_probe()
1351 	if (xadc->ops->flags & XADC_FLAGS_BUFFERED)  in xadc_probe()
1352 		iio_trigger_free(xadc->convst_trigger);  in xadc_probe()
1354 	if (xadc->ops->flags & XADC_FLAGS_BUFFERED)  in xadc_probe()
1363 	struct xadc *xadc = iio_priv(indio_dev);  in xadc_remove()  local
1366 	if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {  in xadc_remove()
1367 		iio_trigger_free(xadc->samplerate_trigger);  in xadc_remove()
1368 		iio_trigger_free(xadc->convst_trigger);  in xadc_remove()
1371 	free_irq(xadc->irq, indio_dev);  in xadc_remove()
1372 	cancel_delayed_work_sync(&xadc->zynq_unmask_work);  in xadc_remove()
1373 	clk_disable_unprepare(xadc->clk);  in xadc_remove()
1374 	kfree(xadc->data);  in xadc_remove()