Lines Matching +full:adc +full:- +full:chan
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/nvmem-consumer.h>
21 /* ADC controller registers definition */
57 /* Timeout (us) for ADC data conversion according to ADC datasheet */
61 /* Maximum ADC channel number */
64 /* ADC voltage ratio definition */
75 * subsystems which will access the unique ADC controller.
91 * According to the datasheet, we can convert one ADC value to one voltage value
93 * should use the small-scale graph, and if more than 1.2v, we should use the
94 * big-scale graph.
118 return ((calib_data & 0xff) + calib_adc - 128) * 4; in sc27xx_adc_get_calib_data()
142 cell = nvmem_cell_get(data->dev, cell_name); in sc27xx_adc_scale_calibration()
154 /* Only need to calibrate the adc values in the linear graph. */ in sc27xx_adc_scale_calibration()
155 graph->adc0 = sc27xx_adc_get_calib_data(calib_data, calib_graph->adc0); in sc27xx_adc_scale_calibration()
156 graph->adc1 = sc27xx_adc_get_calib_data(calib_data >> 8, in sc27xx_adc_scale_calibration()
157 calib_graph->adc1); in sc27xx_adc_scale_calibration()
194 ret = hwspin_lock_timeout_raw(data->hwlock, SC27XX_ADC_HWLOCK_TIMEOUT); in sc27xx_adc_read()
196 dev_err(data->dev, "timeout to get the hwspinlock\n"); in sc27xx_adc_read()
200 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, in sc27xx_adc_read()
205 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_CLR, in sc27xx_adc_read()
213 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CH_CFG, in sc27xx_adc_read()
222 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, in sc27xx_adc_read()
228 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, in sc27xx_adc_read()
233 ret = regmap_read_poll_timeout(data->regmap, in sc27xx_adc_read()
234 data->base + SC27XX_ADC_INT_RAW, in sc27xx_adc_read()
239 dev_err(data->dev, "read adc timeout, status = 0x%x\n", status); in sc27xx_adc_read()
243 ret = regmap_read(data->regmap, data->base + SC27XX_ADC_DATA, &value); in sc27xx_adc_read()
250 regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, in sc27xx_adc_read()
253 hwspin_unlock_raw(data->hwlock); in sc27xx_adc_read()
276 tmp = (graph->volt0 - graph->volt1) * (raw_adc - graph->adc1); in sc27xx_adc_to_volt()
277 tmp /= (graph->adc0 - graph->adc1); in sc27xx_adc_to_volt()
278 tmp += graph->volt1; in sc27xx_adc_to_volt()
290 * Convert ADC values to voltage values according to the linear graph, in sc27xx_adc_convert_volt()
327 struct iio_chan_spec const *chan, in sc27xx_adc_read_raw() argument
331 int scale = data->channel_scale[chan->channel]; in sc27xx_adc_read_raw()
336 mutex_lock(&indio_dev->mlock); in sc27xx_adc_read_raw()
337 ret = sc27xx_adc_read(data, chan->channel, scale, &tmp); in sc27xx_adc_read_raw()
338 mutex_unlock(&indio_dev->mlock); in sc27xx_adc_read_raw()
347 mutex_lock(&indio_dev->mlock); in sc27xx_adc_read_raw()
348 ret = sc27xx_adc_read_processed(data, chan->channel, scale, in sc27xx_adc_read_raw()
350 mutex_unlock(&indio_dev->mlock); in sc27xx_adc_read_raw()
363 return -EINVAL; in sc27xx_adc_read_raw()
368 struct iio_chan_spec const *chan, in sc27xx_adc_write_raw() argument
375 data->channel_scale[chan->channel] = val; in sc27xx_adc_write_raw()
379 return -EINVAL; in sc27xx_adc_write_raw()
435 ret = regmap_update_bits(data->regmap, SC27XX_MODULE_EN, in sc27xx_adc_enable()
440 /* Enable ADC work clock and controller clock */ in sc27xx_adc_enable()
441 ret = regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN, in sc27xx_adc_enable()
447 /* ADC channel scales' calibration from nvmem device */ in sc27xx_adc_enable()
459 regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN, in sc27xx_adc_enable()
462 regmap_update_bits(data->regmap, SC27XX_MODULE_EN, in sc27xx_adc_enable()
472 /* Disable ADC work clock and controller clock */ in sc27xx_adc_disable()
473 regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN, in sc27xx_adc_disable()
476 regmap_update_bits(data->regmap, SC27XX_MODULE_EN, in sc27xx_adc_disable()
482 struct device *dev = &pdev->dev; in sc27xx_adc_probe()
483 struct device_node *np = dev->of_node; in sc27xx_adc_probe()
490 return -ENOMEM; in sc27xx_adc_probe()
494 sc27xx_data->regmap = dev_get_regmap(dev->parent, NULL); in sc27xx_adc_probe()
495 if (!sc27xx_data->regmap) { in sc27xx_adc_probe()
496 dev_err(dev, "failed to get ADC regmap\n"); in sc27xx_adc_probe()
497 return -ENODEV; in sc27xx_adc_probe()
500 ret = of_property_read_u32(np, "reg", &sc27xx_data->base); in sc27xx_adc_probe()
502 dev_err(dev, "failed to get ADC base address\n"); in sc27xx_adc_probe()
506 sc27xx_data->irq = platform_get_irq(pdev, 0); in sc27xx_adc_probe()
507 if (sc27xx_data->irq < 0) in sc27xx_adc_probe()
508 return sc27xx_data->irq; in sc27xx_adc_probe()
516 sc27xx_data->hwlock = devm_hwspin_lock_request_specific(dev, ret); in sc27xx_adc_probe()
517 if (!sc27xx_data->hwlock) { in sc27xx_adc_probe()
519 return -ENXIO; in sc27xx_adc_probe()
522 sc27xx_data->dev = dev; in sc27xx_adc_probe()
526 dev_err(dev, "failed to enable ADC module\n"); in sc27xx_adc_probe()
532 dev_err(dev, "failed to add ADC disable action\n"); in sc27xx_adc_probe()
536 indio_dev->name = dev_name(dev); in sc27xx_adc_probe()
537 indio_dev->modes = INDIO_DIRECT_MODE; in sc27xx_adc_probe()
538 indio_dev->info = &sc27xx_info; in sc27xx_adc_probe()
539 indio_dev->channels = sc27xx_channels; in sc27xx_adc_probe()
540 indio_dev->num_channels = ARRAY_SIZE(sc27xx_channels); in sc27xx_adc_probe()
543 dev_err(dev, "could not register iio (ADC)"); in sc27xx_adc_probe()
549 { .compatible = "sprd,sc2731-adc", },
556 .name = "sc27xx-adc",
564 MODULE_DESCRIPTION("Spreadtrum SC27XX ADC Driver");