Lines Matching full:fclk
266 unsigned int fclk, odr_sel_bits; in ad7124_set_channel_odr() local
269 fclk = clk_get_rate(st->mclk); in ad7124_set_channel_odr()
271 * FS[10:0] = fCLK / (fADC x 32) where: in ad7124_set_channel_odr()
273 * fCLK is the master clock frequency in ad7124_set_channel_odr()
277 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32); in ad7124_set_channel_odr()
288 /* fADC = fCLK / (FS[10:0] x 32) */ in ad7124_set_channel_odr()
290 DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32); in ad7124_set_channel_odr()
656 unsigned int val, fclk, power_mode; in ad7124_setup() local
659 fclk = clk_get_rate(st->mclk); in ad7124_setup()
660 if (!fclk) in ad7124_setup()
666 fclk); in ad7124_setup()
667 if (fclk != ad7124_master_clk_freq_hz[power_mode]) { in ad7124_setup()
668 ret = clk_set_rate(st->mclk, fclk); in ad7124_setup()