Lines Matching +full:i2c +full:- +full:fast +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/i2c/busses/i2c-tegra.c
13 #include <linux/dma-mapping.h>
15 #include <linux/i2c.h>
50 #define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5)
51 #define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2)
129 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4)
130 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16)
143 * I2C Controller will use PIO mode for transfers up to 32 bytes in order to
153 * @MSG_END_REPEAT_START: Send repeat-start.
154 * @MSG_END_CONTINUE: Don't send stop or repeat-start.
164 * @has_continue_xfer_support: continue-transfer supported
169 * @clk_divisor_hs_mode: Clock divisor in HS mode.
170 * @clk_divisor_std_mode: Clock divisor in standard mode. It is
171 * applicable if there is no fast clock source i.e. single clock
173 * @clk_divisor_fast_mode: Clock divisor in fast mode. It is
174 * applicable if there is no fast clock source i.e. single clock
176 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is
177 * applicable if there is no fast clock source (i.e. single
179 * @has_multi_master_mode: The I2C controller supports running in single-master
180 * or multi-master mode.
181 * @has_slcg_override_reg: The I2C controller supports a register that
183 * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that
186 * @quirks: I2C adapter quirks for limiting write/read transfer size and not
191 * @tlow_std_mode: Low period of the clock in standard mode.
192 * @thigh_std_mode: High period of the clock in standard mode.
193 * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes.
194 * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes.
196 * in standard mode.
198 * conditions in fast/fast-plus modes.
200 * in HS mode.
229 * struct tegra_i2c_dev - per device I2C context
231 * @hw: Tegra I2C HW feature
232 * @adapter: core I2C layer adapter information
233 * @div_clk: clock reference for div clock of I2C controller
234 * @clocks: array of I2C controller clocks
236 * @rst: reset control for the I2C controller
238 * @base_phys: physical base address of the I2C controller
239 * @cont_id: I2C controller ID, used for packet header
241 * @is_dvc: identifies the DVC I2C controller, has a different register layout
242 * @is_vi: identifies the VI I2C controller, has a different register layout
248 * @bus_clk_rate: current I2C bus clock rate
249 * @multimaster_mode: indicates that I2C controller is in multi-master mode
300 writel_relaxed(val, i2c_dev->base + reg); in dvc_writel()
305 return readl_relaxed(i2c_dev->base + reg); in dvc_readl()
310 * in order to talk to the I2C block inside the DVC block.
314 if (i2c_dev->is_dvc) in tegra_i2c_reg_addr()
316 else if (i2c_dev->is_vi) in tegra_i2c_reg_addr()
324 writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); in i2c_writel()
328 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); in i2c_writel()
333 return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); in i2c_readl()
339 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); in i2c_writesl()
345 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); in i2c_readsl()
368 complete(&i2c_dev->dma_complete); in tegra_i2c_dma_complete()
377 dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len); in tegra_i2c_dma_submit()
379 reinit_completion(&i2c_dev->dma_complete); in tegra_i2c_dma_submit()
381 dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; in tegra_i2c_dma_submit()
382 chan = i2c_dev->msg_read ? i2c_dev->rx_dma_chan : i2c_dev->tx_dma_chan; in tegra_i2c_dma_submit()
384 dma_desc = dmaengine_prep_slave_single(chan, i2c_dev->dma_phys, in tegra_i2c_dma_submit()
388 dev_err(i2c_dev->dev, "failed to get %s DMA descriptor\n", in tegra_i2c_dma_submit()
389 i2c_dev->msg_read ? "RX" : "TX"); in tegra_i2c_dma_submit()
390 return -EINVAL; in tegra_i2c_dma_submit()
393 dma_desc->callback = tegra_i2c_dma_complete; in tegra_i2c_dma_submit()
394 dma_desc->callback_param = i2c_dev; in tegra_i2c_dma_submit()
404 if (i2c_dev->dma_buf) { in tegra_i2c_release_dma()
405 dma_free_coherent(i2c_dev->dev, i2c_dev->dma_buf_size, in tegra_i2c_release_dma()
406 i2c_dev->dma_buf, i2c_dev->dma_phys); in tegra_i2c_release_dma()
407 i2c_dev->dma_buf = NULL; in tegra_i2c_release_dma()
410 if (i2c_dev->tx_dma_chan) { in tegra_i2c_release_dma()
411 dma_release_channel(i2c_dev->tx_dma_chan); in tegra_i2c_release_dma()
412 i2c_dev->tx_dma_chan = NULL; in tegra_i2c_release_dma()
415 if (i2c_dev->rx_dma_chan) { in tegra_i2c_release_dma()
416 dma_release_channel(i2c_dev->rx_dma_chan); in tegra_i2c_release_dma()
417 i2c_dev->rx_dma_chan = NULL; in tegra_i2c_release_dma()
428 if (!i2c_dev->hw->has_apb_dma || i2c_dev->is_vi) in tegra_i2c_init_dma()
432 dev_dbg(i2c_dev->dev, "DMA support not enabled\n"); in tegra_i2c_init_dma()
436 chan = dma_request_chan(i2c_dev->dev, "rx"); in tegra_i2c_init_dma()
442 i2c_dev->rx_dma_chan = chan; in tegra_i2c_init_dma()
444 chan = dma_request_chan(i2c_dev->dev, "tx"); in tegra_i2c_init_dma()
450 i2c_dev->tx_dma_chan = chan; in tegra_i2c_init_dma()
452 i2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len + in tegra_i2c_init_dma()
455 dma_buf = dma_alloc_coherent(i2c_dev->dev, i2c_dev->dma_buf_size, in tegra_i2c_init_dma()
458 dev_err(i2c_dev->dev, "failed to allocate DMA buffer\n"); in tegra_i2c_init_dma()
459 err = -ENOMEM; in tegra_i2c_init_dma()
463 i2c_dev->dma_buf = dma_buf; in tegra_i2c_init_dma()
464 i2c_dev->dma_phys = dma_phys; in tegra_i2c_init_dma()
470 if (err != -EPROBE_DEFER) { in tegra_i2c_init_dma()
471 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err); in tegra_i2c_init_dma()
472 dev_err(i2c_dev->dev, "falling back to PIO\n"); in tegra_i2c_init_dma()
480 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
481 * block. This block is identical to the rest of the I2C blocks, except that
482 * it only supports master mode, it has registers moved around, and it needs
483 * some extra init to get it into I2C mode. The register moves are handled
533 void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg); in tegra_i2c_poll_register()
536 if (!i2c_dev->atomic_mode) in tegra_i2c_poll_register()
549 if (i2c_dev->hw->has_mst_fifo) { in tegra_i2c_flush_fifos()
565 dev_err(i2c_dev->dev, "failed to flush FIFO\n"); in tegra_i2c_flush_fifos()
576 if (!i2c_dev->hw->has_config_load_reg) in tegra_i2c_wait_for_config_load()
584 dev_err(i2c_dev->dev, "failed to load config\n"); in tegra_i2c_wait_for_config_load()
600 * kernel boot up since voltage regulators use I2C. Hence, we will in tegra_i2c_init()
604 err = reset_control_reset(i2c_dev->rst); in tegra_i2c_init()
607 if (i2c_dev->is_dvc) in tegra_i2c_init()
613 if (i2c_dev->hw->has_multi_master_mode) in tegra_i2c_init()
619 if (i2c_dev->is_vi) in tegra_i2c_init()
622 switch (i2c_dev->bus_clk_rate) { in tegra_i2c_init()
625 tlow = i2c_dev->hw->tlow_fast_fastplus_mode; in tegra_i2c_init()
626 thigh = i2c_dev->hw->thigh_fast_fastplus_mode; in tegra_i2c_init()
627 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; in tegra_i2c_init()
629 if (i2c_dev->bus_clk_rate > I2C_MAX_FAST_MODE_FREQ) in tegra_i2c_init()
630 non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode; in tegra_i2c_init()
632 non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode; in tegra_i2c_init()
636 tlow = i2c_dev->hw->tlow_std_mode; in tegra_i2c_init()
637 thigh = i2c_dev->hw->thigh_std_mode; in tegra_i2c_init()
638 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode; in tegra_i2c_init()
639 non_hs_mode = i2c_dev->hw->clk_divisor_std_mode; in tegra_i2c_init()
645 i2c_dev->hw->clk_divisor_hs_mode) | in tegra_i2c_init()
649 if (i2c_dev->hw->has_interface_timing_reg) { in tegra_i2c_init()
656 * Configure setup and hold times only when tsu_thd is non-zero. in tegra_i2c_init()
659 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) in tegra_i2c_init()
664 err = clk_set_rate(i2c_dev->div_clk, in tegra_i2c_init()
665 i2c_dev->bus_clk_rate * clk_multiplier); in tegra_i2c_init()
667 dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err); in tegra_i2c_init()
671 if (!i2c_dev->is_dvc && !i2c_dev->is_vi) { in tegra_i2c_init()
684 if (i2c_dev->multimaster_mode && i2c_dev->hw->has_slcg_override_reg) in tegra_i2c_init()
699 * NACK interrupt is generated before the I2C controller generates in tegra_i2c_disable_packet_mode()
704 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate)); in tegra_i2c_disable_packet_mode()
715 size_t buf_remaining = i2c_dev->msg_buf_remaining; in tegra_i2c_empty_rx_fifo()
717 u8 *buf = i2c_dev->msg_buf; in tegra_i2c_empty_rx_fifo()
724 if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining))) in tegra_i2c_empty_rx_fifo()
725 return -EINVAL; in tegra_i2c_empty_rx_fifo()
727 if (i2c_dev->hw->has_mst_fifo) { in tegra_i2c_empty_rx_fifo()
743 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; in tegra_i2c_empty_rx_fifo()
744 rx_fifo_avail -= words_to_transfer; in tegra_i2c_empty_rx_fifo()
760 rx_fifo_avail--; in tegra_i2c_empty_rx_fifo()
765 return -EINVAL; in tegra_i2c_empty_rx_fifo()
767 i2c_dev->msg_buf_remaining = buf_remaining; in tegra_i2c_empty_rx_fifo()
768 i2c_dev->msg_buf = buf; in tegra_i2c_empty_rx_fifo()
775 size_t buf_remaining = i2c_dev->msg_buf_remaining; in tegra_i2c_fill_tx_fifo()
777 u8 *buf = i2c_dev->msg_buf; in tegra_i2c_fill_tx_fifo()
780 if (i2c_dev->hw->has_mst_fifo) { in tegra_i2c_fill_tx_fifo()
808 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; in tegra_i2c_fill_tx_fifo()
809 tx_fifo_avail -= words_to_transfer; in tegra_i2c_fill_tx_fifo()
811 i2c_dev->msg_buf_remaining = buf_remaining; in tegra_i2c_fill_tx_fifo()
812 i2c_dev->msg_buf = buf + words_to_transfer * BYTES_PER_FIFO_WORD; in tegra_i2c_fill_tx_fifo()
828 * in this function for non-zero words_to_transfer. in tegra_i2c_fill_tx_fifo()
833 i2c_dev->msg_buf_remaining = 0; in tegra_i2c_fill_tx_fifo()
834 i2c_dev->msg_buf = NULL; in tegra_i2c_fill_tx_fifo()
851 dev_warn(i2c_dev->dev, "IRQ status 0 %08x %08x %08x\n", in tegra_i2c_isr()
855 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; in tegra_i2c_isr()
862 i2c_dev->msg_err |= I2C_ERR_NO_ACK; in tegra_i2c_isr()
864 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; in tegra_i2c_isr()
869 * I2C transfer is terminated during the bus clear, so skip in tegra_i2c_isr()
872 if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE)) in tegra_i2c_isr()
875 if (!i2c_dev->dma_mode) { in tegra_i2c_isr()
876 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { in tegra_i2c_isr()
883 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW; in tegra_i2c_isr()
888 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { in tegra_i2c_isr()
889 if (i2c_dev->msg_buf_remaining) in tegra_i2c_isr()
898 if (i2c_dev->is_dvc) in tegra_i2c_isr()
907 * so forcing msg_buf_remaining to 0 in DMA mode. in tegra_i2c_isr()
910 if (i2c_dev->dma_mode) in tegra_i2c_isr()
911 i2c_dev->msg_buf_remaining = 0; in tegra_i2c_isr()
916 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) { in tegra_i2c_isr()
917 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; in tegra_i2c_isr()
920 complete(&i2c_dev->msg_complete); in tegra_i2c_isr()
932 if (i2c_dev->hw->supports_bus_clear) in tegra_i2c_isr()
937 if (i2c_dev->is_dvc) in tegra_i2c_isr()
940 if (i2c_dev->dma_mode) { in tegra_i2c_isr()
941 if (i2c_dev->msg_read) in tegra_i2c_isr()
942 dmaengine_terminate_async(i2c_dev->rx_dma_chan); in tegra_i2c_isr()
944 dmaengine_terminate_async(i2c_dev->tx_dma_chan); in tegra_i2c_isr()
946 complete(&i2c_dev->dma_complete); in tegra_i2c_isr()
949 complete(&i2c_dev->msg_complete); in tegra_i2c_isr()
962 if (i2c_dev->hw->has_mst_fifo) in tegra_i2c_config_fifo_trig()
967 if (i2c_dev->dma_mode) { in tegra_i2c_config_fifo_trig()
975 if (i2c_dev->msg_read) { in tegra_i2c_config_fifo_trig()
976 chan = i2c_dev->rx_dma_chan; in tegra_i2c_config_fifo_trig()
979 slv_config.src_addr = i2c_dev->base_phys + reg_offset; in tegra_i2c_config_fifo_trig()
983 if (i2c_dev->hw->has_mst_fifo) in tegra_i2c_config_fifo_trig()
988 chan = i2c_dev->tx_dma_chan; in tegra_i2c_config_fifo_trig()
991 slv_config.dst_addr = i2c_dev->base_phys + reg_offset; in tegra_i2c_config_fifo_trig()
995 if (i2c_dev->hw->has_mst_fifo) in tegra_i2c_config_fifo_trig()
1004 dev_err(i2c_dev->dev, "DMA config failed: %d\n", err); in tegra_i2c_config_fifo_trig()
1005 dev_err(i2c_dev->dev, "falling back to PIO\n"); in tegra_i2c_config_fifo_trig()
1008 i2c_dev->dma_mode = false; in tegra_i2c_config_fifo_trig()
1014 if (i2c_dev->hw->has_mst_fifo) in tegra_i2c_config_fifo_trig()
1035 tegra_i2c_isr(i2c_dev->irq, i2c_dev); in tegra_i2c_poll_completion()
1056 if (i2c_dev->atomic_mode) { in tegra_i2c_wait_completion()
1059 enable_irq(i2c_dev->irq); in tegra_i2c_wait_completion()
1062 disable_irq(i2c_dev->irq); in tegra_i2c_wait_completion()
1068 * case we will get timeout if I2C transfer is running on in tegra_i2c_wait_completion()
1087 reinit_completion(&i2c_dev->msg_complete); in tegra_i2c_issue_bus_clear()
1101 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 50); in tegra_i2c_issue_bus_clear()
1105 dev_err(i2c_dev->dev, "failed to clear bus\n"); in tegra_i2c_issue_bus_clear()
1106 return -ETIMEDOUT; in tegra_i2c_issue_bus_clear()
1111 dev_err(i2c_dev->dev, "un-recovered arbitration lost\n"); in tegra_i2c_issue_bus_clear()
1112 return -EIO; in tegra_i2c_issue_bus_clear()
1115 return -EAGAIN; in tegra_i2c_issue_bus_clear()
1122 u32 *dma_buf = i2c_dev->dma_buf; in tegra_i2c_push_packet_header()
1128 FIELD_PREP(PACKET_HEADER0_CONT_ID, i2c_dev->cont_id) | in tegra_i2c_push_packet_header()
1131 if (i2c_dev->dma_mode && !i2c_dev->msg_read) in tegra_i2c_push_packet_header()
1136 packet_header = msg->len - 1; in tegra_i2c_push_packet_header()
1138 if (i2c_dev->dma_mode && !i2c_dev->msg_read) in tegra_i2c_push_packet_header()
1150 if (msg->flags & I2C_M_TEN) { in tegra_i2c_push_packet_header()
1151 packet_header |= msg->addr; in tegra_i2c_push_packet_header()
1154 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; in tegra_i2c_push_packet_header()
1157 if (msg->flags & I2C_M_IGNORE_NAK) in tegra_i2c_push_packet_header()
1160 if (msg->flags & I2C_M_RD) in tegra_i2c_push_packet_header()
1163 if (i2c_dev->dma_mode && !i2c_dev->msg_read) in tegra_i2c_push_packet_header()
1172 if (i2c_dev->msg_err == I2C_ERR_NONE) in tegra_i2c_error_recover()
1177 /* start recovery upon arbitration loss in single master mode */ in tegra_i2c_error_recover()
1178 if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) { in tegra_i2c_error_recover()
1179 if (!i2c_dev->multimaster_mode) in tegra_i2c_error_recover()
1180 return i2c_recover_bus(&i2c_dev->adapter); in tegra_i2c_error_recover()
1182 return -EAGAIN; in tegra_i2c_error_recover()
1185 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { in tegra_i2c_error_recover()
1186 if (msg->flags & I2C_M_IGNORE_NAK) in tegra_i2c_error_recover()
1189 return -EREMOTEIO; in tegra_i2c_error_recover()
1192 return -EIO; in tegra_i2c_error_recover()
1208 i2c_dev->msg_buf = msg->buf; in tegra_i2c_xfer_msg()
1209 i2c_dev->msg_buf_remaining = msg->len; in tegra_i2c_xfer_msg()
1210 i2c_dev->msg_err = I2C_ERR_NONE; in tegra_i2c_xfer_msg()
1211 i2c_dev->msg_read = !!(msg->flags & I2C_M_RD); in tegra_i2c_xfer_msg()
1212 reinit_completion(&i2c_dev->msg_complete); in tegra_i2c_xfer_msg()
1214 if (i2c_dev->msg_read) in tegra_i2c_xfer_msg()
1215 xfer_size = msg->len; in tegra_i2c_xfer_msg()
1217 xfer_size = msg->len + I2C_PACKET_HEADER_SIZE; in tegra_i2c_xfer_msg()
1221 i2c_dev->dma_mode = xfer_size > I2C_PIO_MODE_PREFERRED_LEN && in tegra_i2c_xfer_msg()
1222 i2c_dev->dma_buf && !i2c_dev->atomic_mode; in tegra_i2c_xfer_msg()
1231 i2c_dev->bus_clk_rate); in tegra_i2c_xfer_msg()
1236 if (i2c_dev->dma_mode) { in tegra_i2c_xfer_msg()
1237 if (i2c_dev->msg_read) { in tegra_i2c_xfer_msg()
1238 dma_sync_single_for_device(i2c_dev->dev, in tegra_i2c_xfer_msg()
1239 i2c_dev->dma_phys, in tegra_i2c_xfer_msg()
1246 dma_sync_single_for_cpu(i2c_dev->dev, in tegra_i2c_xfer_msg()
1247 i2c_dev->dma_phys, in tegra_i2c_xfer_msg()
1254 if (!i2c_dev->msg_read) { in tegra_i2c_xfer_msg()
1255 if (i2c_dev->dma_mode) { in tegra_i2c_xfer_msg()
1256 memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE, in tegra_i2c_xfer_msg()
1257 msg->buf, msg->len); in tegra_i2c_xfer_msg()
1259 dma_sync_single_for_device(i2c_dev->dev, in tegra_i2c_xfer_msg()
1260 i2c_dev->dma_phys, in tegra_i2c_xfer_msg()
1271 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq) in tegra_i2c_xfer_msg()
1274 if (!i2c_dev->dma_mode) { in tegra_i2c_xfer_msg()
1275 if (msg->flags & I2C_M_RD) in tegra_i2c_xfer_msg()
1277 else if (i2c_dev->msg_buf_remaining) in tegra_i2c_xfer_msg()
1282 dev_dbg(i2c_dev->dev, "unmasked IRQ: %02x\n", in tegra_i2c_xfer_msg()
1285 if (i2c_dev->dma_mode) { in tegra_i2c_xfer_msg()
1287 &i2c_dev->dma_complete, in tegra_i2c_xfer_msg()
1295 dmaengine_synchronize(i2c_dev->msg_read ? in tegra_i2c_xfer_msg()
1296 i2c_dev->rx_dma_chan : in tegra_i2c_xfer_msg()
1297 i2c_dev->tx_dma_chan); in tegra_i2c_xfer_msg()
1299 dmaengine_terminate_sync(i2c_dev->msg_read ? in tegra_i2c_xfer_msg()
1300 i2c_dev->rx_dma_chan : in tegra_i2c_xfer_msg()
1301 i2c_dev->tx_dma_chan); in tegra_i2c_xfer_msg()
1303 if (!time_left && !completion_done(&i2c_dev->dma_complete)) { in tegra_i2c_xfer_msg()
1304 dev_err(i2c_dev->dev, "DMA transfer timed out\n"); in tegra_i2c_xfer_msg()
1306 return -ETIMEDOUT; in tegra_i2c_xfer_msg()
1309 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) { in tegra_i2c_xfer_msg()
1310 dma_sync_single_for_cpu(i2c_dev->dev, in tegra_i2c_xfer_msg()
1311 i2c_dev->dma_phys, in tegra_i2c_xfer_msg()
1314 memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, msg->len); in tegra_i2c_xfer_msg()
1318 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, in tegra_i2c_xfer_msg()
1324 dev_err(i2c_dev->dev, "I2C transfer timed out\n"); in tegra_i2c_xfer_msg()
1326 return -ETIMEDOUT; in tegra_i2c_xfer_msg()
1329 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n", in tegra_i2c_xfer_msg()
1330 time_left, completion_done(&i2c_dev->msg_complete), in tegra_i2c_xfer_msg()
1331 i2c_dev->msg_err); in tegra_i2c_xfer_msg()
1333 i2c_dev->dma_mode = false; in tegra_i2c_xfer_msg()
1348 ret = pm_runtime_get_sync(i2c_dev->dev); in tegra_i2c_xfer()
1350 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret); in tegra_i2c_xfer()
1351 pm_runtime_put_noidle(i2c_dev->dev); in tegra_i2c_xfer()
1358 if (i < (num - 1)) { in tegra_i2c_xfer()
1370 pm_runtime_put(i2c_dev->dev); in tegra_i2c_xfer()
1381 i2c_dev->atomic_mode = true; in tegra_i2c_xfer_atomic()
1383 i2c_dev->atomic_mode = false; in tegra_i2c_xfer_atomic()
1394 if (i2c_dev->hw->has_continue_xfer_support) in tegra_i2c_func()
1410 .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE,
1415 .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE,
1591 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
1592 { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
1593 { .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_i2c_hw, },
1594 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
1595 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
1596 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
1597 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
1598 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
1599 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
1606 struct device_node *np = i2c_dev->dev->of_node; in tegra_i2c_parse_dt()
1610 err = of_property_read_u32(np, "clock-frequency", in tegra_i2c_parse_dt()
1611 &i2c_dev->bus_clk_rate); in tegra_i2c_parse_dt()
1613 i2c_dev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ; in tegra_i2c_parse_dt()
1615 multi_mode = of_property_read_bool(np, "multi-master"); in tegra_i2c_parse_dt()
1616 i2c_dev->multimaster_mode = multi_mode; in tegra_i2c_parse_dt()
1618 if (of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc")) in tegra_i2c_parse_dt()
1619 i2c_dev->is_dvc = true; in tegra_i2c_parse_dt()
1621 if (of_device_is_compatible(np, "nvidia,tegra210-i2c-vi")) in tegra_i2c_parse_dt()
1622 i2c_dev->is_vi = true; in tegra_i2c_parse_dt()
1629 i2c_dev->clocks[i2c_dev->nclocks++].id = "div-clk"; in tegra_i2c_init_clocks()
1631 if (i2c_dev->hw == &tegra20_i2c_hw || i2c_dev->hw == &tegra30_i2c_hw) in tegra_i2c_init_clocks()
1632 i2c_dev->clocks[i2c_dev->nclocks++].id = "fast-clk"; in tegra_i2c_init_clocks()
1634 if (i2c_dev->is_vi) in tegra_i2c_init_clocks()
1635 i2c_dev->clocks[i2c_dev->nclocks++].id = "slow"; in tegra_i2c_init_clocks()
1637 err = devm_clk_bulk_get(i2c_dev->dev, i2c_dev->nclocks, in tegra_i2c_init_clocks()
1638 i2c_dev->clocks); in tegra_i2c_init_clocks()
1642 err = clk_bulk_prepare(i2c_dev->nclocks, i2c_dev->clocks); in tegra_i2c_init_clocks()
1646 i2c_dev->div_clk = i2c_dev->clocks[0].clk; in tegra_i2c_init_clocks()
1648 if (!i2c_dev->multimaster_mode) in tegra_i2c_init_clocks()
1651 err = clk_enable(i2c_dev->div_clk); in tegra_i2c_init_clocks()
1653 dev_err(i2c_dev->dev, "failed to enable div-clk: %d\n", err); in tegra_i2c_init_clocks()
1660 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks); in tegra_i2c_init_clocks()
1667 if (i2c_dev->multimaster_mode) in tegra_i2c_release_clocks()
1668 clk_disable(i2c_dev->div_clk); in tegra_i2c_release_clocks()
1670 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks); in tegra_i2c_release_clocks()
1677 ret = pm_runtime_get_sync(i2c_dev->dev); in tegra_i2c_init_hardware()
1679 dev_err(i2c_dev->dev, "runtime resume failed: %d\n", ret); in tegra_i2c_init_hardware()
1683 pm_runtime_put(i2c_dev->dev); in tegra_i2c_init_hardware()
1694 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); in tegra_i2c_probe()
1696 return -ENOMEM; in tegra_i2c_probe()
1700 init_completion(&i2c_dev->msg_complete); in tegra_i2c_probe()
1701 init_completion(&i2c_dev->dma_complete); in tegra_i2c_probe()
1703 i2c_dev->hw = of_device_get_match_data(&pdev->dev); in tegra_i2c_probe()
1704 i2c_dev->cont_id = pdev->id; in tegra_i2c_probe()
1705 i2c_dev->dev = &pdev->dev; in tegra_i2c_probe()
1707 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in tegra_i2c_probe()
1708 if (IS_ERR(i2c_dev->base)) in tegra_i2c_probe()
1709 return PTR_ERR(i2c_dev->base); in tegra_i2c_probe()
1711 i2c_dev->base_phys = res->start; in tegra_i2c_probe()
1717 i2c_dev->irq = err; in tegra_i2c_probe()
1720 irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN); in tegra_i2c_probe()
1722 err = devm_request_irq(i2c_dev->dev, i2c_dev->irq, tegra_i2c_isr, in tegra_i2c_probe()
1723 IRQF_NO_SUSPEND, dev_name(i2c_dev->dev), in tegra_i2c_probe()
1728 i2c_dev->rst = devm_reset_control_get_exclusive(i2c_dev->dev, "i2c"); in tegra_i2c_probe()
1729 if (IS_ERR(i2c_dev->rst)) { in tegra_i2c_probe()
1730 dev_err_probe(i2c_dev->dev, PTR_ERR(i2c_dev->rst), in tegra_i2c_probe()
1732 return PTR_ERR(i2c_dev->rst); in tegra_i2c_probe()
1746 * VI I2C is in VE power domain which is not always ON and not in tegra_i2c_probe()
1747 * IRQ-safe. Thus, IRQ-safe device shouldn't be attached to a in tegra_i2c_probe()
1748 * non IRQ-safe domain because this prevents powering off the power in tegra_i2c_probe()
1751 * VI I2C device shouldn't be marked as IRQ-safe because VI I2C won't in tegra_i2c_probe()
1754 if (!i2c_dev->is_vi) in tegra_i2c_probe()
1755 pm_runtime_irq_safe(i2c_dev->dev); in tegra_i2c_probe()
1757 pm_runtime_enable(i2c_dev->dev); in tegra_i2c_probe()
1763 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); in tegra_i2c_probe()
1764 i2c_dev->adapter.dev.of_node = i2c_dev->dev->of_node; in tegra_i2c_probe()
1765 i2c_dev->adapter.dev.parent = i2c_dev->dev; in tegra_i2c_probe()
1766 i2c_dev->adapter.retries = 1; in tegra_i2c_probe()
1767 i2c_dev->adapter.timeout = 6 * HZ; in tegra_i2c_probe()
1768 i2c_dev->adapter.quirks = i2c_dev->hw->quirks; in tegra_i2c_probe()
1769 i2c_dev->adapter.owner = THIS_MODULE; in tegra_i2c_probe()
1770 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED; in tegra_i2c_probe()
1771 i2c_dev->adapter.algo = &tegra_i2c_algo; in tegra_i2c_probe()
1772 i2c_dev->adapter.nr = pdev->id; in tegra_i2c_probe()
1774 if (i2c_dev->hw->supports_bus_clear) in tegra_i2c_probe()
1775 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info; in tegra_i2c_probe()
1777 strlcpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev), in tegra_i2c_probe()
1778 sizeof(i2c_dev->adapter.name)); in tegra_i2c_probe()
1780 err = i2c_add_numbered_adapter(&i2c_dev->adapter); in tegra_i2c_probe()
1787 pm_runtime_disable(i2c_dev->dev); in tegra_i2c_probe()
1800 i2c_del_adapter(&i2c_dev->adapter); in tegra_i2c_remove()
1801 pm_runtime_disable(i2c_dev->dev); in tegra_i2c_remove()
1818 err = clk_bulk_enable(i2c_dev->nclocks, i2c_dev->clocks); in tegra_i2c_runtime_resume()
1823 * VI I2C device is attached to VE power domain which goes through in tegra_i2c_runtime_resume()
1825 * controller needs to be re-initialized after power ON. in tegra_i2c_runtime_resume()
1827 if (i2c_dev->is_vi) { in tegra_i2c_runtime_resume()
1836 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks); in tegra_i2c_runtime_resume()
1845 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks); in tegra_i2c_runtime_suspend()
1855 i2c_mark_adapter_suspended(&i2c_dev->adapter); in tegra_i2c_suspend()
1894 i2c_mark_adapter_resumed(&i2c_dev->adapter); in tegra_i2c_resume()
1909 .name = "tegra-i2c",
1916 MODULE_DESCRIPTION("NVIDIA Tegra I2C Bus Controller driver");