42 #define STM32F7_I2C_CR2				0x04  macro
765 	cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_reload()
775 	writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_reload()
795 	cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_reload()
798 	writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_reload()
855 	cr2 = readl_relaxed(base + STM32F7_I2C_CR2);  in stm32f7_i2c_xfer_msg()
923 	writel_relaxed(cr2, base + STM32F7_I2C_CR2);  in stm32f7_i2c_xfer_msg()
939 	cr2 = readl_relaxed(base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_xfer_msg()
1089 	writel_relaxed(cr2, base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_xfer_msg()
1101 	cr2 = readl_relaxed(base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_rep_start()
1173 	writel_relaxed(cr2, base + STM32F7_I2C_CR2);  in stm32f7_i2c_smbus_rep_start()
1253 		stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);  in stm32f7_i2c_slave_start()
1271 		stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);  in stm32f7_i2c_slave_start()
1417 			cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_slave_isr_event()
1419 			writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_slave_isr_event()
1422 			stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);  in stm32f7_i2c_slave_isr_event()
1518 			stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);  in stm32f7_i2c_isr_event()
1843 	stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);  in stm32f7_i2c_reg_slave()
2276 	backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_regs_backup()
2308 	writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);  in stm32f7_i2c_regs_restore()