Lines Matching full:qup
25 /* QUP Registers */
45 /* QUP States and reset values */
58 /* QUP OPERATIONAL FLAGS */
97 /* QUP tags */
105 /* QUP v2 tags */
144 * Max tags length (start, stop and maximum 2 bytes address) for each QUP
164 * total_tx_len: total tx length including tag bytes for current QUP transfer
165 * total_rx_len: total rx length including tag bytes for current QUP transfer
167 * tx_fifo_free: number of free bytes in current QUP block write.
170 * QUP block read
171 * tx_fifo_data: QUP TX FIFO write works on word basis (4 bytes). New byte write
174 * rx_fifo_data: QUP RX FIFO read works on word basis (4 bytes). This will
184 * tags: contains tx tag bytes for current QUP transfer
248 /* QUP core errors */
273 void (*write_tx_fifo)(struct qup_i2c_dev *qup);
275 void (*read_rx_fifo)(struct qup_i2c_dev *qup);
277 void (*write_rx_tags)(struct qup_i2c_dev *qup);
282 struct qup_i2c_dev *qup = dev; in qup_i2c_interrupt() local
283 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_interrupt()
288 bus_err = readl(qup->base + QUP_I2C_STATUS); in qup_i2c_interrupt()
289 qup_err = readl(qup->base + QUP_ERROR_FLAGS); in qup_i2c_interrupt()
290 opflags = readl(qup->base + QUP_OPERATIONAL); in qup_i2c_interrupt()
292 if (!qup->msg) { in qup_i2c_interrupt()
294 writel(QUP_RESET_STATE, qup->base + QUP_STATE); in qup_i2c_interrupt()
303 writel(qup_err, qup->base + QUP_ERROR_FLAGS); in qup_i2c_interrupt()
307 writel(bus_err, qup->base + QUP_I2C_STATUS); in qup_i2c_interrupt()
311 * transfer. In Error case, sometimes, QUP generates more than one in qup_i2c_interrupt()
314 if (qup->use_dma && (qup->qup_err || qup->bus_err)) in qup_i2c_interrupt()
317 /* Reset the QUP State in case of error */ in qup_i2c_interrupt()
320 * Don’t reset the QUP state in case of BAM mode. The BAM in qup_i2c_interrupt()
325 if (!qup->use_dma) in qup_i2c_interrupt()
326 writel(QUP_RESET_STATE, qup->base + QUP_STATE); in qup_i2c_interrupt()
331 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL); in qup_i2c_interrupt()
334 blk->tx_fifo_free += qup->out_blk_sz; in qup_i2c_interrupt()
335 if (qup->msg->flags & I2C_M_RD) in qup_i2c_interrupt()
336 qup->write_rx_tags(qup); in qup_i2c_interrupt()
338 qup->write_tx_fifo(qup); in qup_i2c_interrupt()
343 writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL); in qup_i2c_interrupt()
346 blk->fifo_available += qup->in_fifo_sz; in qup_i2c_interrupt()
347 qup->read_rx_fifo(qup); in qup_i2c_interrupt()
349 blk->fifo_available += qup->in_blk_sz; in qup_i2c_interrupt()
350 qup->read_rx_fifo(qup); in qup_i2c_interrupt()
354 if (qup->msg->flags & I2C_M_RD) { in qup_i2c_interrupt()
370 qup->qup_err = qup_err; in qup_i2c_interrupt()
371 qup->bus_err = bus_err; in qup_i2c_interrupt()
372 complete(&qup->xfer); in qup_i2c_interrupt()
376 static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup, in qup_i2c_poll_state_mask() argument
387 state = readl(qup->base + QUP_STATE); in qup_i2c_poll_state_mask()
399 static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state) in qup_i2c_poll_state() argument
401 return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK); in qup_i2c_poll_state()
404 static void qup_i2c_flush(struct qup_i2c_dev *qup) in qup_i2c_flush() argument
406 u32 val = readl(qup->base + QUP_STATE); in qup_i2c_flush()
409 writel(val, qup->base + QUP_STATE); in qup_i2c_flush()
412 static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup) in qup_i2c_poll_state_valid() argument
414 return qup_i2c_poll_state_mask(qup, 0, 0); in qup_i2c_poll_state_valid()
417 static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup) in qup_i2c_poll_state_i2c_master() argument
419 return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN); in qup_i2c_poll_state_i2c_master()
422 static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state) in qup_i2c_change_state() argument
424 if (qup_i2c_poll_state_valid(qup) != 0) in qup_i2c_change_state()
427 writel(state, qup->base + QUP_STATE); in qup_i2c_change_state()
429 if (qup_i2c_poll_state(qup, state) != 0) in qup_i2c_change_state()
435 static int qup_i2c_bus_active(struct qup_i2c_dev *qup, int len) in qup_i2c_bus_active() argument
443 status = readl(qup->base + QUP_I2C_STATUS); in qup_i2c_bus_active()
456 static void qup_i2c_write_tx_fifo_v1(struct qup_i2c_dev *qup) in qup_i2c_write_tx_fifo_v1() argument
458 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_tx_fifo_v1()
459 struct i2c_msg *msg = qup->msg; in qup_i2c_write_tx_fifo_v1()
465 if (qup->pos == 0) { in qup_i2c_write_tx_fifo_v1()
474 while (blk->tx_fifo_free && qup->pos < msg->len) { in qup_i2c_write_tx_fifo_v1()
475 if (qup->pos == msg->len - 1) in qup_i2c_write_tx_fifo_v1()
481 val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT; in qup_i2c_write_tx_fifo_v1()
483 val = qup_tag | msg->buf[qup->pos]; in qup_i2c_write_tx_fifo_v1()
486 if (idx & 1 || qup->pos == msg->len - 1) in qup_i2c_write_tx_fifo_v1()
487 writel(val, qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_tx_fifo_v1()
489 qup->pos++; in qup_i2c_write_tx_fifo_v1()
495 static void qup_i2c_set_blk_data(struct qup_i2c_dev *qup, in qup_i2c_set_blk_data() argument
498 qup->blk.pos = 0; in qup_i2c_set_blk_data()
499 qup->blk.data_len = msg->len; in qup_i2c_set_blk_data()
500 qup->blk.count = DIV_ROUND_UP(msg->len, qup->blk_xfer_limit); in qup_i2c_set_blk_data()
503 static int qup_i2c_get_data_len(struct qup_i2c_dev *qup) in qup_i2c_get_data_len() argument
507 if (qup->blk.data_len > qup->blk_xfer_limit) in qup_i2c_get_data_len()
508 data_len = qup->blk_xfer_limit; in qup_i2c_get_data_len()
510 data_len = qup->blk.data_len; in qup_i2c_get_data_len()
520 static int qup_i2c_set_tags_smb(u16 addr, u8 *tags, struct qup_i2c_dev *qup, in qup_i2c_set_tags_smb() argument
525 if (qup->is_smbus_read) { in qup_i2c_set_tags_smb()
527 tags[len++] = qup_i2c_get_data_len(qup); in qup_i2c_set_tags_smb()
542 static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup, in qup_i2c_set_tags() argument
549 int last = (qup->blk.pos == (qup->blk.count - 1)) && (qup->is_last); in qup_i2c_set_tags()
553 return qup_i2c_set_tags_smb(addr, tags, qup, msg); in qup_i2c_set_tags()
555 if (qup->blk.pos == 0) { in qup_i2c_set_tags()
571 tags[len++] = qup->blk.pos == (qup->blk.count - 1) ? in qup_i2c_set_tags()
578 data_len = qup_i2c_get_data_len(qup); in qup_i2c_set_tags()
592 struct qup_i2c_dev *qup = data; in qup_i2c_bam_cb() local
594 complete(&qup->xfer); in qup_i2c_bam_cb()
598 unsigned int buflen, struct qup_i2c_dev *qup, in qup_sg_set_buf() argument
604 ret = dma_map_sg(qup->dev, sg, 1, dir); in qup_sg_set_buf()
611 static void qup_i2c_rel_dma(struct qup_i2c_dev *qup) in qup_i2c_rel_dma() argument
613 if (qup->btx.dma) in qup_i2c_rel_dma()
614 dma_release_channel(qup->btx.dma); in qup_i2c_rel_dma()
615 if (qup->brx.dma) in qup_i2c_rel_dma()
616 dma_release_channel(qup->brx.dma); in qup_i2c_rel_dma()
617 qup->btx.dma = NULL; in qup_i2c_rel_dma()
618 qup->brx.dma = NULL; in qup_i2c_rel_dma()
621 static int qup_i2c_req_dma(struct qup_i2c_dev *qup) in qup_i2c_req_dma() argument
625 if (!qup->btx.dma) { in qup_i2c_req_dma()
626 qup->btx.dma = dma_request_chan(qup->dev, "tx"); in qup_i2c_req_dma()
627 if (IS_ERR(qup->btx.dma)) { in qup_i2c_req_dma()
628 err = PTR_ERR(qup->btx.dma); in qup_i2c_req_dma()
629 qup->btx.dma = NULL; in qup_i2c_req_dma()
630 dev_err(qup->dev, "\n tx channel not available"); in qup_i2c_req_dma()
635 if (!qup->brx.dma) { in qup_i2c_req_dma()
636 qup->brx.dma = dma_request_chan(qup->dev, "rx"); in qup_i2c_req_dma()
637 if (IS_ERR(qup->brx.dma)) { in qup_i2c_req_dma()
638 dev_err(qup->dev, "\n rx channel not available"); in qup_i2c_req_dma()
639 err = PTR_ERR(qup->brx.dma); in qup_i2c_req_dma()
640 qup->brx.dma = NULL; in qup_i2c_req_dma()
641 qup_i2c_rel_dma(qup); in qup_i2c_req_dma()
648 static int qup_i2c_bam_make_desc(struct qup_i2c_dev *qup, struct i2c_msg *msg) in qup_i2c_bam_make_desc() argument
655 qup->blk_xfer_limit = QUP_READ_LIMIT; in qup_i2c_bam_make_desc()
656 qup_i2c_set_blk_data(qup, msg); in qup_i2c_bam_make_desc()
658 blocks = qup->blk.count; in qup_i2c_bam_make_desc()
662 while (qup->blk.pos < blocks) { in qup_i2c_bam_make_desc()
664 tags = &qup->start_tag.start[qup->tag_buf_pos + len]; in qup_i2c_bam_make_desc()
665 len += qup_i2c_set_tags(tags, qup, msg); in qup_i2c_bam_make_desc()
666 qup->blk.data_len -= tlen; in qup_i2c_bam_make_desc()
669 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++], in qup_i2c_bam_make_desc()
670 &qup->brx.tag.start[0], in qup_i2c_bam_make_desc()
671 2, qup, DMA_FROM_DEVICE); in qup_i2c_bam_make_desc()
676 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++], in qup_i2c_bam_make_desc()
678 tlen, qup, in qup_i2c_bam_make_desc()
684 qup->blk.pos = i; in qup_i2c_bam_make_desc()
686 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], in qup_i2c_bam_make_desc()
687 &qup->start_tag.start[qup->tag_buf_pos], in qup_i2c_bam_make_desc()
688 len, qup, DMA_TO_DEVICE); in qup_i2c_bam_make_desc()
692 qup->tag_buf_pos += len; in qup_i2c_bam_make_desc()
694 while (qup->blk.pos < blocks) { in qup_i2c_bam_make_desc()
696 tags = &qup->start_tag.start[qup->tag_buf_pos + tx_len]; in qup_i2c_bam_make_desc()
697 len = qup_i2c_set_tags(tags, qup, msg); in qup_i2c_bam_make_desc()
698 qup->blk.data_len -= tlen; in qup_i2c_bam_make_desc()
700 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], in qup_i2c_bam_make_desc()
702 qup, DMA_TO_DEVICE); in qup_i2c_bam_make_desc()
707 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], in qup_i2c_bam_make_desc()
709 tlen, qup, DMA_TO_DEVICE); in qup_i2c_bam_make_desc()
713 qup->blk.pos = i; in qup_i2c_bam_make_desc()
716 qup->tag_buf_pos += tx_len; in qup_i2c_bam_make_desc()
722 static int qup_i2c_bam_schedule_desc(struct qup_i2c_dev *qup) in qup_i2c_bam_schedule_desc() argument
728 u32 tx_cnt = qup->btx.sg_cnt, rx_cnt = qup->brx.sg_cnt; in qup_i2c_bam_schedule_desc()
733 qup->btx.tag.start[0] = QUP_BAM_INPUT_EOT; in qup_i2c_bam_schedule_desc()
737 ret = qup_sg_set_buf(&qup->brx.sg[rx_cnt++], in qup_i2c_bam_schedule_desc()
738 &qup->brx.tag.start[0], in qup_i2c_bam_schedule_desc()
739 1, qup, DMA_FROM_DEVICE); in qup_i2c_bam_schedule_desc()
744 qup->btx.tag.start[len - 1] = QUP_BAM_FLUSH_STOP; in qup_i2c_bam_schedule_desc()
745 ret = qup_sg_set_buf(&qup->btx.sg[tx_cnt++], &qup->btx.tag.start[0], in qup_i2c_bam_schedule_desc()
746 len, qup, DMA_TO_DEVICE); in qup_i2c_bam_schedule_desc()
750 txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_cnt, in qup_i2c_bam_schedule_desc()
754 dev_err(qup->dev, "failed to get tx desc\n"); in qup_i2c_bam_schedule_desc()
761 txd->callback_param = qup; in qup_i2c_bam_schedule_desc()
770 dma_async_issue_pending(qup->btx.dma); in qup_i2c_bam_schedule_desc()
773 rxd = dmaengine_prep_slave_sg(qup->brx.dma, qup->brx.sg, in qup_i2c_bam_schedule_desc()
777 dev_err(qup->dev, "failed to get rx desc\n"); in qup_i2c_bam_schedule_desc()
781 dmaengine_terminate_all(qup->btx.dma); in qup_i2c_bam_schedule_desc()
786 rxd->callback_param = qup; in qup_i2c_bam_schedule_desc()
793 dma_async_issue_pending(qup->brx.dma); in qup_i2c_bam_schedule_desc()
796 if (!wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout)) { in qup_i2c_bam_schedule_desc()
797 dev_err(qup->dev, "normal trans timed out\n"); in qup_i2c_bam_schedule_desc()
801 if (ret || qup->bus_err || qup->qup_err) { in qup_i2c_bam_schedule_desc()
802 reinit_completion(&qup->xfer); in qup_i2c_bam_schedule_desc()
804 ret = qup_i2c_change_state(qup, QUP_RUN_STATE); in qup_i2c_bam_schedule_desc()
806 dev_err(qup->dev, "change to run state timed out"); in qup_i2c_bam_schedule_desc()
810 qup_i2c_flush(qup); in qup_i2c_bam_schedule_desc()
813 if (!wait_for_completion_timeout(&qup->xfer, HZ)) in qup_i2c_bam_schedule_desc()
814 dev_err(qup->dev, "flush timed out\n"); in qup_i2c_bam_schedule_desc()
816 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO; in qup_i2c_bam_schedule_desc()
820 dma_unmap_sg(qup->dev, qup->btx.sg, tx_cnt, DMA_TO_DEVICE); in qup_i2c_bam_schedule_desc()
823 dma_unmap_sg(qup->dev, qup->brx.sg, rx_cnt, in qup_i2c_bam_schedule_desc()
829 static void qup_i2c_bam_clear_tag_buffers(struct qup_i2c_dev *qup) in qup_i2c_bam_clear_tag_buffers() argument
831 qup->btx.sg_cnt = 0; in qup_i2c_bam_clear_tag_buffers()
832 qup->brx.sg_cnt = 0; in qup_i2c_bam_clear_tag_buffers()
833 qup->tag_buf_pos = 0; in qup_i2c_bam_clear_tag_buffers()
839 struct qup_i2c_dev *qup = i2c_get_adapdata(adap); in qup_i2c_bam_xfer() local
843 enable_irq(qup->irq); in qup_i2c_bam_xfer()
844 ret = qup_i2c_req_dma(qup); in qup_i2c_bam_xfer()
849 writel(0, qup->base + QUP_MX_INPUT_CNT); in qup_i2c_bam_xfer()
850 writel(0, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_bam_xfer()
853 writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE); in qup_i2c_bam_xfer()
856 writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK); in qup_i2c_bam_xfer()
859 ret = qup_i2c_change_state(qup, QUP_RUN_STATE); in qup_i2c_bam_xfer()
863 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); in qup_i2c_bam_xfer()
864 qup_i2c_bam_clear_tag_buffers(qup); in qup_i2c_bam_xfer()
867 qup->msg = msg + idx; in qup_i2c_bam_xfer()
868 qup->is_last = idx == (num - 1); in qup_i2c_bam_xfer()
870 ret = qup_i2c_bam_make_desc(qup, qup->msg); in qup_i2c_bam_xfer()
881 if (qup->btx.sg_cnt > qup->max_xfer_sg_len || in qup_i2c_bam_xfer()
882 qup->brx.sg_cnt > qup->max_xfer_sg_len || in qup_i2c_bam_xfer()
883 qup->is_last) { in qup_i2c_bam_xfer()
884 ret = qup_i2c_bam_schedule_desc(qup); in qup_i2c_bam_xfer()
888 qup_i2c_bam_clear_tag_buffers(qup); in qup_i2c_bam_xfer()
893 disable_irq(qup->irq); in qup_i2c_bam_xfer()
895 qup->msg = NULL; in qup_i2c_bam_xfer()
899 static int qup_i2c_wait_for_complete(struct qup_i2c_dev *qup, in qup_i2c_wait_for_complete() argument
905 left = wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout); in qup_i2c_wait_for_complete()
907 writel(1, qup->base + QUP_SW_RESET); in qup_i2c_wait_for_complete()
911 if (qup->bus_err || qup->qup_err) in qup_i2c_wait_for_complete()
912 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO; in qup_i2c_wait_for_complete()
917 static void qup_i2c_read_rx_fifo_v1(struct qup_i2c_dev *qup) in qup_i2c_read_rx_fifo_v1() argument
919 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_read_rx_fifo_v1()
920 struct i2c_msg *msg = qup->msg; in qup_i2c_read_rx_fifo_v1()
924 while (blk->fifo_available && qup->pos < msg->len) { in qup_i2c_read_rx_fifo_v1()
927 val = readl(qup->base + QUP_IN_FIFO_BASE); in qup_i2c_read_rx_fifo_v1()
928 msg->buf[qup->pos++] = val & 0xFF; in qup_i2c_read_rx_fifo_v1()
930 msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT; in qup_i2c_read_rx_fifo_v1()
936 if (qup->pos == msg->len) in qup_i2c_read_rx_fifo_v1()
940 static void qup_i2c_write_rx_tags_v1(struct qup_i2c_dev *qup) in qup_i2c_write_rx_tags_v1() argument
942 struct i2c_msg *msg = qup->msg; in qup_i2c_write_rx_tags_v1()
951 writel(val, qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_rx_tags_v1()
954 static void qup_i2c_conf_v1(struct qup_i2c_dev *qup) in qup_i2c_conf_v1() argument
956 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_v1()
960 blk->is_tx_blk_mode = blk->total_tx_len > qup->out_fifo_sz; in qup_i2c_conf_v1()
961 blk->is_rx_blk_mode = blk->total_rx_len > qup->in_fifo_sz; in qup_i2c_conf_v1()
965 writel(0, qup->base + QUP_MX_WRITE_CNT); in qup_i2c_conf_v1()
966 writel(blk->total_tx_len, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_conf_v1()
968 writel(0, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_conf_v1()
969 writel(blk->total_tx_len, qup->base + QUP_MX_WRITE_CNT); in qup_i2c_conf_v1()
975 writel(0, qup->base + QUP_MX_READ_CNT); in qup_i2c_conf_v1()
976 writel(blk->total_rx_len, qup->base + QUP_MX_INPUT_CNT); in qup_i2c_conf_v1()
978 writel(0, qup->base + QUP_MX_INPUT_CNT); in qup_i2c_conf_v1()
979 writel(blk->total_rx_len, qup->base + QUP_MX_READ_CNT); in qup_i2c_conf_v1()
985 writel(qup_config, qup->base + QUP_CONFIG); in qup_i2c_conf_v1()
986 writel(io_mode, qup->base + QUP_IO_MODE); in qup_i2c_conf_v1()
996 static int qup_i2c_conf_xfer_v1(struct qup_i2c_dev *qup, bool is_rx) in qup_i2c_conf_xfer_v1() argument
998 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_xfer_v1()
1002 qup_i2c_conf_v1(qup); in qup_i2c_conf_xfer_v1()
1003 ret = qup_i2c_change_state(qup, QUP_RUN_STATE); in qup_i2c_conf_xfer_v1()
1007 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); in qup_i2c_conf_xfer_v1()
1009 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); in qup_i2c_conf_xfer_v1()
1013 reinit_completion(&qup->xfer); in qup_i2c_conf_xfer_v1()
1014 enable_irq(qup->irq); in qup_i2c_conf_xfer_v1()
1016 blk->tx_fifo_free = qup->out_fifo_sz; in qup_i2c_conf_xfer_v1()
1019 qup_i2c_write_rx_tags_v1(qup); in qup_i2c_conf_xfer_v1()
1021 qup_i2c_write_tx_fifo_v1(qup); in qup_i2c_conf_xfer_v1()
1024 ret = qup_i2c_change_state(qup, QUP_RUN_STATE); in qup_i2c_conf_xfer_v1()
1028 ret = qup_i2c_wait_for_complete(qup, qup->msg); in qup_i2c_conf_xfer_v1()
1032 ret = qup_i2c_bus_active(qup, ONE_BYTE); in qup_i2c_conf_xfer_v1()
1035 disable_irq(qup->irq); in qup_i2c_conf_xfer_v1()
1039 static int qup_i2c_write_one(struct qup_i2c_dev *qup) in qup_i2c_write_one() argument
1041 struct i2c_msg *msg = qup->msg; in qup_i2c_write_one()
1042 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_one()
1044 qup->pos = 0; in qup_i2c_write_one()
1048 return qup_i2c_conf_xfer_v1(qup, false); in qup_i2c_write_one()
1051 static int qup_i2c_read_one(struct qup_i2c_dev *qup) in qup_i2c_read_one() argument
1053 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_read_one()
1055 qup->pos = 0; in qup_i2c_read_one()
1057 blk->total_rx_len = qup->msg->len; in qup_i2c_read_one()
1059 return qup_i2c_conf_xfer_v1(qup, true); in qup_i2c_read_one()
1066 struct qup_i2c_dev *qup = i2c_get_adapdata(adap); in qup_i2c_xfer() local
1069 ret = pm_runtime_get_sync(qup->dev); in qup_i2c_xfer()
1073 qup->bus_err = 0; in qup_i2c_xfer()
1074 qup->qup_err = 0; in qup_i2c_xfer()
1076 writel(1, qup->base + QUP_SW_RESET); in qup_i2c_xfer()
1077 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE); in qup_i2c_xfer()
1081 /* Configure QUP as I2C mini core */ in qup_i2c_xfer()
1082 writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG); in qup_i2c_xfer()
1085 if (qup_i2c_poll_state_i2c_master(qup)) { in qup_i2c_xfer()
1095 qup->msg = &msgs[idx]; in qup_i2c_xfer()
1097 ret = qup_i2c_read_one(qup); in qup_i2c_xfer()
1099 ret = qup_i2c_write_one(qup); in qup_i2c_xfer()
1104 ret = qup_i2c_change_state(qup, QUP_RESET_STATE); in qup_i2c_xfer()
1113 pm_runtime_mark_last_busy(qup->dev); in qup_i2c_xfer()
1114 pm_runtime_put_autosuspend(qup->dev); in qup_i2c_xfer()
1123 static void qup_i2c_conf_count_v2(struct qup_i2c_dev *qup) in qup_i2c_conf_count_v2() argument
1125 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_count_v2()
1129 writel(qup->config_run | blk->total_tx_len, in qup_i2c_conf_count_v2()
1130 qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_conf_count_v2()
1132 writel(qup->config_run | blk->total_tx_len, in qup_i2c_conf_count_v2()
1133 qup->base + QUP_MX_WRITE_CNT); in qup_i2c_conf_count_v2()
1137 writel(qup->config_run | blk->total_rx_len, in qup_i2c_conf_count_v2()
1138 qup->base + QUP_MX_INPUT_CNT); in qup_i2c_conf_count_v2()
1140 writel(qup->config_run | blk->total_rx_len, in qup_i2c_conf_count_v2()
1141 qup->base + QUP_MX_READ_CNT); in qup_i2c_conf_count_v2()
1146 writel(qup_config, qup->base + QUP_CONFIG); in qup_i2c_conf_count_v2()
1152 * QUP RESET state.
1154 static void qup_i2c_conf_mode_v2(struct qup_i2c_dev *qup) in qup_i2c_conf_mode_v2() argument
1156 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_mode_v2()
1161 writel(0, qup->base + QUP_MX_WRITE_CNT); in qup_i2c_conf_mode_v2()
1163 writel(0, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_conf_mode_v2()
1168 writel(0, qup->base + QUP_MX_READ_CNT); in qup_i2c_conf_mode_v2()
1170 writel(0, qup->base + QUP_MX_INPUT_CNT); in qup_i2c_conf_mode_v2()
1173 writel(io_mode, qup->base + QUP_IO_MODE); in qup_i2c_conf_mode_v2()
1176 /* Clear required variables before starting of any QUP v2 sub transfer. */
1192 /* Receive data from RX FIFO for read message in QUP v2 i2c transfer. */
1193 static void qup_i2c_recv_data(struct qup_i2c_dev *qup) in qup_i2c_recv_data() argument
1195 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_recv_data()
1202 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE); in qup_i2c_recv_data()
1216 /* Receive tags for read message in QUP v2 i2c transfer. */
1217 static void qup_i2c_recv_tags(struct qup_i2c_dev *qup) in qup_i2c_recv_tags() argument
1219 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_recv_tags()
1221 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE); in qup_i2c_recv_tags()
1230 * 1. Check if rx_tags_fetched is false i.e. the start of QUP block so receive
1235 static void qup_i2c_read_rx_fifo_v2(struct qup_i2c_dev *qup) in qup_i2c_read_rx_fifo_v2() argument
1237 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_read_rx_fifo_v2()
1240 qup_i2c_recv_tags(qup); in qup_i2c_read_rx_fifo_v2()
1244 qup_i2c_recv_data(qup); in qup_i2c_read_rx_fifo_v2()
1250 * Write bytes in TX FIFO for write message in QUP v2 i2c transfer. QUP TX FIFO
1255 qup_i2c_write_blk_data(struct qup_i2c_dev *qup, u8 **data, unsigned int *len) in qup_i2c_write_blk_data() argument
1257 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_blk_data()
1265 qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_blk_data()
1276 /* Transfer tags for read message in QUP v2 i2c transfer. */
1277 static void qup_i2c_write_rx_tags_v2(struct qup_i2c_dev *qup) in qup_i2c_write_rx_tags_v2() argument
1279 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_rx_tags_v2()
1281 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, &blk->tx_tag_len); in qup_i2c_write_rx_tags_v2()
1283 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_rx_tags_v2()
1288 * need to be written and QUP write tags can have maximum 256 data length, so
1290 * 1. Check if tx_tags_sent is false i.e. the start of QUP block so write the
1308 static void qup_i2c_write_tx_fifo_v2(struct qup_i2c_dev *qup) in qup_i2c_write_tx_fifo_v2() argument
1310 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_tx_fifo_v2()
1313 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, in qup_i2c_write_tx_fifo_v2()
1321 qup_i2c_write_blk_data(qup, &blk->cur_data, &blk->cur_blk_len); in qup_i2c_write_tx_fifo_v2()
1335 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_tx_fifo_v2()
1340 * The QUP v2 supports reconfiguration during run in which multiple i2c sub
1344 qup_i2c_conf_xfer_v2(struct qup_i2c_dev *qup, bool is_rx, bool is_first, in qup_i2c_conf_xfer_v2() argument
1347 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_xfer_v2()
1348 struct i2c_msg *msg = qup->msg; in qup_i2c_conf_xfer_v2()
1353 * done into 2 QUP reads. One with message length 1 while other one is in qup_i2c_conf_xfer_v2()
1357 if (qup->is_smbus_read) { in qup_i2c_conf_xfer_v2()
1370 qup->config_run = is_first ? 0 : QUP_I2C_MX_CONFIG_DURING_RUN; in qup_i2c_conf_xfer_v2()
1373 qup_i2c_conf_count_v2(qup); in qup_i2c_conf_xfer_v2()
1377 ret = qup_i2c_change_state(qup, QUP_RUN_STATE); in qup_i2c_conf_xfer_v2()
1381 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); in qup_i2c_conf_xfer_v2()
1383 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); in qup_i2c_conf_xfer_v2()
1388 reinit_completion(&qup->xfer); in qup_i2c_conf_xfer_v2()
1389 enable_irq(qup->irq); in qup_i2c_conf_xfer_v2()
1395 blk->tx_fifo_free = qup->out_fifo_sz; in qup_i2c_conf_xfer_v2()
1398 qup_i2c_write_rx_tags_v2(qup); in qup_i2c_conf_xfer_v2()
1400 qup_i2c_write_tx_fifo_v2(qup); in qup_i2c_conf_xfer_v2()
1403 ret = qup_i2c_change_state(qup, QUP_RUN_STATE); in qup_i2c_conf_xfer_v2()
1407 ret = qup_i2c_wait_for_complete(qup, msg); in qup_i2c_conf_xfer_v2()
1413 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE); in qup_i2c_conf_xfer_v2()
1419 disable_irq(qup->irq); in qup_i2c_conf_xfer_v2()
1426 * QUP block individually.
1428 static int qup_i2c_xfer_v2_msg(struct qup_i2c_dev *qup, int msg_id, bool is_rx) in qup_i2c_xfer_v2_msg() argument
1432 struct i2c_msg *msg = qup->msg; in qup_i2c_xfer_v2_msg()
1433 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_xfer_v2_msg()
1436 qup->blk_xfer_limit = is_rx ? RECV_MAX_DATA_LEN : QUP_READ_LIMIT; in qup_i2c_xfer_v2_msg()
1437 qup_i2c_set_blk_data(qup, msg); in qup_i2c_xfer_v2_msg()
1440 data_len = qup_i2c_get_data_len(qup); in qup_i2c_xfer_v2_msg()
1445 qup_i2c_set_tags(blk->cur_tx_tags, qup, qup->msg); in qup_i2c_xfer_v2_msg()
1458 ret = qup_i2c_conf_xfer_v2(qup, is_rx, !msg_id && !i, in qup_i2c_xfer_v2_msg()
1459 !qup->is_last || i < blk->count - 1); in qup_i2c_xfer_v2_msg()
1465 !qup->is_smbus_read) { in qup_i2c_xfer_v2_msg()
1470 qup->is_smbus_read = true; in qup_i2c_xfer_v2_msg()
1471 ret = qup_i2c_xfer_v2_msg(qup, msg_id, true); in qup_i2c_xfer_v2_msg()
1472 qup->is_smbus_read = false; in qup_i2c_xfer_v2_msg()
1480 blk->data_len -= qup->blk_xfer_limit; in qup_i2c_xfer_v2_msg()
1487 * QUP v2 supports 3 modes
1503 qup_i2c_determine_mode_v2(struct qup_i2c_dev *qup, in qup_i2c_determine_mode_v2() argument
1525 if (!no_dma && qup->is_dma && in qup_i2c_determine_mode_v2()
1526 (total_len > qup->out_fifo_sz || total_len > qup->in_fifo_sz)) { in qup_i2c_determine_mode_v2()
1527 qup->use_dma = true; in qup_i2c_determine_mode_v2()
1529 qup->blk.is_tx_blk_mode = max_tx_len > qup->out_fifo_sz - in qup_i2c_determine_mode_v2()
1531 qup->blk.is_rx_blk_mode = max_rx_len > qup->in_fifo_sz - in qup_i2c_determine_mode_v2()
1542 struct qup_i2c_dev *qup = i2c_get_adapdata(adap); in qup_i2c_xfer_v2() local
1545 qup->bus_err = 0; in qup_i2c_xfer_v2()
1546 qup->qup_err = 0; in qup_i2c_xfer_v2()
1548 ret = pm_runtime_get_sync(qup->dev); in qup_i2c_xfer_v2()
1552 ret = qup_i2c_determine_mode_v2(qup, msgs, num); in qup_i2c_xfer_v2()
1556 writel(1, qup->base + QUP_SW_RESET); in qup_i2c_xfer_v2()
1557 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE); in qup_i2c_xfer_v2()
1561 /* Configure QUP as I2C mini core */ in qup_i2c_xfer_v2()
1562 writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG); in qup_i2c_xfer_v2()
1563 writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN); in qup_i2c_xfer_v2()
1565 if (qup_i2c_poll_state_i2c_master(qup)) { in qup_i2c_xfer_v2()
1570 if (qup->use_dma) { in qup_i2c_xfer_v2()
1571 reinit_completion(&qup->xfer); in qup_i2c_xfer_v2()
1573 qup->use_dma = false; in qup_i2c_xfer_v2()
1575 qup_i2c_conf_mode_v2(qup); in qup_i2c_xfer_v2()
1578 qup->msg = &msgs[idx]; in qup_i2c_xfer_v2()
1579 qup->is_last = idx == (num - 1); in qup_i2c_xfer_v2()
1581 ret = qup_i2c_xfer_v2_msg(qup, idx, in qup_i2c_xfer_v2()
1586 qup->msg = NULL; in qup_i2c_xfer_v2()
1590 ret = qup_i2c_bus_active(qup, ONE_BYTE); in qup_i2c_xfer_v2()
1593 qup_i2c_change_state(qup, QUP_RESET_STATE); in qup_i2c_xfer_v2()
1598 pm_runtime_mark_last_busy(qup->dev); in qup_i2c_xfer_v2()
1599 pm_runtime_put_autosuspend(qup->dev); in qup_i2c_xfer_v2()
1620 * The QUP block will issue a NACK and STOP on the bus when reaching
1633 static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup) in qup_i2c_enable_clocks() argument
1635 clk_prepare_enable(qup->clk); in qup_i2c_enable_clocks()
1636 clk_prepare_enable(qup->pclk); in qup_i2c_enable_clocks()
1639 static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup) in qup_i2c_disable_clocks() argument
1643 qup_i2c_change_state(qup, QUP_RESET_STATE); in qup_i2c_disable_clocks()
1644 clk_disable_unprepare(qup->clk); in qup_i2c_disable_clocks()
1645 config = readl(qup->base + QUP_CONFIG); in qup_i2c_disable_clocks()
1647 writel(config, qup->base + QUP_CONFIG); in qup_i2c_disable_clocks()
1648 clk_disable_unprepare(qup->pclk); in qup_i2c_disable_clocks()
1660 struct qup_i2c_dev *qup; in qup_i2c_probe() local
1669 qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL); in qup_i2c_probe()
1670 if (!qup) in qup_i2c_probe()
1673 qup->dev = &pdev->dev; in qup_i2c_probe()
1674 init_completion(&qup->xfer); in qup_i2c_probe()
1675 platform_set_drvdata(pdev, qup); in qup_i2c_probe()
1678 dev_notice(qup->dev, "Using override frequency of %u\n", scl_freq); in qup_i2c_probe()
1681 ret = device_property_read_u32(qup->dev, "clock-frequency", &clk_freq); in qup_i2c_probe()
1683 dev_notice(qup->dev, "using default clock-frequency %d", in qup_i2c_probe()
1688 if (of_device_is_compatible(pdev->dev.of_node, "qcom,i2c-qup-v1.1.1")) { in qup_i2c_probe()
1689 qup->adap.algo = &qup_i2c_algo; in qup_i2c_probe()
1690 qup->adap.quirks = &qup_i2c_quirks; in qup_i2c_probe()
1693 qup->adap.algo = &qup_i2c_algo_v2; in qup_i2c_probe()
1694 qup->adap.quirks = &qup_i2c_quirks_v2; in qup_i2c_probe()
1696 if (acpi_match_device(qup_i2c_acpi_match, qup->dev)) in qup_i2c_probe()
1699 ret = qup_i2c_req_dma(qup); in qup_i2c_probe()
1706 qup->max_xfer_sg_len = (MX_BLOCKS << 1); in qup_i2c_probe()
1708 qup->btx.sg = devm_kcalloc(&pdev->dev, in qup_i2c_probe()
1709 blocks, sizeof(*qup->btx.sg), in qup_i2c_probe()
1711 if (!qup->btx.sg) { in qup_i2c_probe()
1715 sg_init_table(qup->btx.sg, blocks); in qup_i2c_probe()
1717 qup->brx.sg = devm_kcalloc(&pdev->dev, in qup_i2c_probe()
1718 blocks, sizeof(*qup->brx.sg), in qup_i2c_probe()
1720 if (!qup->brx.sg) { in qup_i2c_probe()
1724 sg_init_table(qup->brx.sg, blocks); in qup_i2c_probe()
1729 qup->start_tag.start = devm_kzalloc(&pdev->dev, in qup_i2c_probe()
1731 if (!qup->start_tag.start) { in qup_i2c_probe()
1736 qup->brx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL); in qup_i2c_probe()
1737 if (!qup->brx.tag.start) { in qup_i2c_probe()
1742 qup->btx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL); in qup_i2c_probe()
1743 if (!qup->btx.tag.start) { in qup_i2c_probe()
1747 qup->is_dma = true; in qup_i2c_probe()
1753 dev_err(qup->dev, "clock frequency not supported %d\n", in qup_i2c_probe()
1758 qup->base = devm_platform_ioremap_resource(pdev, 0); in qup_i2c_probe()
1759 if (IS_ERR(qup->base)) in qup_i2c_probe()
1760 return PTR_ERR(qup->base); in qup_i2c_probe()
1762 qup->irq = platform_get_irq(pdev, 0); in qup_i2c_probe()
1763 if (qup->irq < 0) in qup_i2c_probe()
1764 return qup->irq; in qup_i2c_probe()
1766 if (has_acpi_companion(qup->dev)) { in qup_i2c_probe()
1767 ret = device_property_read_u32(qup->dev, in qup_i2c_probe()
1770 dev_notice(qup->dev, "using default src-clock-hz %d", in qup_i2c_probe()
1773 ACPI_COMPANION_SET(&qup->adap.dev, ACPI_COMPANION(qup->dev)); in qup_i2c_probe()
1775 qup->clk = devm_clk_get(qup->dev, "core"); in qup_i2c_probe()
1776 if (IS_ERR(qup->clk)) { in qup_i2c_probe()
1777 dev_err(qup->dev, "Could not get core clock\n"); in qup_i2c_probe()
1778 return PTR_ERR(qup->clk); in qup_i2c_probe()
1781 qup->pclk = devm_clk_get(qup->dev, "iface"); in qup_i2c_probe()
1782 if (IS_ERR(qup->pclk)) { in qup_i2c_probe()
1783 dev_err(qup->dev, "Could not get iface clock\n"); in qup_i2c_probe()
1784 return PTR_ERR(qup->pclk); in qup_i2c_probe()
1786 qup_i2c_enable_clocks(qup); in qup_i2c_probe()
1787 src_clk_freq = clk_get_rate(qup->clk); in qup_i2c_probe()
1791 * Bootloaders might leave a pending interrupt on certain QUP's, in qup_i2c_probe()
1794 writel(1, qup->base + QUP_SW_RESET); in qup_i2c_probe()
1795 ret = qup_i2c_poll_state_valid(qup); in qup_i2c_probe()
1799 ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt, in qup_i2c_probe()
1800 IRQF_TRIGGER_HIGH, "i2c_qup", qup); in qup_i2c_probe()
1802 dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq); in qup_i2c_probe()
1805 disable_irq(qup->irq); in qup_i2c_probe()
1807 hw_ver = readl(qup->base + QUP_HW_VERSION); in qup_i2c_probe()
1808 dev_dbg(qup->dev, "Revision %x\n", hw_ver); in qup_i2c_probe()
1810 io_mode = readl(qup->base + QUP_IO_MODE); in qup_i2c_probe()
1821 qup->out_blk_sz = blk_sizes[size]; in qup_i2c_probe()
1828 qup->in_blk_sz = blk_sizes[size]; in qup_i2c_probe()
1832 * in QUP v1, QUP_CONFIG uses N as 15 i.e 16 bits constitutes a in qup_i2c_probe()
1836 qup->in_blk_sz /= 2; in qup_i2c_probe()
1837 qup->out_blk_sz /= 2; in qup_i2c_probe()
1838 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v1; in qup_i2c_probe()
1839 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v1; in qup_i2c_probe()
1840 qup->write_rx_tags = qup_i2c_write_rx_tags_v1; in qup_i2c_probe()
1842 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v2; in qup_i2c_probe()
1843 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v2; in qup_i2c_probe()
1844 qup->write_rx_tags = qup_i2c_write_rx_tags_v2; in qup_i2c_probe()
1848 qup->out_fifo_sz = qup->out_blk_sz * (2 << size); in qup_i2c_probe()
1851 qup->in_fifo_sz = qup->in_blk_sz * (2 << size); in qup_i2c_probe()
1856 qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff); in qup_i2c_probe()
1860 qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff); in qup_i2c_probe()
1868 qup->one_byte_t = one_bit_t * 9; in qup_i2c_probe()
1869 qup->xfer_timeout = TOUT_MIN * HZ + in qup_i2c_probe()
1870 usecs_to_jiffies(MX_DMA_TX_RX_LEN * qup->one_byte_t); in qup_i2c_probe()
1872 dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n", in qup_i2c_probe()
1873 qup->in_blk_sz, qup->in_fifo_sz, in qup_i2c_probe()
1874 qup->out_blk_sz, qup->out_fifo_sz); in qup_i2c_probe()
1876 i2c_set_adapdata(&qup->adap, qup); in qup_i2c_probe()
1877 qup->adap.dev.parent = qup->dev; in qup_i2c_probe()
1878 qup->adap.dev.of_node = pdev->dev.of_node; in qup_i2c_probe()
1879 qup->is_last = true; in qup_i2c_probe()
1881 strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name)); in qup_i2c_probe()
1883 pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC); in qup_i2c_probe()
1884 pm_runtime_use_autosuspend(qup->dev); in qup_i2c_probe()
1885 pm_runtime_set_active(qup->dev); in qup_i2c_probe()
1886 pm_runtime_enable(qup->dev); in qup_i2c_probe()
1888 ret = i2c_add_adapter(&qup->adap); in qup_i2c_probe()
1895 pm_runtime_disable(qup->dev); in qup_i2c_probe()
1896 pm_runtime_set_suspended(qup->dev); in qup_i2c_probe()
1898 qup_i2c_disable_clocks(qup); in qup_i2c_probe()
1900 if (qup->btx.dma) in qup_i2c_probe()
1901 dma_release_channel(qup->btx.dma); in qup_i2c_probe()
1902 if (qup->brx.dma) in qup_i2c_probe()
1903 dma_release_channel(qup->brx.dma); in qup_i2c_probe()
1909 struct qup_i2c_dev *qup = platform_get_drvdata(pdev); in qup_i2c_remove() local
1911 if (qup->is_dma) { in qup_i2c_remove()
1912 dma_release_channel(qup->btx.dma); in qup_i2c_remove()
1913 dma_release_channel(qup->brx.dma); in qup_i2c_remove()
1916 disable_irq(qup->irq); in qup_i2c_remove()
1917 qup_i2c_disable_clocks(qup); in qup_i2c_remove()
1918 i2c_del_adapter(&qup->adap); in qup_i2c_remove()
1919 pm_runtime_disable(qup->dev); in qup_i2c_remove()
1920 pm_runtime_set_suspended(qup->dev); in qup_i2c_remove()
1927 struct qup_i2c_dev *qup = dev_get_drvdata(device); in qup_i2c_pm_suspend_runtime() local
1930 qup_i2c_disable_clocks(qup); in qup_i2c_pm_suspend_runtime()
1936 struct qup_i2c_dev *qup = dev_get_drvdata(device); in qup_i2c_pm_resume_runtime() local
1939 qup_i2c_enable_clocks(qup); in qup_i2c_pm_resume_runtime()
1972 { .compatible = "qcom,i2c-qup-v1.1.1" },
1973 { .compatible = "qcom,i2c-qup-v2.1.1" },
1974 { .compatible = "qcom,i2c-qup-v2.2.1" },