141 #define NPCM_I2CFIF_CTS			0x10 /* Both FIFOs Control and Status */  macro
469 	val = ioread8(bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_clear_fifo_int()
471 	iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_clear_fifo_int()
649 	iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_reset()
1051 				 bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_int_slave_handler()
1076 		iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_int_slave_handler()
1123 				 bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_int_slave_handler()
1131 				       ioread8(bus->reg + NPCM_I2CFIF_CTS))) {  in npcm_i2c_int_slave_handler()
1140 		iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_int_slave_handler()
1408 				data = ioread8(bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_master_handler_read()
1410 				iowrite8(data, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_master_handler_read()
1459 		iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_handle_nack()
1573 		fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_handle_sda()
1578 		iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_handle_sda()
1582 		iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_irq_handle_sda()
1695 	fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_recovery_tgclk()
1698 	iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_recovery_tgclk()
2029 		i2cfif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_master_start_xmit()
2032 		iowrite8(i2cfif_cts, bus->reg + NPCM_I2CFIF_CTS);  in npcm_i2c_master_start_xmit()