Lines Matching +full:i2c +full:- +full:sda +full:- +full:hold +full:- +full:time +full:- +full:ns
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Synopsys DesignWare I2C adapter driver (master only).
5 * Based on the TI DAVINCI I2C adapter driver.
16 #include <linux/i2c.h>
24 #include "i2c-designware-core.h"
29 regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2); in i2c_dw_configure_fifo_master()
30 regmap_write(dev->map, DW_IC_RX_TL, 0); in i2c_dw_configure_fifo_master()
32 /* Configure the I2C master */ in i2c_dw_configure_fifo_master()
33 regmap_write(dev->map, DW_IC_CON, dev->master_cfg); in i2c_dw_configure_fifo_master()
41 struct i2c_timings *t = &dev->timings; in i2c_dw_set_timings_master()
49 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1); in i2c_dw_set_timings_master()
55 sda_falling_time = t->sda_fall_ns ?: 300; /* ns */ in i2c_dw_set_timings_master()
56 scl_falling_time = t->scl_fall_ns ?: 300; /* ns */ in i2c_dw_set_timings_master()
59 if (!dev->ss_hcnt || !dev->ss_lcnt) { in i2c_dw_set_timings_master()
61 dev->ss_hcnt = in i2c_dw_set_timings_master()
67 dev->ss_lcnt = in i2c_dw_set_timings_master()
73 dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n", in i2c_dw_set_timings_master()
74 dev->ss_hcnt, dev->ss_lcnt); in i2c_dw_set_timings_master()
81 if (t->bus_freq_hz == 1000000) { in i2c_dw_set_timings_master()
86 if (dev->fp_hcnt && dev->fp_lcnt) { in i2c_dw_set_timings_master()
87 dev->fs_hcnt = dev->fp_hcnt; in i2c_dw_set_timings_master()
88 dev->fs_lcnt = dev->fp_lcnt; in i2c_dw_set_timings_master()
91 dev->fs_hcnt = in i2c_dw_set_timings_master()
93 260, /* tHIGH = 260 ns */ in i2c_dw_set_timings_master()
97 dev->fs_lcnt = in i2c_dw_set_timings_master()
99 500, /* tLOW = 500 ns */ in i2c_dw_set_timings_master()
109 if (!dev->fs_hcnt || !dev->fs_lcnt) { in i2c_dw_set_timings_master()
111 dev->fs_hcnt = in i2c_dw_set_timings_master()
117 dev->fs_lcnt = in i2c_dw_set_timings_master()
123 dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n", in i2c_dw_set_timings_master()
124 fp_str, dev->fs_hcnt, dev->fs_lcnt); in i2c_dw_set_timings_master()
127 if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) == in i2c_dw_set_timings_master()
131 dev_err(dev->dev, "High Speed not supported!\n"); in i2c_dw_set_timings_master()
132 dev->master_cfg &= ~DW_IC_CON_SPEED_MASK; in i2c_dw_set_timings_master()
133 dev->master_cfg |= DW_IC_CON_SPEED_FAST; in i2c_dw_set_timings_master()
134 dev->hs_hcnt = 0; in i2c_dw_set_timings_master()
135 dev->hs_lcnt = 0; in i2c_dw_set_timings_master()
136 } else if (!dev->hs_hcnt || !dev->hs_lcnt) { in i2c_dw_set_timings_master()
138 dev->hs_hcnt = in i2c_dw_set_timings_master()
140 160, /* tHIGH = 160 ns */ in i2c_dw_set_timings_master()
144 dev->hs_lcnt = in i2c_dw_set_timings_master()
146 320, /* tLOW = 320 ns */ in i2c_dw_set_timings_master()
150 dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n", in i2c_dw_set_timings_master()
151 dev->hs_hcnt, dev->hs_lcnt); in i2c_dw_set_timings_master()
158 switch (dev->master_cfg & DW_IC_CON_SPEED_MASK) { in i2c_dw_set_timings_master()
168 dev_dbg(dev->dev, "Bus speed: %s%s\n", mode_str, fp_str); in i2c_dw_set_timings_master()
175 * i2c_dw_init() - Initialize the designware I2C master hardware
178 * This functions configures and enables the I2C master.
179 * This function is called during I2C init function, and in case of timeout at
180 * run time.
194 regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt); in i2c_dw_init_master()
195 regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt); in i2c_dw_init_master()
198 regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt); in i2c_dw_init_master()
199 regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt); in i2c_dw_init_master()
202 if (dev->hs_hcnt && dev->hs_lcnt) { in i2c_dw_init_master()
203 regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt); in i2c_dw_init_master()
204 regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt); in i2c_dw_init_master()
207 /* Write SDA hold time if supported */ in i2c_dw_init_master()
208 if (dev->sda_hold_time) in i2c_dw_init_master()
209 regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time); in i2c_dw_init_master()
219 struct i2c_msg *msgs = dev->msgs; in i2c_dw_xfer_init()
227 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) { in i2c_dw_xfer_init()
230 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing in i2c_dw_xfer_init()
238 regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER, in i2c_dw_xfer_init()
242 * Set the slave (target) address and enable 10-bit addressing mode in i2c_dw_xfer_init()
245 regmap_write(dev->map, DW_IC_TAR, in i2c_dw_xfer_init()
246 msgs[dev->msg_write_idx].addr | ic_tar); in i2c_dw_xfer_init()
255 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy); in i2c_dw_xfer_init()
258 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy); in i2c_dw_xfer_init()
259 regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_MASTER_MASK); in i2c_dw_xfer_init()
271 struct i2c_msg *msgs = dev->msgs; in i2c_dw_xfer_msg()
274 u32 addr = msgs[dev->msg_write_idx].addr; in i2c_dw_xfer_msg()
275 u32 buf_len = dev->tx_buf_len; in i2c_dw_xfer_msg()
276 u8 *buf = dev->tx_buf; in i2c_dw_xfer_msg()
282 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { in i2c_dw_xfer_msg()
283 u32 flags = msgs[dev->msg_write_idx].flags; in i2c_dw_xfer_msg()
287 * reprogram the target address in the I2C in i2c_dw_xfer_msg()
290 if (msgs[dev->msg_write_idx].addr != addr) { in i2c_dw_xfer_msg()
291 dev_err(dev->dev, in i2c_dw_xfer_msg()
293 dev->msg_err = -EINVAL; in i2c_dw_xfer_msg()
297 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { in i2c_dw_xfer_msg()
299 buf = msgs[dev->msg_write_idx].buf; in i2c_dw_xfer_msg()
300 buf_len = msgs[dev->msg_write_idx].len; in i2c_dw_xfer_msg()
306 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) && in i2c_dw_xfer_msg()
307 (dev->msg_write_idx > 0)) in i2c_dw_xfer_msg()
311 regmap_read(dev->map, DW_IC_TXFLR, &flr); in i2c_dw_xfer_msg()
312 tx_limit = dev->tx_fifo_depth - flr; in i2c_dw_xfer_msg()
314 regmap_read(dev->map, DW_IC_RXFLR, &flr); in i2c_dw_xfer_msg()
315 rx_limit = dev->rx_fifo_depth - flr; in i2c_dw_xfer_msg()
328 * i2c-core always sets the buffer length of in i2c_dw_xfer_msg()
333 if (dev->msg_write_idx == dev->msgs_num - 1 && in i2c_dw_xfer_msg()
342 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { in i2c_dw_xfer_msg()
345 if (dev->rx_outstanding >= dev->rx_fifo_depth) in i2c_dw_xfer_msg()
348 regmap_write(dev->map, DW_IC_DATA_CMD, in i2c_dw_xfer_msg()
350 rx_limit--; in i2c_dw_xfer_msg()
351 dev->rx_outstanding++; in i2c_dw_xfer_msg()
353 regmap_write(dev->map, DW_IC_DATA_CMD, in i2c_dw_xfer_msg()
356 tx_limit--; buf_len--; in i2c_dw_xfer_msg()
359 dev->tx_buf = buf; in i2c_dw_xfer_msg()
360 dev->tx_buf_len = buf_len; in i2c_dw_xfer_msg()
369 dev->status |= STATUS_WRITE_IN_PROGRESS; in i2c_dw_xfer_msg()
372 dev->status &= ~STATUS_WRITE_IN_PROGRESS; in i2c_dw_xfer_msg()
379 if (dev->msg_write_idx == dev->msgs_num) in i2c_dw_xfer_msg()
382 if (dev->msg_err) in i2c_dw_xfer_msg()
385 regmap_write(dev->map, DW_IC_INTR_MASK, intr_mask); in i2c_dw_xfer_msg()
391 struct i2c_msg *msgs = dev->msgs; in i2c_dw_recv_len()
392 u32 flags = msgs[dev->msg_read_idx].flags; in i2c_dw_recv_len()
399 dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding); in i2c_dw_recv_len()
400 msgs[dev->msg_read_idx].len = len; in i2c_dw_recv_len()
401 msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN; in i2c_dw_recv_len()
409 struct i2c_msg *msgs = dev->msgs; in i2c_dw_read()
412 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { in i2c_dw_read()
416 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) in i2c_dw_read()
419 if (!(dev->status & STATUS_READ_IN_PROGRESS)) { in i2c_dw_read()
420 len = msgs[dev->msg_read_idx].len; in i2c_dw_read()
421 buf = msgs[dev->msg_read_idx].buf; in i2c_dw_read()
423 len = dev->rx_buf_len; in i2c_dw_read()
424 buf = dev->rx_buf; in i2c_dw_read()
427 regmap_read(dev->map, DW_IC_RXFLR, &rx_valid); in i2c_dw_read()
429 for (; len > 0 && rx_valid > 0; len--, rx_valid--) { in i2c_dw_read()
430 u32 flags = msgs[dev->msg_read_idx].flags; in i2c_dw_read()
432 regmap_read(dev->map, DW_IC_DATA_CMD, &tmp); in i2c_dw_read()
439 dev->rx_outstanding--; in i2c_dw_read()
443 dev->status |= STATUS_READ_IN_PROGRESS; in i2c_dw_read()
444 dev->rx_buf_len = len; in i2c_dw_read()
445 dev->rx_buf = buf; in i2c_dw_read()
448 dev->status &= ~STATUS_READ_IN_PROGRESS; in i2c_dw_read()
461 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); in i2c_dw_xfer()
463 pm_runtime_get_sync(dev->dev); in i2c_dw_xfer()
465 if (dev_WARN_ONCE(dev->dev, dev->suspended, "Transfer while suspended\n")) { in i2c_dw_xfer()
466 ret = -ESHUTDOWN; in i2c_dw_xfer()
470 reinit_completion(&dev->cmd_complete); in i2c_dw_xfer()
471 dev->msgs = msgs; in i2c_dw_xfer()
472 dev->msgs_num = num; in i2c_dw_xfer()
473 dev->cmd_err = 0; in i2c_dw_xfer()
474 dev->msg_write_idx = 0; in i2c_dw_xfer()
475 dev->msg_read_idx = 0; in i2c_dw_xfer()
476 dev->msg_err = 0; in i2c_dw_xfer()
477 dev->status = STATUS_IDLE; in i2c_dw_xfer()
478 dev->abort_source = 0; in i2c_dw_xfer()
479 dev->rx_outstanding = 0; in i2c_dw_xfer()
493 if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) { in i2c_dw_xfer()
494 dev_err(dev->dev, "controller timed out\n"); in i2c_dw_xfer()
496 i2c_recover_bus(&dev->adapter); in i2c_dw_xfer()
498 ret = -ETIMEDOUT; in i2c_dw_xfer()
512 if (dev->msg_err) { in i2c_dw_xfer()
513 ret = dev->msg_err; in i2c_dw_xfer()
518 if (likely(!dev->cmd_err && !dev->status)) { in i2c_dw_xfer()
524 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { in i2c_dw_xfer()
529 if (dev->status) in i2c_dw_xfer()
530 dev_err(dev->dev, in i2c_dw_xfer()
531 "transfer terminated early - interrupt latency too high?\n"); in i2c_dw_xfer()
533 ret = -EIO; in i2c_dw_xfer()
539 pm_runtime_mark_last_busy(dev->dev); in i2c_dw_xfer()
540 pm_runtime_put_autosuspend(dev->dev); in i2c_dw_xfer()
570 regmap_read(dev->map, DW_IC_INTR_STAT, &stat); in i2c_dw_read_clear_intrbits()
577 * Instead, use the separately-prepared IC_CLR_* registers. in i2c_dw_read_clear_intrbits()
580 regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy); in i2c_dw_read_clear_intrbits()
582 regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy); in i2c_dw_read_clear_intrbits()
584 regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy); in i2c_dw_read_clear_intrbits()
586 regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy); in i2c_dw_read_clear_intrbits()
592 regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source); in i2c_dw_read_clear_intrbits()
593 regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy); in i2c_dw_read_clear_intrbits()
596 regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy); in i2c_dw_read_clear_intrbits()
598 regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy); in i2c_dw_read_clear_intrbits()
600 regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy); in i2c_dw_read_clear_intrbits()
602 regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy); in i2c_dw_read_clear_intrbits()
604 regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy); in i2c_dw_read_clear_intrbits()
610 * Interrupt service routine. This gets called whenever an I2C master interrupt
619 dev->cmd_err |= DW_IC_ERR_TX_ABRT; in i2c_dw_irq_handler_master()
620 dev->status = STATUS_IDLE; in i2c_dw_irq_handler_master()
626 regmap_write(dev->map, DW_IC_INTR_MASK, 0); in i2c_dw_irq_handler_master()
643 if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) in i2c_dw_irq_handler_master()
644 complete(&dev->cmd_complete); in i2c_dw_irq_handler_master()
645 else if (unlikely(dev->flags & ACCESS_INTR_MASK)) { in i2c_dw_irq_handler_master()
647 regmap_read(dev->map, DW_IC_INTR_MASK, &stat); in i2c_dw_irq_handler_master()
649 regmap_write(dev->map, DW_IC_INTR_MASK, stat); in i2c_dw_irq_handler_master()
660 regmap_read(dev->map, DW_IC_ENABLE, &enabled); in i2c_dw_isr()
661 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat); in i2c_dw_isr()
662 dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat); in i2c_dw_isr()
673 struct i2c_timings *t = &dev->timings; in i2c_dw_configure_master()
675 dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY; in i2c_dw_configure_master()
677 dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | in i2c_dw_configure_master()
680 dev->mode = DW_IC_MASTER; in i2c_dw_configure_master()
682 switch (t->bus_freq_hz) { in i2c_dw_configure_master()
684 dev->master_cfg |= DW_IC_CON_SPEED_STD; in i2c_dw_configure_master()
687 dev->master_cfg |= DW_IC_CON_SPEED_HIGH; in i2c_dw_configure_master()
690 dev->master_cfg |= DW_IC_CON_SPEED_FAST; in i2c_dw_configure_master()
700 reset_control_assert(dev->rst); in i2c_dw_prepare_recovery()
709 reset_control_deassert(dev->rst); in i2c_dw_unprepare_recovery()
715 struct i2c_bus_recovery_info *rinfo = &dev->rinfo; in i2c_dw_init_recovery_info()
716 struct i2c_adapter *adap = &dev->adapter; in i2c_dw_init_recovery_info()
719 gpio = devm_gpiod_get_optional(dev->dev, "scl", GPIOD_OUT_HIGH); in i2c_dw_init_recovery_info()
723 rinfo->scl_gpiod = gpio; in i2c_dw_init_recovery_info()
725 gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN); in i2c_dw_init_recovery_info()
728 rinfo->sda_gpiod = gpio; in i2c_dw_init_recovery_info()
730 rinfo->recover_bus = i2c_generic_scl_recovery; in i2c_dw_init_recovery_info()
731 rinfo->prepare_recovery = i2c_dw_prepare_recovery; in i2c_dw_init_recovery_info()
732 rinfo->unprepare_recovery = i2c_dw_unprepare_recovery; in i2c_dw_init_recovery_info()
733 adap->bus_recovery_info = rinfo; in i2c_dw_init_recovery_info()
735 dev_info(dev->dev, "running with gpio recovery mode! scl%s", in i2c_dw_init_recovery_info()
736 rinfo->sda_gpiod ? ",sda" : ""); in i2c_dw_init_recovery_info()
743 struct i2c_adapter *adap = &dev->adapter; in i2c_dw_probe_master()
747 init_completion(&dev->cmd_complete); in i2c_dw_probe_master()
749 dev->init = i2c_dw_init_master; in i2c_dw_probe_master()
750 dev->disable = i2c_dw_disable; in i2c_dw_probe_master()
751 dev->disable_int = i2c_dw_disable_int; in i2c_dw_probe_master()
765 ret = dev->init(dev); in i2c_dw_probe_master()
769 snprintf(adap->name, sizeof(adap->name), in i2c_dw_probe_master()
770 "Synopsys DesignWare I2C adapter"); in i2c_dw_probe_master()
771 adap->retries = 3; in i2c_dw_probe_master()
772 adap->algo = &i2c_dw_algo; in i2c_dw_probe_master()
773 adap->quirks = &i2c_dw_quirks; in i2c_dw_probe_master()
774 adap->dev.parent = dev->dev; in i2c_dw_probe_master()
777 if (dev->flags & ACCESS_NO_IRQ_SUSPEND) { in i2c_dw_probe_master()
784 ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags, in i2c_dw_probe_master()
785 dev_name(dev->dev), dev); in i2c_dw_probe_master()
787 dev_err(dev->dev, "failure requesting irq %i: %d\n", in i2c_dw_probe_master()
788 dev->irq, ret); in i2c_dw_probe_master()
800 * registered I2C slaves that do I2C transfers in their probe. in i2c_dw_probe_master()
802 pm_runtime_get_noresume(dev->dev); in i2c_dw_probe_master()
805 dev_err(dev->dev, "failure adding adapter: %d\n", ret); in i2c_dw_probe_master()
806 pm_runtime_put_noidle(dev->dev); in i2c_dw_probe_master()
812 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter");