Lines Matching +full:0 +full:xf00
16 * Coresight management registers (0xf00-0xfcc)
17 * 0xfa0 - 0xfa4: Management registers in PFTv1.0
20 #define CORESIGHT_ITCTRL 0xf00
21 #define CORESIGHT_CLAIMSET 0xfa0
22 #define CORESIGHT_CLAIMCLR 0xfa4
23 #define CORESIGHT_LAR 0xfb0
24 #define CORESIGHT_LSR 0xfb4
25 #define CORESIGHT_DEVARCH 0xfbc
26 #define CORESIGHT_AUTHSTATUS 0xfb8
27 #define CORESIGHT_DEVID 0xfc8
28 #define CORESIGHT_DEVTYPE 0xfcc
58 return scnprintf(buf, PAGE_SIZE, "0x%llx\n", val); \
115 writel_relaxed(0x0, addr + CORESIGHT_LAR); in CS_LOCK()
116 } while (0); in CS_LOCK()
125 } while (0); in CS_UNLOCK()
134 val |= (hi_offset < 0) ? 0 : in coresight_read_reg_pair()
143 if (hi_offset >= 0) in coresight_write_reg_pair()
172 static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; } in etm_readl_cp14()
173 static inline int etm_writel_cp14(u32 off, u32 val) { return 0; } in etm_writel_cp14()
193 .mask = 0x000fffff, \
200 .mask = 0x000fffff, \
211 .mask = 0x000fffff, \