Lines Matching full:trace

13 	  and trace drivers to register themselves with. It's intended to build
16 	  trace source gets enabled.
26 	  responsible for transporting and collecting the trace data
27 	  respectively.  Link and sinks are dynamically aggregated with a trace
28 	  entity at run time to form a complete trace path.
38 	  This enables support for the Trace Memory Controller driver.
40 	  trace router - ETR) or sink (embedded trace FIFO).  The driver
53 	   lookup. CATU helps TMC ETR to use a large physically non-contiguous trace
65 	  This enables support for the Trace Port Interface Unit driver,
67 	  components and a trace for bridging the gap between the on-chip
68 	  coresight components and a trace port collection engine, typically
79 	  This enables support for the Embedded Trace Buffer version 1.0 driver
87 	tristate "CoreSight Embedded Trace Macrocell 3.x driver"
100 	tristate "CoreSight Embedded Trace Macrocell 4.x driver"
114 	tristate "CoreSight System Trace Macrocell driver"
138 	  properly, please refer Documentation/trace/coresight/coresight-cpu-debug.rst
149 	  These provide hardware triggering events between CoreSight trace
150 	  source and sink components. These can be used to halt trace or
151 	  inject events into the trace stream. CTI also provides a software
152 	  control to trigger the same halt events. This can provide fast trace