123 	struct zx_vou_hw *vou;  member
220 	return zcrtc->vou;  in crtc_to_vou()
227 	struct zx_vou_hw *vou = zcrtc->vou;  in vou_inf_hdmi_audio_sel()  local
229 	zx_writel_mask(vou->vouctl + VOU_INF_HDMI_CTRL, VOU_HDMI_AUD_MASK, aud);  in vou_inf_hdmi_audio_sel()
235 	struct zx_vou_hw *vou = zcrtc->vou;  in vou_inf_enable()  local
258 	zx_writel_mask(vou->vouctl + VOU_INF_DATA_SEL, 0x3 << data_sel_shift,  in vou_inf_enable()
262 	zx_writel_mask(vou->vouctl + VOU_INF_CH_SEL, 0x1 << id,  in vou_inf_enable()
266 	zx_writel_mask(vou->vouctl + VOU_CLK_SEL, inf->clocks_sel_bits,  in vou_inf_enable()
270 	zx_writel_mask(vou->vouctl + VOU_CLK_EN, inf->clocks_en_bits,  in vou_inf_enable()
274 	zx_writel_mask(vou->vouctl + VOU_INF_EN, 1 << id, 1 << id);  in vou_inf_enable()
279 	struct zx_vou_hw *vou = crtc_to_vou(crtc);  in vou_inf_disable()  local
283 	zx_writel_mask(vou->vouctl + VOU_INF_EN, 1 << id, 0);  in vou_inf_disable()
286 	zx_writel_mask(vou->vouctl + VOU_CLK_EN, inf->clocks_en_bits, 0);  in vou_inf_disable()
293 	struct zx_vou_hw *vou = zcrtc->vou;  in zx_vou_config_dividers()  local
298 	zx_writel_mask(vou->vouctl + VOU_DIV_PARA, DIV_PARA_UPDATE, 0);  in zx_vou_config_dividers()
338 		zx_writel_mask(vou->vouctl + reg, 0x7 << shift,  in zx_vou_config_dividers()
343 	zx_writel_mask(vou->vouctl + VOU_DIV_PARA, DIV_PARA_UPDATE,  in zx_vou_config_dividers()
358 	struct zx_vou_hw *vou = zcrtc->vou;  in zx_crtc_atomic_enable()  local
372 	zx_writel(vou->timing + regs->fir_active, val);  in zx_crtc_atomic_enable()
377 	zx_writel(vou->timing + regs->fir_htiming, val);  in zx_crtc_atomic_enable()
382 	zx_writel(vou->timing + regs->fir_vtiming, val);  in zx_crtc_atomic_enable()
388 		val = zx_readl(vou->timing + SEC_V_ACTIVE);  in zx_crtc_atomic_enable()
391 		zx_writel(vou->timing + SEC_V_ACTIVE, val);  in zx_crtc_atomic_enable()
400 		zx_writel(vou->timing + regs->sec_vtiming, val);  in zx_crtc_atomic_enable()
409 	zx_writel_mask(vou->timing + TIMING_CTRL, bits->polarity_mask,  in zx_crtc_atomic_enable()
416 	zx_writel(vou->timing + regs->timing_shift, val);  in zx_crtc_atomic_enable()
417 	zx_writel(vou->timing + regs->timing_pi_shift, H_PI_SHIFT_VAL);  in zx_crtc_atomic_enable()
421 	zx_writel_mask(vou->timing + SCAN_CTRL, scan_mask,  in zx_crtc_atomic_enable()
425 	zx_writel_mask(vou->timing + TIMING_TC_ENABLE, bits->tc_enable,  in zx_crtc_atomic_enable()
448 		DRM_DEV_ERROR(vou->dev, "failed to set pixclk rate: %d\n", ret);  in zx_crtc_atomic_enable()
454 		DRM_DEV_ERROR(vou->dev, "failed to enable pixclk: %d\n", ret);  in zx_crtc_atomic_enable()
462 	struct zx_vou_hw *vou = zcrtc->vou;  in zx_crtc_atomic_disable()  local
472 	zx_writel_mask(vou->timing + TIMING_TC_ENABLE, bits->tc_enable, 0);  in zx_crtc_atomic_disable()
502 	struct zx_vou_hw *vou = crtc_to_vou(crtc);  in zx_vou_enable_vblank()  local
505 	zx_writel_mask(vou->timing + TIMING_INT_CTRL, int_frame_mask,  in zx_vou_enable_vblank()
514 	struct zx_vou_hw *vou = crtc_to_vou(crtc);  in zx_vou_disable_vblank()  local
516 	zx_writel_mask(vou->timing + TIMING_INT_CTRL,  in zx_vou_disable_vblank()
531 static int zx_crtc_init(struct drm_device *drm, struct zx_vou_hw *vou,  in zx_crtc_init()  argument
534 	struct device *dev = vou->dev;  in zx_crtc_init()
543 	zcrtc->vou = vou;  in zx_crtc_init()
553 		zplane->layer = vou->osd + MAIN_GL_OFFSET;  in zx_crtc_init()
554 		zplane->csc = vou->osd + MAIN_GL_CSC_OFFSET;  in zx_crtc_init()
555 		zplane->hbsc = vou->osd + MAIN_HBSC_OFFSET;  in zx_crtc_init()
556 		zplane->rsz = vou->otfppu + MAIN_RSZ_OFFSET;  in zx_crtc_init()
558 		zcrtc->chnreg = vou->osd + OSD_MAIN_CHN;  in zx_crtc_init()
559 		zcrtc->chncsc = vou->osd + MAIN_CHN_CSC_OFFSET;  in zx_crtc_init()
560 		zcrtc->dither = vou->osd + MAIN_DITHER_OFFSET;  in zx_crtc_init()
564 		zplane->layer = vou->osd + AUX_GL_OFFSET;  in zx_crtc_init()
565 		zplane->csc = vou->osd + AUX_GL_CSC_OFFSET;  in zx_crtc_init()
566 		zplane->hbsc = vou->osd + AUX_HBSC_OFFSET;  in zx_crtc_init()
567 		zplane->rsz = vou->otfppu + AUX_RSZ_OFFSET;  in zx_crtc_init()
569 		zcrtc->chnreg = vou->osd + OSD_AUX_CHN;  in zx_crtc_init()
570 		zcrtc->chncsc = vou->osd + AUX_CHN_CSC_OFFSET;  in zx_crtc_init()
571 		zcrtc->dither = vou->osd + AUX_DITHER_OFFSET;  in zx_crtc_init()
602 		vou->main_crtc = zcrtc;  in zx_crtc_init()
604 		vou->aux_crtc = zcrtc;  in zx_crtc_init()
612 	struct zx_vou_hw *vou = zcrtc->vou;  in zx_vou_layer_enable()  local
617 		zx_writel_mask(vou->osd + OSD_CTRL0, bits->chnsel, 0);  in zx_vou_layer_enable()
618 		zx_writel_mask(vou->vouctl + VOU_CLK_SEL, bits->clksel, 0);  in zx_vou_layer_enable()
620 		zx_writel_mask(vou->osd + OSD_CTRL0, bits->chnsel,  in zx_vou_layer_enable()
622 		zx_writel_mask(vou->vouctl + VOU_CLK_SEL, bits->clksel,  in zx_vou_layer_enable()
626 	zx_writel_mask(vou->osd + OSD_CTRL0, bits->enable, bits->enable);  in zx_vou_layer_enable()
633 	struct zx_vou_hw *vou = zcrtc->vou;  in zx_vou_layer_disable()  local
637 	zx_writel_mask(vou->osd + OSD_CTRL0, bits->enable, 0);  in zx_vou_layer_disable()
640 static void zx_overlay_init(struct drm_device *drm, struct zx_vou_hw *vou)  in zx_overlay_init()  argument
642 	struct device *dev = vou->dev;  in zx_overlay_init()
658 		zplane->layer = vou->osd + OSD_VL_OFFSET(i);  in zx_overlay_init()
659 		zplane->hbsc = vou->osd + HBSC_VL_OFFSET(i);  in zx_overlay_init()
660 		zplane->rsz = vou->otfppu + RSZ_VL_OFFSET(i);  in zx_overlay_init()
684 	struct zx_vou_hw *vou = dev_id;  in vou_irq_handler()  local
688 	state = zx_readl(vou->timing + TIMING_INT_STATE);  in vou_irq_handler()
689 	zx_writel(vou->timing + TIMING_INT_STATE, state);  in vou_irq_handler()
692 		drm_crtc_handle_vblank(&vou->main_crtc->crtc);  in vou_irq_handler()
695 		drm_crtc_handle_vblank(&vou->aux_crtc->crtc);  in vou_irq_handler()
698 	state = zx_readl(vou->osd + OSD_INT_STA);  in vou_irq_handler()
699 	zx_writel(vou->osd + OSD_INT_CLRSTA, state);  in vou_irq_handler()
702 		zx_osd_int_update(vou->main_crtc);  in vou_irq_handler()
705 		zx_osd_int_update(vou->aux_crtc);  in vou_irq_handler()
708 		DRM_DEV_ERROR(vou->dev, "OSD ERROR: 0x%08x!\n", state);  in vou_irq_handler()
713 static void vou_dtrc_init(struct zx_vou_hw *vou)  in vou_dtrc_init()  argument
716 	zx_writel_mask(vou->dtrc + DTRC_DETILE_CTRL,  in vou_dtrc_init()
720 	zx_writel_mask(vou->dtrc + DTRC_DETILE_CTRL, DETILE_ARIDR_MODE_MASK,  in vou_dtrc_init()
724 	zx_writel_mask(vou->dtrc + DTRC_F0_CTRL, DTRC_DECOMPRESS_BYPASS,  in vou_dtrc_init()
726 	zx_writel_mask(vou->dtrc + DTRC_F1_CTRL, DTRC_DECOMPRESS_BYPASS,  in vou_dtrc_init()
730 	zx_writel(vou->dtrc + DTRC_ARID, DTRC_ARID3(0xf) | DTRC_ARID2(0xe) |  in vou_dtrc_init()
734 static void vou_hw_init(struct zx_vou_hw *vou)  in vou_hw_init()  argument
737 	zx_writel(vou->vouctl + VOU_SOFT_RST, ~0);  in vou_hw_init()
740 	zx_writel(vou->vouctl + VOU_CLK_EN, ~0);  in vou_hw_init()
743 	zx_writel(vou->osd + OSD_INT_CLRSTA, ~0);  in vou_hw_init()
744 	zx_writel(vou->timing + TIMING_INT_STATE, ~0);  in vou_hw_init()
747 	zx_writel(vou->osd + OSD_INT_MSK, OSD_INT_ENABLE);  in vou_hw_init()
748 	zx_writel(vou->timing + TIMING_INT_CTRL, TIMING_INT_ENABLE);  in vou_hw_init()
751 	zx_writel(vou->otfppu + OTFPPU_RSZ_DATA_SOURCE, 0x2a);  in vou_hw_init()
757 	zx_writel_mask(vou->osd + OSD_RST_CLR, RST_PER_FRAME, RST_PER_FRAME);  in vou_hw_init()
759 	vou_dtrc_init(vou);  in vou_hw_init()
766 	struct zx_vou_hw *vou;  in zx_crtc_bind()  local
771 	vou = devm_kzalloc(dev, sizeof(*vou), GFP_KERNEL);  in zx_crtc_bind()
772 	if (!vou)  in zx_crtc_bind()
776 	vou->osd = devm_ioremap_resource(dev, res);  in zx_crtc_bind()
777 	if (IS_ERR(vou->osd)) {  in zx_crtc_bind()
778 		ret = PTR_ERR(vou->osd);  in zx_crtc_bind()
784 	vou->timing = devm_ioremap_resource(dev, res);  in zx_crtc_bind()
785 	if (IS_ERR(vou->timing)) {  in zx_crtc_bind()
786 		ret = PTR_ERR(vou->timing);  in zx_crtc_bind()
793 	vou->dtrc = devm_ioremap_resource(dev, res);  in zx_crtc_bind()
794 	if (IS_ERR(vou->dtrc)) {  in zx_crtc_bind()
795 		ret = PTR_ERR(vou->dtrc);  in zx_crtc_bind()
801 	vou->vouctl = devm_ioremap_resource(dev, res);  in zx_crtc_bind()
802 	if (IS_ERR(vou->vouctl)) {  in zx_crtc_bind()
803 		ret = PTR_ERR(vou->vouctl);  in zx_crtc_bind()
810 	vou->otfppu = devm_ioremap_resource(dev, res);  in zx_crtc_bind()
811 	if (IS_ERR(vou->otfppu)) {  in zx_crtc_bind()
812 		ret = PTR_ERR(vou->otfppu);  in zx_crtc_bind()
821 	vou->axi_clk = devm_clk_get(dev, "aclk");  in zx_crtc_bind()
822 	if (IS_ERR(vou->axi_clk)) {  in zx_crtc_bind()
823 		ret = PTR_ERR(vou->axi_clk);  in zx_crtc_bind()
828 	vou->ppu_clk = devm_clk_get(dev, "ppu_wclk");  in zx_crtc_bind()
829 	if (IS_ERR(vou->ppu_clk)) {  in zx_crtc_bind()
830 		ret = PTR_ERR(vou->ppu_clk);  in zx_crtc_bind()
835 	ret = clk_prepare_enable(vou->axi_clk);  in zx_crtc_bind()
841 	clk_prepare_enable(vou->ppu_clk);  in zx_crtc_bind()
847 	vou->dev = dev;  in zx_crtc_bind()
848 	dev_set_drvdata(dev, vou);  in zx_crtc_bind()
850 	vou_hw_init(vou);  in zx_crtc_bind()
852 	ret = devm_request_irq(dev, irq, vou_irq_handler, 0, "zx_vou", vou);  in zx_crtc_bind()
858 	ret = zx_crtc_init(drm, vou, VOU_CHN_MAIN);  in zx_crtc_bind()
865 	ret = zx_crtc_init(drm, vou, VOU_CHN_AUX);  in zx_crtc_bind()
872 	zx_overlay_init(drm, vou);  in zx_crtc_bind()
877 	clk_disable_unprepare(vou->ppu_clk);  in zx_crtc_bind()
879 	clk_disable_unprepare(vou->axi_clk);  in zx_crtc_bind()
886 	struct zx_vou_hw *vou = dev_get_drvdata(dev);  in zx_crtc_unbind()  local
888 	clk_disable_unprepare(vou->axi_clk);  in zx_crtc_unbind()
889 	clk_disable_unprepare(vou->ppu_clk);  in zx_crtc_unbind()