171 	void __iomem *osd;  member
553 		zplane->layer = vou->osd + MAIN_GL_OFFSET;  in zx_crtc_init()
554 		zplane->csc = vou->osd + MAIN_GL_CSC_OFFSET;  in zx_crtc_init()
555 		zplane->hbsc = vou->osd + MAIN_HBSC_OFFSET;  in zx_crtc_init()
558 		zcrtc->chnreg = vou->osd + OSD_MAIN_CHN;  in zx_crtc_init()
559 		zcrtc->chncsc = vou->osd + MAIN_CHN_CSC_OFFSET;  in zx_crtc_init()
560 		zcrtc->dither = vou->osd + MAIN_DITHER_OFFSET;  in zx_crtc_init()
564 		zplane->layer = vou->osd + AUX_GL_OFFSET;  in zx_crtc_init()
565 		zplane->csc = vou->osd + AUX_GL_CSC_OFFSET;  in zx_crtc_init()
566 		zplane->hbsc = vou->osd + AUX_HBSC_OFFSET;  in zx_crtc_init()
569 		zcrtc->chnreg = vou->osd + OSD_AUX_CHN;  in zx_crtc_init()
570 		zcrtc->chncsc = vou->osd + AUX_CHN_CSC_OFFSET;  in zx_crtc_init()
571 		zcrtc->dither = vou->osd + AUX_DITHER_OFFSET;  in zx_crtc_init()
617 		zx_writel_mask(vou->osd + OSD_CTRL0, bits->chnsel, 0);  in zx_vou_layer_enable()
620 		zx_writel_mask(vou->osd + OSD_CTRL0, bits->chnsel,  in zx_vou_layer_enable()
626 	zx_writel_mask(vou->osd + OSD_CTRL0, bits->enable, bits->enable);  in zx_vou_layer_enable()
637 	zx_writel_mask(vou->osd + OSD_CTRL0, bits->enable, 0);  in zx_vou_layer_disable()
658 		zplane->layer = vou->osd + OSD_VL_OFFSET(i);  in zx_overlay_init()
659 		zplane->hbsc = vou->osd + HBSC_VL_OFFSET(i);  in zx_overlay_init()
698 	state = zx_readl(vou->osd + OSD_INT_STA);  in vou_irq_handler()
699 	zx_writel(vou->osd + OSD_INT_CLRSTA, state);  in vou_irq_handler()
743 	zx_writel(vou->osd + OSD_INT_CLRSTA, ~0);  in vou_hw_init()
747 	zx_writel(vou->osd + OSD_INT_MSK, OSD_INT_ENABLE);  in vou_hw_init()
757 	zx_writel_mask(vou->osd + OSD_RST_CLR, RST_PER_FRAME, RST_PER_FRAME);  in vou_hw_init()
776 	vou->osd = devm_ioremap_resource(dev, res);  in zx_crtc_bind()
777 	if (IS_ERR(vou->osd)) {  in zx_crtc_bind()
778 		ret = PTR_ERR(vou->osd);  in zx_crtc_bind()