Lines Matching +full:3 +full:- +full:channel

1 /* via_dmablit.h -- PCI DMA BitBlt support for the VIA Unichrome/Pro
19  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
33 #include <linux/dma-mapping.h>
84  *  Channels 2 & 3 don't seem to be implemented in hardware.
87 #define VIA_PCI_DMA_MAR0            0xE40   /* Memory Address Register of Channel 0 */
88 #define VIA_PCI_DMA_DAR0            0xE44   /* Device Address Register of Channel 0 */
89 #define VIA_PCI_DMA_BCR0            0xE48   /* Byte Count Register of Channel 0 */
90 #define VIA_PCI_DMA_DPR0            0xE4C   /* Descriptor Pointer Register of Channel 0 */
92 #define VIA_PCI_DMA_MAR1            0xE50   /* Memory Address Register of Channel 1 */
93 #define VIA_PCI_DMA_DAR1            0xE54   /* Device Address Register of Channel 1 */
94 #define VIA_PCI_DMA_BCR1            0xE58   /* Byte Count Register of Channel 1 */
95 #define VIA_PCI_DMA_DPR1            0xE5C   /* Descriptor Pointer Register of Channel 1 */
97 #define VIA_PCI_DMA_MAR2            0xE60   /* Memory Address Register of Channel 2 */
98 #define VIA_PCI_DMA_DAR2            0xE64   /* Device Address Register of Channel 2 */
99 #define VIA_PCI_DMA_BCR2            0xE68   /* Byte Count Register of Channel 2 */
100 #define VIA_PCI_DMA_DPR2            0xE6C   /* Descriptor Pointer Register of Channel 2 */
102 #define VIA_PCI_DMA_MAR3            0xE70   /* Memory Address Register of Channel 3 */
103 #define VIA_PCI_DMA_DAR3            0xE74   /* Device Address Register of Channel 3 */
104 #define VIA_PCI_DMA_BCR3            0xE78   /* Byte Count Register of Channel 3 */
105 #define VIA_PCI_DMA_DPR3            0xE7C   /* Descriptor Pointer Register of Channel 3 */
107 #define VIA_PCI_DMA_MR0             0xE80   /* Mode Register of Channel 0 */
108 #define VIA_PCI_DMA_MR1             0xE84   /* Mode Register of Channel 1 */
109 #define VIA_PCI_DMA_MR2             0xE88   /* Mode Register of Channel 2 */
110 #define VIA_PCI_DMA_MR3             0xE8C   /* Mode Register of Channel 3 */
112 #define VIA_PCI_DMA_CSR0            0xE90   /* Command/Status Register of Channel 0 */
113 #define VIA_PCI_DMA_CSR1            0xE94   /* Command/Status Register of Channel 1 */
114 #define VIA_PCI_DMA_CSR2            0xE98   /* Command/Status Register of Channel 2 */
115 #define VIA_PCI_DMA_CSR3            0xE9C   /* Command/Status Register of Channel 3 */
123 #define VIA_DMA_DPR_DT		(1<<3)	/* direction of transfer (RO) */
134 #define VIA_DMA_CSR_TD		(1<<3)	/* transfer done */