31  * (reading it as a texture, uniform data, or direct-addressed TMU
37  * uniform stream.
62 	 * one argument being a uniform, the address of the uniform.
73 	 * Used for validation that the uniform stream is updated at the right
78 	/* Set when entering a basic block, and cleared when the uniform
241 			DRM_DEBUG("direct TMU load didn't add to a uniform\n");  in check_tmu_write()
249 			DRM_DEBUG("uniform read in the same instruction as "  in check_tmu_write()
263 	/* Since direct uses a RADDR uniform reference, it will get counted in  in check_tmu_write()
268 			DRM_DEBUG("Texturing with undefined uniform address\n");  in check_tmu_write()
316 	/* We want our reset to be pointing at whatever uniform follows the  in validate_uniform_address_write()
321 	/* We only support absolute uniform address changes, and we  in validate_uniform_address_write()
323 	 * of its uniform reads.  in validate_uniform_address_write()
326 	 * noticing that (say) an if statement does uniform control  in validate_uniform_address_write()
345 		DRM_DEBUG("Uniform address reset must be an ADD.\n");  in validate_uniform_address_write()
350 		DRM_DEBUG("Uniform address reset must be unconditional.\n");  in validate_uniform_address_write()
361 		DRM_DEBUG("First argument of uniform address write must be "  in validate_uniform_address_write()
375 		DRM_DEBUG("Second argument of uniform address write must be "  in validate_uniform_address_write()
376 			  "a uniform.\n");  in validate_uniform_address_write()
536 		 * a maximum of some uniform's offset.  in track_live_clamps()
617 			DRM_DEBUG("Uniform read with undefined uniform "  in check_instruction_reads()
769 	 * uniform to be loaded is a uniform address offset.  That uniform's  in vc4_handle_branch_target()
770 	 * offset will be marked by the uniform address register write  in vc4_handle_branch_target()