56 static inline void rcl_u8(struct vc4_rcl_setup *setup, u8 val)  in rcl_u8()  argument
58 	*(u8 *)(setup->rcl->vaddr + setup->next_offset) = val;  in rcl_u8()
59 	setup->next_offset += 1;  in rcl_u8()
62 static inline void rcl_u16(struct vc4_rcl_setup *setup, u16 val)  in rcl_u16()  argument
64 	*(u16 *)(setup->rcl->vaddr + setup->next_offset) = val;  in rcl_u16()
65 	setup->next_offset += 2;  in rcl_u16()
68 static inline void rcl_u32(struct vc4_rcl_setup *setup, u32 val)  in rcl_u32()  argument
70 	*(u32 *)(setup->rcl->vaddr + setup->next_offset) = val;  in rcl_u32()
71 	setup->next_offset += 4;  in rcl_u32()
80 static void vc4_store_before_load(struct vc4_rcl_setup *setup)  in vc4_store_before_load()  argument
82 	rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);  in vc4_store_before_load()
83 	rcl_u16(setup,  in vc4_store_before_load()
89 	rcl_u32(setup, 0); /* no address, since we're in None mode */  in vc4_store_before_load()
115 static void vc4_tile_coordinates(struct vc4_rcl_setup *setup,  in vc4_tile_coordinates()  argument
118 	rcl_u8(setup, VC4_PACKET_TILE_COORDINATES);  in vc4_tile_coordinates()
119 	rcl_u8(setup, x);  in vc4_tile_coordinates()
120 	rcl_u8(setup, y);  in vc4_tile_coordinates()
124 		      struct vc4_rcl_setup *setup,  in emit_tile()  argument
134 	if (setup->color_read) {  in emit_tile()
137 			rcl_u8(setup, VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER);  in emit_tile()
138 			rcl_u32(setup,  in emit_tile()
139 				vc4_full_res_offset(exec, setup->color_read,  in emit_tile()
143 			rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);  in emit_tile()
144 			rcl_u16(setup, args->color_read.bits);  in emit_tile()
145 			rcl_u32(setup, setup->color_read->paddr +  in emit_tile()
150 	if (setup->zs_read) {  in emit_tile()
151 		if (setup->color_read) {  in emit_tile()
153 			vc4_tile_coordinates(setup, x, y);  in emit_tile()
154 			vc4_store_before_load(setup);  in emit_tile()
159 			rcl_u8(setup, VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER);  in emit_tile()
160 			rcl_u32(setup,  in emit_tile()
161 				vc4_full_res_offset(exec, setup->zs_read,  in emit_tile()
165 			rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);  in emit_tile()
166 			rcl_u16(setup, args->zs_read.bits);  in emit_tile()
167 			rcl_u32(setup, setup->zs_read->paddr +  in emit_tile()
175 	vc4_tile_coordinates(setup, x, y);  in emit_tile()
181 		rcl_u8(setup, VC4_PACKET_WAIT_ON_SEMAPHORE);  in emit_tile()
184 		rcl_u8(setup, VC4_PACKET_BRANCH_TO_SUB_LIST);  in emit_tile()
185 		rcl_u32(setup, (exec->tile_alloc_offset +  in emit_tile()
189 	if (setup->msaa_color_write) {  in emit_tile()
190 		bool last_tile_write = (!setup->msaa_zs_write &&  in emit_tile()
191 					!setup->zs_write &&  in emit_tile()
192 					!setup->color_write);  in emit_tile()
199 		rcl_u8(setup, VC4_PACKET_STORE_FULL_RES_TILE_BUFFER);  in emit_tile()
200 		rcl_u32(setup,  in emit_tile()
201 			vc4_full_res_offset(exec, setup->msaa_color_write,  in emit_tile()
206 	if (setup->msaa_zs_write) {  in emit_tile()
207 		bool last_tile_write = (!setup->zs_write &&  in emit_tile()
208 					!setup->color_write);  in emit_tile()
211 		if (setup->msaa_color_write)  in emit_tile()
212 			vc4_tile_coordinates(setup, x, y);  in emit_tile()
217 		rcl_u8(setup, VC4_PACKET_STORE_FULL_RES_TILE_BUFFER);  in emit_tile()
218 		rcl_u32(setup,  in emit_tile()
219 			vc4_full_res_offset(exec, setup->msaa_zs_write,  in emit_tile()
224 	if (setup->zs_write) {  in emit_tile()
225 		bool last_tile_write = !setup->color_write;  in emit_tile()
227 		if (setup->msaa_color_write || setup->msaa_zs_write)  in emit_tile()
228 			vc4_tile_coordinates(setup, x, y);  in emit_tile()
230 		rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);  in emit_tile()
231 		rcl_u16(setup, args->zs_write.bits |  in emit_tile()
234 		rcl_u32(setup,  in emit_tile()
235 			(setup->zs_write->paddr + args->zs_write.offset) |  in emit_tile()
240 	if (setup->color_write) {  in emit_tile()
241 		if (setup->msaa_color_write || setup->msaa_zs_write ||  in emit_tile()
242 		    setup->zs_write) {  in emit_tile()
243 			vc4_tile_coordinates(setup, x, y);  in emit_tile()
247 			rcl_u8(setup, VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF);  in emit_tile()
249 			rcl_u8(setup, VC4_PACKET_STORE_MS_TILE_BUFFER);  in emit_tile()
254 			     struct vc4_rcl_setup *setup)  in vc4_create_rcl_bo()  argument
285 	if (setup->color_read) {  in vc4_create_rcl_bo()
293 	if (setup->zs_read) {  in vc4_create_rcl_bo()
294 		if (setup->color_read) {  in vc4_create_rcl_bo()
312 	if (setup->msaa_color_write)  in vc4_create_rcl_bo()
314 	if (setup->msaa_zs_write)  in vc4_create_rcl_bo()
317 	if (setup->zs_write)  in vc4_create_rcl_bo()
319 	if (setup->color_write)  in vc4_create_rcl_bo()
324 		((setup->msaa_color_write != NULL) +  in vc4_create_rcl_bo()
325 		 (setup->msaa_zs_write != NULL) +  in vc4_create_rcl_bo()
326 		 (setup->color_write != NULL) +  in vc4_create_rcl_bo()
327 		 (setup->zs_write != NULL) - 1);  in vc4_create_rcl_bo()
331 	setup->rcl = &vc4_bo_create(dev, size, true, VC4_BO_TYPE_RCL)->base;  in vc4_create_rcl_bo()
332 	if (IS_ERR(setup->rcl))  in vc4_create_rcl_bo()
333 		return PTR_ERR(setup->rcl);  in vc4_create_rcl_bo()
334 	list_add_tail(&to_vc4_bo(&setup->rcl->base)->unref_head,  in vc4_create_rcl_bo()
343 		rcl_u8(setup, VC4_PACKET_CLEAR_COLORS);  in vc4_create_rcl_bo()
344 		rcl_u32(setup, args->clear_color[0]);  in vc4_create_rcl_bo()
345 		rcl_u32(setup, args->clear_color[1]);  in vc4_create_rcl_bo()
346 		rcl_u32(setup, args->clear_z);  in vc4_create_rcl_bo()
347 		rcl_u8(setup, args->clear_s);  in vc4_create_rcl_bo()
349 		vc4_tile_coordinates(setup, 0, 0);  in vc4_create_rcl_bo()
351 		rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);  in vc4_create_rcl_bo()
352 		rcl_u16(setup, VC4_LOADSTORE_TILE_BUFFER_NONE);  in vc4_create_rcl_bo()
353 		rcl_u32(setup, 0); /* no address, since we're in None mode */  in vc4_create_rcl_bo()
356 	rcl_u8(setup, VC4_PACKET_TILE_RENDERING_MODE_CONFIG);  in vc4_create_rcl_bo()
357 	rcl_u32(setup,  in vc4_create_rcl_bo()
358 		(setup->color_write ? (setup->color_write->paddr +  in vc4_create_rcl_bo()
361 	rcl_u16(setup, args->width);  in vc4_create_rcl_bo()
362 	rcl_u16(setup, args->height);  in vc4_create_rcl_bo()
363 	rcl_u16(setup, args->color_write.bits);  in vc4_create_rcl_bo()
372 			emit_tile(exec, setup, x, y, first, last);  in vc4_create_rcl_bo()
376 	BUG_ON(setup->next_offset != size);  in vc4_create_rcl_bo()
377 	exec->ct1ca = setup->rcl->paddr;  in vc4_create_rcl_bo()
378 	exec->ct1ea = setup->rcl->paddr + setup->next_offset;  in vc4_create_rcl_bo()
535 				    struct vc4_rcl_setup *setup,  in vc4_rcl_render_config_surface_setup()  argument
596 	struct vc4_rcl_setup setup = {0};  in vc4_get_rcl()  local
619 	ret = vc4_rcl_render_config_surface_setup(exec, &setup,  in vc4_get_rcl()
620 						  &setup.color_write,  in vc4_get_rcl()
625 	ret = vc4_rcl_surface_setup(exec, &setup.color_read, &args->color_read,  in vc4_get_rcl()
630 	ret = vc4_rcl_surface_setup(exec, &setup.zs_read, &args->zs_read,  in vc4_get_rcl()
635 	ret = vc4_rcl_surface_setup(exec, &setup.zs_write, &args->zs_write,  in vc4_get_rcl()
640 	ret = vc4_rcl_msaa_surface_setup(exec, &setup.msaa_color_write,  in vc4_get_rcl()
645 	ret = vc4_rcl_msaa_surface_setup(exec, &setup.msaa_zs_write,  in vc4_get_rcl()
653 	if (!setup.color_write && !setup.zs_write &&  in vc4_get_rcl()
654 	    !setup.msaa_color_write && !setup.msaa_zs_write) {  in vc4_get_rcl()
659 	return vc4_create_rcl_bo(dev, exec, &setup);  in vc4_get_rcl()