Lines Matching +full:offset +full:- +full:y
2 * Copyright © 2014-2015 Broadcom
28 * tiles of a framebuffer and optionally call out to binner-generated
33 * user-submitted command list is hard to get right and has high CPU overhead,
58 *(u8 *)(setup->rcl->vaddr + setup->next_offset) = val; in rcl_u8()
59 setup->next_offset += 1; in rcl_u8()
64 *(u16 *)(setup->rcl->vaddr + setup->next_offset) = val; in rcl_u16()
65 setup->next_offset += 2; in rcl_u16()
70 *(u32 *)(setup->rcl->vaddr + setup->next_offset) = val; in rcl_u32()
71 setup->next_offset += 4; in rcl_u32()
75 * Emits a no-op STORE_TILE_BUFFER_GENERAL.
102 uint8_t x, uint8_t y) in vc4_full_res_offset() argument
104 return bo->paddr + surf->offset + VC4_TILE_BUFFER_SIZE * in vc4_full_res_offset()
105 (DIV_ROUND_UP(exec->args->width, 32) * y + x); in vc4_full_res_offset()
116 uint32_t x, uint32_t y) in vc4_tile_coordinates() argument
120 rcl_u8(setup, y); in vc4_tile_coordinates()
125 uint8_t x, uint8_t y, bool first, bool last) in emit_tile() argument
127 struct drm_vc4_submit_cl *args = exec->args; in emit_tile()
128 bool has_bin = args->bin_cl_size != 0; in emit_tile()
134 if (setup->color_read) { in emit_tile()
135 if (args->color_read.flags & in emit_tile()
139 vc4_full_res_offset(exec, setup->color_read, in emit_tile()
140 &args->color_read, x, y) | in emit_tile()
144 rcl_u16(setup, args->color_read.bits); in emit_tile()
145 rcl_u32(setup, setup->color_read->paddr + in emit_tile()
146 args->color_read.offset); in emit_tile()
150 if (setup->zs_read) { in emit_tile()
151 if (setup->color_read) { in emit_tile()
153 vc4_tile_coordinates(setup, x, y); in emit_tile()
157 if (args->zs_read.flags & in emit_tile()
161 vc4_full_res_offset(exec, setup->zs_read, in emit_tile()
162 &args->zs_read, x, y) | in emit_tile()
166 rcl_u16(setup, args->zs_read.bits); in emit_tile()
167 rcl_u32(setup, setup->zs_read->paddr + in emit_tile()
168 args->zs_read.offset); in emit_tile()
175 vc4_tile_coordinates(setup, x, y); in emit_tile()
185 rcl_u32(setup, (exec->tile_alloc_offset + in emit_tile()
186 (y * exec->bin_tiles_x + x) * 32)); in emit_tile()
189 if (setup->msaa_color_write) { in emit_tile()
190 bool last_tile_write = (!setup->msaa_zs_write && in emit_tile()
191 !setup->zs_write && in emit_tile()
192 !setup->color_write); in emit_tile()
201 vc4_full_res_offset(exec, setup->msaa_color_write, in emit_tile()
202 &args->msaa_color_write, x, y) | in emit_tile()
206 if (setup->msaa_zs_write) { in emit_tile()
207 bool last_tile_write = (!setup->zs_write && in emit_tile()
208 !setup->color_write); in emit_tile()
211 if (setup->msaa_color_write) in emit_tile()
212 vc4_tile_coordinates(setup, x, y); in emit_tile()
219 vc4_full_res_offset(exec, setup->msaa_zs_write, in emit_tile()
220 &args->msaa_zs_write, x, y) | in emit_tile()
224 if (setup->zs_write) { in emit_tile()
225 bool last_tile_write = !setup->color_write; in emit_tile()
227 if (setup->msaa_color_write || setup->msaa_zs_write) in emit_tile()
228 vc4_tile_coordinates(setup, x, y); in emit_tile()
231 rcl_u16(setup, args->zs_write.bits | in emit_tile()
235 (setup->zs_write->paddr + args->zs_write.offset) | in emit_tile()
240 if (setup->color_write) { in emit_tile()
241 if (setup->msaa_color_write || setup->msaa_zs_write || in emit_tile()
242 setup->zs_write) { in emit_tile()
243 vc4_tile_coordinates(setup, x, y); in emit_tile()
256 struct drm_vc4_submit_cl *args = exec->args; in vc4_create_rcl_bo()
257 bool has_bin = args->bin_cl_size != 0; in vc4_create_rcl_bo()
258 uint8_t min_x_tile = args->min_x_tile; in vc4_create_rcl_bo()
259 uint8_t min_y_tile = args->min_y_tile; in vc4_create_rcl_bo()
260 uint8_t max_x_tile = args->max_x_tile; in vc4_create_rcl_bo()
261 uint8_t max_y_tile = args->max_y_tile; in vc4_create_rcl_bo()
262 uint8_t xtiles = max_x_tile - min_x_tile + 1; in vc4_create_rcl_bo()
263 uint8_t ytiles = max_y_tile - min_y_tile + 1; in vc4_create_rcl_bo()
269 if (args->flags & VC4_SUBMIT_CL_FIXED_RCL_ORDER) { in vc4_create_rcl_bo()
270 if (!(args->flags & VC4_SUBMIT_CL_RCL_ORDER_INCREASING_X)) in vc4_create_rcl_bo()
272 if (!(args->flags & VC4_SUBMIT_CL_RCL_ORDER_INCREASING_Y)) in vc4_create_rcl_bo()
279 if (args->flags & VC4_SUBMIT_CL_USE_CLEAR_COLOR) { in vc4_create_rcl_bo()
285 if (setup->color_read) { in vc4_create_rcl_bo()
286 if (args->color_read.flags & in vc4_create_rcl_bo()
293 if (setup->zs_read) { in vc4_create_rcl_bo()
294 if (setup->color_read) { in vc4_create_rcl_bo()
299 if (args->zs_read.flags & in vc4_create_rcl_bo()
312 if (setup->msaa_color_write) in vc4_create_rcl_bo()
314 if (setup->msaa_zs_write) in vc4_create_rcl_bo()
317 if (setup->zs_write) in vc4_create_rcl_bo()
319 if (setup->color_write) in vc4_create_rcl_bo()
324 ((setup->msaa_color_write != NULL) + in vc4_create_rcl_bo()
325 (setup->msaa_zs_write != NULL) + in vc4_create_rcl_bo()
326 (setup->color_write != NULL) + in vc4_create_rcl_bo()
327 (setup->zs_write != NULL) - 1); in vc4_create_rcl_bo()
331 setup->rcl = &vc4_bo_create(dev, size, true, VC4_BO_TYPE_RCL)->base; in vc4_create_rcl_bo()
332 if (IS_ERR(setup->rcl)) in vc4_create_rcl_bo()
333 return PTR_ERR(setup->rcl); in vc4_create_rcl_bo()
334 list_add_tail(&to_vc4_bo(&setup->rcl->base)->unref_head, in vc4_create_rcl_bo()
335 &exec->unref_list); in vc4_create_rcl_bo()
342 if (args->flags & VC4_SUBMIT_CL_USE_CLEAR_COLOR) { in vc4_create_rcl_bo()
344 rcl_u32(setup, args->clear_color[0]); in vc4_create_rcl_bo()
345 rcl_u32(setup, args->clear_color[1]); in vc4_create_rcl_bo()
346 rcl_u32(setup, args->clear_z); in vc4_create_rcl_bo()
347 rcl_u8(setup, args->clear_s); in vc4_create_rcl_bo()
358 (setup->color_write ? (setup->color_write->paddr + in vc4_create_rcl_bo()
359 args->color_write.offset) : in vc4_create_rcl_bo()
361 rcl_u16(setup, args->width); in vc4_create_rcl_bo()
362 rcl_u16(setup, args->height); in vc4_create_rcl_bo()
363 rcl_u16(setup, args->color_write.bits); in vc4_create_rcl_bo()
366 int y = positive_y ? min_y_tile + yi : max_y_tile - yi; in vc4_create_rcl_bo() local
368 int x = positive_x ? min_x_tile + xi : max_x_tile - xi; in vc4_create_rcl_bo()
370 bool last = (xi == xtiles - 1 && yi == ytiles - 1); in vc4_create_rcl_bo()
372 emit_tile(exec, setup, x, y, first, last); in vc4_create_rcl_bo()
376 BUG_ON(setup->next_offset != size); in vc4_create_rcl_bo()
377 exec->ct1ca = setup->rcl->paddr; in vc4_create_rcl_bo()
378 exec->ct1ea = setup->rcl->paddr + setup->next_offset; in vc4_create_rcl_bo()
387 struct drm_vc4_submit_cl *args = exec->args; in vc4_full_res_bounds_check()
388 u32 render_tiles_stride = DIV_ROUND_UP(exec->args->width, 32); in vc4_full_res_bounds_check()
390 if (surf->offset > obj->base.size) { in vc4_full_res_bounds_check()
391 DRM_DEBUG("surface offset %d > BO size %zd\n", in vc4_full_res_bounds_check()
392 surf->offset, obj->base.size); in vc4_full_res_bounds_check()
393 return -EINVAL; in vc4_full_res_bounds_check()
396 if ((obj->base.size - surf->offset) / VC4_TILE_BUFFER_SIZE < in vc4_full_res_bounds_check()
397 render_tiles_stride * args->max_y_tile + args->max_x_tile) { in vc4_full_res_bounds_check()
399 "(bo size %zd, offset %d).\n", in vc4_full_res_bounds_check()
400 args->max_x_tile, args->max_y_tile, in vc4_full_res_bounds_check()
401 obj->base.size, in vc4_full_res_bounds_check()
402 surf->offset); in vc4_full_res_bounds_check()
403 return -EINVAL; in vc4_full_res_bounds_check()
413 if (surf->flags != 0 || surf->bits != 0) { in vc4_rcl_msaa_surface_setup()
415 return -EINVAL; in vc4_rcl_msaa_surface_setup()
418 if (surf->hindex == ~0) in vc4_rcl_msaa_surface_setup()
421 *obj = vc4_use_bo(exec, surf->hindex); in vc4_rcl_msaa_surface_setup()
423 return -EINVAL; in vc4_rcl_msaa_surface_setup()
425 exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj; in vc4_rcl_msaa_surface_setup()
427 if (surf->offset & 0xf) { in vc4_rcl_msaa_surface_setup()
429 return -EINVAL; in vc4_rcl_msaa_surface_setup()
440 uint8_t tiling = VC4_GET_FIELD(surf->bits, in vc4_rcl_surface_setup()
442 uint8_t buffer = VC4_GET_FIELD(surf->bits, in vc4_rcl_surface_setup()
444 uint8_t format = VC4_GET_FIELD(surf->bits, in vc4_rcl_surface_setup()
449 if (surf->flags & ~VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { in vc4_rcl_surface_setup()
451 return -EINVAL; in vc4_rcl_surface_setup()
454 if (surf->hindex == ~0) in vc4_rcl_surface_setup()
457 *obj = vc4_use_bo(exec, surf->hindex); in vc4_rcl_surface_setup()
459 return -EINVAL; in vc4_rcl_surface_setup()
462 exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj; in vc4_rcl_surface_setup()
464 if (surf->flags & VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { in vc4_rcl_surface_setup()
465 if (surf == &exec->args->zs_write) { in vc4_rcl_surface_setup()
466 DRM_DEBUG("general zs write may not be a full-res.\n"); in vc4_rcl_surface_setup()
467 return -EINVAL; in vc4_rcl_surface_setup()
470 if (surf->bits != 0) { in vc4_rcl_surface_setup()
473 return -EINVAL; in vc4_rcl_surface_setup()
483 if (surf->bits & ~(VC4_LOADSTORE_TILE_BUFFER_TILING_MASK | in vc4_rcl_surface_setup()
487 surf->bits); in vc4_rcl_surface_setup()
488 return -EINVAL; in vc4_rcl_surface_setup()
493 return -EINVAL; in vc4_rcl_surface_setup()
499 return -EINVAL; in vc4_rcl_surface_setup()
513 return -EINVAL; in vc4_rcl_surface_setup()
517 return -EINVAL; in vc4_rcl_surface_setup()
520 if (surf->offset & 0xf) { in vc4_rcl_surface_setup()
522 return -EINVAL; in vc4_rcl_surface_setup()
525 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling, in vc4_rcl_surface_setup()
526 exec->args->width, exec->args->height, cpp)) { in vc4_rcl_surface_setup()
527 return -EINVAL; in vc4_rcl_surface_setup()
539 uint8_t tiling = VC4_GET_FIELD(surf->bits, in vc4_rcl_render_config_surface_setup()
541 uint8_t format = VC4_GET_FIELD(surf->bits, in vc4_rcl_render_config_surface_setup()
545 if (surf->flags != 0) { in vc4_rcl_render_config_surface_setup()
547 return -EINVAL; in vc4_rcl_render_config_surface_setup()
550 if (surf->bits & ~(VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK | in vc4_rcl_render_config_surface_setup()
555 surf->bits); in vc4_rcl_render_config_surface_setup()
556 return -EINVAL; in vc4_rcl_render_config_surface_setup()
559 if (surf->hindex == ~0) in vc4_rcl_render_config_surface_setup()
562 *obj = vc4_use_bo(exec, surf->hindex); in vc4_rcl_render_config_surface_setup()
564 return -EINVAL; in vc4_rcl_render_config_surface_setup()
566 exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj; in vc4_rcl_render_config_surface_setup()
570 return -EINVAL; in vc4_rcl_render_config_surface_setup()
583 return -EINVAL; in vc4_rcl_render_config_surface_setup()
586 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling, in vc4_rcl_render_config_surface_setup()
587 exec->args->width, exec->args->height, cpp)) { in vc4_rcl_render_config_surface_setup()
588 return -EINVAL; in vc4_rcl_render_config_surface_setup()
597 struct drm_vc4_submit_cl *args = exec->args; in vc4_get_rcl()
598 bool has_bin = args->bin_cl_size != 0; in vc4_get_rcl()
601 if (args->min_x_tile > args->max_x_tile || in vc4_get_rcl()
602 args->min_y_tile > args->max_y_tile) { in vc4_get_rcl()
603 DRM_DEBUG("Bad render tile set (%d,%d)-(%d,%d)\n", in vc4_get_rcl()
604 args->min_x_tile, args->min_y_tile, in vc4_get_rcl()
605 args->max_x_tile, args->max_y_tile); in vc4_get_rcl()
606 return -EINVAL; in vc4_get_rcl()
610 (args->max_x_tile > exec->bin_tiles_x || in vc4_get_rcl()
611 args->max_y_tile > exec->bin_tiles_y)) { in vc4_get_rcl()
614 args->max_x_tile, args->max_y_tile, in vc4_get_rcl()
615 exec->bin_tiles_x, exec->bin_tiles_y); in vc4_get_rcl()
616 return -EINVAL; in vc4_get_rcl()
621 &args->color_write); in vc4_get_rcl()
625 ret = vc4_rcl_surface_setup(exec, &setup.color_read, &args->color_read, in vc4_get_rcl()
630 ret = vc4_rcl_surface_setup(exec, &setup.zs_read, &args->zs_read, in vc4_get_rcl()
635 ret = vc4_rcl_surface_setup(exec, &setup.zs_write, &args->zs_write, in vc4_get_rcl()
641 &args->msaa_color_write); in vc4_get_rcl()
646 &args->msaa_zs_write); in vc4_get_rcl()
656 return -EINVAL; in vc4_get_rcl()