Lines Matching full:dsi
9 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
10 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
496 /* General DSI hardware state. */
515 /* DSI channel for the panel we're connected to. */
522 /* Input clock from CPRMAN to the digital PHY, for the DSI
527 /* Input clock to the analog PHY, used to generate the DSI bit
532 /* HS Clocks generated within the DSI analog PHY. */
551 dsi_dma_workaround_write(struct vc4_dsi *dsi, u32 offset, u32 val) in dsi_dma_workaround_write() argument
553 struct dma_chan *chan = dsi->reg_dma_chan; in dsi_dma_workaround_write()
560 writel(val, dsi->regs + offset); in dsi_dma_workaround_write()
564 *dsi->reg_dma_mem = val; in dsi_dma_workaround_write()
567 dsi->reg_paddr + offset, in dsi_dma_workaround_write()
568 dsi->reg_dma_paddr, in dsi_dma_workaround_write()
586 #define DSI_READ(offset) readl(dsi->regs + (offset))
587 #define DSI_WRITE(offset, val) dsi_dma_workaround_write(dsi, offset, val)
589 DSI_READ(dsi->port ? DSI1_##offset : DSI0_##offset)
591 DSI_WRITE(dsi->port ? DSI1_##offset : DSI0_##offset, val)
592 #define DSI_PORT_BIT(bit) (dsi->port ? DSI1_##bit : DSI0_##bit)
594 /* VC4 DSI encoder KMS struct */
597 struct vc4_dsi *dsi; member
656 static void vc4_dsi_latch_ulps(struct vc4_dsi *dsi, bool latch) in vc4_dsi_latch_ulps() argument
669 static void vc4_dsi_ulps(struct vc4_dsi *dsi, bool ulps) in vc4_dsi_ulps() argument
671 bool non_continuous = dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS; in vc4_dsi_ulps()
674 (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) | in vc4_dsi_ulps()
675 (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) | in vc4_dsi_ulps()
676 (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0)); in vc4_dsi_ulps()
679 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) | in vc4_dsi_ulps()
680 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) | in vc4_dsi_ulps()
681 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0)); in vc4_dsi_ulps()
684 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) | in vc4_dsi_ulps()
685 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) | in vc4_dsi_ulps()
686 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0)); in vc4_dsi_ulps()
698 dev_warn(&dsi->pdev->dev, in vc4_dsi_ulps()
699 "Timeout waiting for DSI ULPS entry: STAT 0x%08x", in vc4_dsi_ulps()
702 vc4_dsi_latch_ulps(dsi, false); in vc4_dsi_ulps()
706 /* The DSI module can't be disabled while the module is in vc4_dsi_ulps()
711 vc4_dsi_latch_ulps(dsi, ulps); in vc4_dsi_ulps()
717 dev_warn(&dsi->pdev->dev, in vc4_dsi_ulps()
718 "Timeout waiting for DSI STOP entry: STAT 0x%08x", in vc4_dsi_ulps()
746 struct vc4_dsi *dsi = vc4_encoder->dsi; in vc4_dsi_encoder_disable() local
747 struct device *dev = &dsi->pdev->dev; in vc4_dsi_encoder_disable()
750 list_for_each_entry_reverse(iter, &dsi->bridge_chain, chain_node) { in vc4_dsi_encoder_disable()
755 vc4_dsi_ulps(dsi, true); in vc4_dsi_encoder_disable()
757 list_for_each_entry_from(iter, &dsi->bridge_chain, chain_node) { in vc4_dsi_encoder_disable()
762 clk_disable_unprepare(dsi->pll_phy_clock); in vc4_dsi_encoder_disable()
763 clk_disable_unprepare(dsi->escape_clock); in vc4_dsi_encoder_disable()
764 clk_disable_unprepare(dsi->pixel_clock); in vc4_dsi_encoder_disable()
770 * DSI PLL divider.
774 * divider. PLLD_DSI1, which drives our DSI bit clock (and therefore
775 * the pixel clock), only has an integer divider off of DSI.
787 struct vc4_dsi *dsi = vc4_encoder->dsi; in vc4_dsi_encoder_mode_fixup() local
788 struct clk *phy_parent = clk_get_parent(dsi->pll_phy_clock); in vc4_dsi_encoder_mode_fixup()
791 unsigned long pll_clock = pixel_clock_hz * dsi->divider; in vc4_dsi_encoder_mode_fixup()
808 pixel_clock_hz = pll_clock / dsi->divider; in vc4_dsi_encoder_mode_fixup()
825 struct vc4_dsi *dsi = vc4_encoder->dsi; in vc4_dsi_encoder_enable() local
826 struct device *dev = &dsi->pdev->dev; in vc4_dsi_encoder_enable()
840 DRM_ERROR("Failed to runtime PM enable on DSI%d\n", dsi->port); in vc4_dsi_encoder_enable()
845 struct drm_printer p = drm_info_printer(&dsi->pdev->dev); in vc4_dsi_encoder_enable()
846 dev_info(&dsi->pdev->dev, "DSI regs before:\n"); in vc4_dsi_encoder_enable()
847 drm_print_regset32(&p, &dsi->regset); in vc4_dsi_encoder_enable()
854 phy_clock = (pixel_clock_hz + 1000) * dsi->divider; in vc4_dsi_encoder_enable()
855 ret = clk_set_rate(dsi->pll_phy_clock, phy_clock); in vc4_dsi_encoder_enable()
857 dev_err(&dsi->pdev->dev, in vc4_dsi_encoder_enable()
861 /* Reset the DSI and all its fifos. */ in vc4_dsi_encoder_enable()
874 if (dsi->port == 0) { in vc4_dsi_encoder_enable()
878 if (dsi->lanes < 2) in vc4_dsi_encoder_enable()
881 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) in vc4_dsi_encoder_enable()
899 if (dsi->lanes < 4) in vc4_dsi_encoder_enable()
901 if (dsi->lanes < 3) in vc4_dsi_encoder_enable()
903 if (dsi->lanes < 2) in vc4_dsi_encoder_enable()
916 ret = clk_prepare_enable(dsi->escape_clock); in vc4_dsi_encoder_enable()
918 DRM_ERROR("Failed to turn on DSI escape clock: %d\n", ret); in vc4_dsi_encoder_enable()
922 ret = clk_prepare_enable(dsi->pll_phy_clock); in vc4_dsi_encoder_enable()
924 DRM_ERROR("Failed to turn on DSI PLL: %d\n", ret); in vc4_dsi_encoder_enable()
928 hs_clock = clk_get_rate(dsi->pll_phy_clock); in vc4_dsi_encoder_enable()
935 * pixel clock for pushing pixels into DSI. in vc4_dsi_encoder_enable()
938 ret = clk_set_rate(dsi->pixel_clock, dsip_clock); in vc4_dsi_encoder_enable()
944 ret = clk_prepare_enable(dsi->pixel_clock); in vc4_dsi_encoder_enable()
946 DRM_ERROR("Failed to turn on DSI pixel clock: %d\n", ret); in vc4_dsi_encoder_enable()
950 /* How many ns one DSI unit interval is. Note that the clock in vc4_dsi_encoder_enable()
1014 (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) | in vc4_dsi_encoder_enable()
1015 (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) | in vc4_dsi_encoder_enable()
1016 (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) | in vc4_dsi_encoder_enable()
1018 ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? in vc4_dsi_encoder_enable()
1020 (dsi->port == 0 ? in vc4_dsi_encoder_enable()
1046 if (dsi->port == 0) in vc4_dsi_encoder_enable()
1052 if (dsi->port == 0) { in vc4_dsi_encoder_enable()
1059 vc4_dsi_ulps(dsi, false); in vc4_dsi_encoder_enable()
1061 list_for_each_entry_reverse(iter, &dsi->bridge_chain, chain_node) { in vc4_dsi_encoder_enable()
1066 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { in vc4_dsi_encoder_enable()
1068 VC4_SET_FIELD(dsi->divider, in vc4_dsi_encoder_enable()
1070 VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) | in vc4_dsi_encoder_enable()
1081 list_for_each_entry(iter, &dsi->bridge_chain, chain_node) { in vc4_dsi_encoder_enable()
1087 struct drm_printer p = drm_info_printer(&dsi->pdev->dev); in vc4_dsi_encoder_enable()
1088 dev_info(&dsi->pdev->dev, "DSI regs after:\n"); in vc4_dsi_encoder_enable()
1089 drm_print_regset32(&p, &dsi->regset); in vc4_dsi_encoder_enable()
1096 struct vc4_dsi *dsi = host_to_dsi(host); in vc4_dsi_host_transfer() local
1174 dsi->xfer_result = 0; in vc4_dsi_host_transfer()
1175 reinit_completion(&dsi->xfer_completion); in vc4_dsi_host_transfer()
1189 if (!wait_for_completion_timeout(&dsi->xfer_completion, in vc4_dsi_host_transfer()
1191 dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout"); in vc4_dsi_host_transfer()
1192 dev_err(&dsi->pdev->dev, "instat: 0x%08x\n", in vc4_dsi_host_transfer()
1196 ret = dsi->xfer_result; in vc4_dsi_host_transfer()
1213 DRM_ERROR("DSI returned %db, expecting %db\n", in vc4_dsi_host_transfer()
1236 DRM_ERROR("DSI transfer failed, resetting: %d\n", ret); in vc4_dsi_host_transfer()
1252 struct vc4_dsi *dsi = host_to_dsi(host); in vc4_dsi_host_attach() local
1254 dsi->lanes = device->lanes; in vc4_dsi_host_attach()
1255 dsi->channel = device->channel; in vc4_dsi_host_attach()
1256 dsi->mode_flags = device->mode_flags; in vc4_dsi_host_attach()
1260 dsi->format = DSI_PFORMAT_RGB888; in vc4_dsi_host_attach()
1261 dsi->divider = 24 / dsi->lanes; in vc4_dsi_host_attach()
1264 dsi->format = DSI_PFORMAT_RGB666; in vc4_dsi_host_attach()
1265 dsi->divider = 24 / dsi->lanes; in vc4_dsi_host_attach()
1268 dsi->format = DSI_PFORMAT_RGB666_PACKED; in vc4_dsi_host_attach()
1269 dsi->divider = 18 / dsi->lanes; in vc4_dsi_host_attach()
1272 dsi->format = DSI_PFORMAT_RGB565; in vc4_dsi_host_attach()
1273 dsi->divider = 16 / dsi->lanes; in vc4_dsi_host_attach()
1276 dev_err(&dsi->pdev->dev, "Unknown DSI format: %d.\n", in vc4_dsi_host_attach()
1277 dsi->format); in vc4_dsi_host_attach()
1281 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) { in vc4_dsi_host_attach()
1282 dev_err(&dsi->pdev->dev, in vc4_dsi_host_attach()
1313 static void dsi_handle_error(struct vc4_dsi *dsi, in dsi_handle_error() argument
1320 DRM_ERROR("DSI%d: %s error\n", dsi->port, type); in dsi_handle_error()
1332 struct vc4_dsi *dsi = data; in vc4_dsi_irq_defer_to_thread_handler() local
1347 struct vc4_dsi *dsi = data; in vc4_dsi_irq_handler() local
1353 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1355 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1357 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1359 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1361 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1363 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1365 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1367 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1371 complete(&dsi->xfer_completion); in vc4_dsi_irq_handler()
1374 complete(&dsi->xfer_completion); in vc4_dsi_irq_handler()
1375 dsi->xfer_result = -ETIMEDOUT; in vc4_dsi_irq_handler()
1385 * @dsi: DSI encoder
1388 vc4_dsi_init_phy_clocks(struct vc4_dsi *dsi) in vc4_dsi_init_phy_clocks() argument
1390 struct device *dev = &dsi->pdev->dev; in vc4_dsi_init_phy_clocks()
1391 const char *parent_name = __clk_get_name(dsi->pll_phy_clock); in vc4_dsi_init_phy_clocks()
1402 dsi->clk_onecell = devm_kzalloc(dev, in vc4_dsi_init_phy_clocks()
1403 sizeof(*dsi->clk_onecell) + in vc4_dsi_init_phy_clocks()
1407 if (!dsi->clk_onecell) in vc4_dsi_init_phy_clocks()
1409 dsi->clk_onecell->num = ARRAY_SIZE(phy_clocks); in vc4_dsi_init_phy_clocks()
1412 struct clk_fixed_factor *fix = &dsi->phy_clocks[i]; in vc4_dsi_init_phy_clocks()
1421 * setting both our parent DSI PLL's rate and this in vc4_dsi_init_phy_clocks()
1432 if (dsi->port == 1) in vc4_dsi_init_phy_clocks()
1442 dsi->clk_onecell->hws[i] = &fix->hw; in vc4_dsi_init_phy_clocks()
1447 dsi->clk_onecell); in vc4_dsi_init_phy_clocks()
1455 struct vc4_dsi *dsi = dev_get_drvdata(dev); in vc4_dsi_bind() local
1466 dsi->port = (uintptr_t)match->data; in vc4_dsi_bind()
1473 INIT_LIST_HEAD(&dsi->bridge_chain); in vc4_dsi_bind()
1475 vc4_dsi_encoder->dsi = dsi; in vc4_dsi_bind()
1476 dsi->encoder = &vc4_dsi_encoder->base.base; in vc4_dsi_bind()
1478 dsi->regs = vc4_ioremap_regs(pdev, 0); in vc4_dsi_bind()
1479 if (IS_ERR(dsi->regs)) in vc4_dsi_bind()
1480 return PTR_ERR(dsi->regs); in vc4_dsi_bind()
1482 dsi->regset.base = dsi->regs; in vc4_dsi_bind()
1483 if (dsi->port == 0) { in vc4_dsi_bind()
1484 dsi->regset.regs = dsi0_regs; in vc4_dsi_bind()
1485 dsi->regset.nregs = ARRAY_SIZE(dsi0_regs); in vc4_dsi_bind()
1487 dsi->regset.regs = dsi1_regs; in vc4_dsi_bind()
1488 dsi->regset.nregs = ARRAY_SIZE(dsi1_regs); in vc4_dsi_bind()
1501 if (dsi->port == 1) { in vc4_dsi_bind()
1502 dsi->reg_dma_mem = dma_alloc_coherent(dev, 4, in vc4_dsi_bind()
1503 &dsi->reg_dma_paddr, in vc4_dsi_bind()
1505 if (!dsi->reg_dma_mem) { in vc4_dsi_bind()
1512 dsi->reg_dma_chan = dma_request_chan_by_mask(&dma_mask); in vc4_dsi_bind()
1513 if (IS_ERR(dsi->reg_dma_chan)) { in vc4_dsi_bind()
1514 ret = PTR_ERR(dsi->reg_dma_chan); in vc4_dsi_bind()
1525 dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node, in vc4_dsi_bind()
1529 init_completion(&dsi->xfer_completion); in vc4_dsi_bind()
1535 if (dsi->reg_dma_mem) in vc4_dsi_bind()
1540 "vc4 dsi", dsi); in vc4_dsi_bind()
1543 vc4_dsi_irq_handler, 0, "vc4 dsi", dsi); in vc4_dsi_bind()
1550 dsi->escape_clock = devm_clk_get(dev, "escape"); in vc4_dsi_bind()
1551 if (IS_ERR(dsi->escape_clock)) { in vc4_dsi_bind()
1552 ret = PTR_ERR(dsi->escape_clock); in vc4_dsi_bind()
1558 dsi->pll_phy_clock = devm_clk_get(dev, "phy"); in vc4_dsi_bind()
1559 if (IS_ERR(dsi->pll_phy_clock)) { in vc4_dsi_bind()
1560 ret = PTR_ERR(dsi->pll_phy_clock); in vc4_dsi_bind()
1566 dsi->pixel_clock = devm_clk_get(dev, "pixel"); in vc4_dsi_bind()
1567 if (IS_ERR(dsi->pixel_clock)) { in vc4_dsi_bind()
1568 ret = PTR_ERR(dsi->pixel_clock); in vc4_dsi_bind()
1575 &panel, &dsi->bridge); in vc4_dsi_bind()
1579 * dev from being registered. Of course that means the DSI in vc4_dsi_bind()
1590 dsi->bridge = devm_drm_panel_bridge_add_typed(dev, panel, in vc4_dsi_bind()
1592 if (IS_ERR(dsi->bridge)) in vc4_dsi_bind()
1593 return PTR_ERR(dsi->bridge); in vc4_dsi_bind()
1597 ret = clk_set_rate(dsi->escape_clock, 100 * 1000000); in vc4_dsi_bind()
1603 ret = vc4_dsi_init_phy_clocks(dsi); in vc4_dsi_bind()
1607 if (dsi->port == 1) in vc4_dsi_bind()
1608 vc4->dsi1 = dsi; in vc4_dsi_bind()
1610 drm_simple_encoder_init(drm, dsi->encoder, DRM_MODE_ENCODER_DSI); in vc4_dsi_bind()
1611 drm_encoder_helper_add(dsi->encoder, &vc4_dsi_encoder_helper_funcs); in vc4_dsi_bind()
1613 ret = drm_bridge_attach(dsi->encoder, dsi->bridge, NULL, 0); in vc4_dsi_bind()
1623 list_splice_init(&dsi->encoder->bridge_chain, &dsi->bridge_chain); in vc4_dsi_bind()
1625 if (dsi->port == 0) in vc4_dsi_bind()
1626 vc4_debugfs_add_regset32(drm, "dsi0_regs", &dsi->regset); in vc4_dsi_bind()
1628 vc4_debugfs_add_regset32(drm, "dsi1_regs", &dsi->regset); in vc4_dsi_bind()
1640 struct vc4_dsi *dsi = dev_get_drvdata(dev); in vc4_dsi_unbind() local
1642 if (dsi->bridge) in vc4_dsi_unbind()
1649 list_splice_init(&dsi->bridge_chain, &dsi->encoder->bridge_chain); in vc4_dsi_unbind()
1650 drm_encoder_cleanup(dsi->encoder); in vc4_dsi_unbind()
1652 if (dsi->port == 1) in vc4_dsi_unbind()
1664 struct vc4_dsi *dsi; in vc4_dsi_dev_probe() local
1667 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); in vc4_dsi_dev_probe()
1668 if (!dsi) in vc4_dsi_dev_probe()
1670 dev_set_drvdata(dev, dsi); in vc4_dsi_dev_probe()
1672 dsi->pdev = pdev; in vc4_dsi_dev_probe()
1674 /* Note, the initialization sequence for DSI and panels is in vc4_dsi_dev_probe()
1683 dsi->dsi_host.ops = &vc4_dsi_host_ops; in vc4_dsi_dev_probe()
1684 dsi->dsi_host.dev = dev; in vc4_dsi_dev_probe()
1685 mipi_dsi_host_register(&dsi->dsi_host); in vc4_dsi_dev_probe()
1689 mipi_dsi_host_unregister(&dsi->dsi_host); in vc4_dsi_dev_probe()
1699 struct vc4_dsi *dsi = dev_get_drvdata(dev); in vc4_dsi_dev_remove() local
1702 mipi_dsi_host_unregister(&dsi->dsi_host); in vc4_dsi_dev_remove()