Lines Matching +full:0 +full:x00000
14 WARN_ON((fieldval & ~field##_MASK) != 0); \
23 #define V3D_HUB_AXICFG 0x00000
24 # define V3D_HUB_AXICFG_MAX_LEN_MASK V3D_MASK(3, 0)
25 # define V3D_HUB_AXICFG_MAX_LEN_SHIFT 0
26 #define V3D_HUB_UIFCFG 0x00004
27 #define V3D_HUB_IDENT0 0x00008
29 #define V3D_HUB_IDENT1 0x0000c
40 # define V3D_HUB_IDENT1_TVER_MASK V3D_MASK(3, 0)
41 # define V3D_HUB_IDENT1_TVER_SHIFT 0
43 #define V3D_HUB_IDENT2 0x00010
45 # define V3D_HUB_IDENT2_L3C_NKB_MASK V3D_MASK(7, 0)
46 # define V3D_HUB_IDENT2_L3C_NKB_SHIFT 0
48 #define V3D_HUB_IDENT3 0x00014
51 # define V3D_HUB_IDENT3_IPIDX_MASK V3D_MASK(7, 0)
52 # define V3D_HUB_IDENT3_IPIDX_SHIFT 0
54 #define V3D_HUB_INT_STS 0x00050
55 #define V3D_HUB_INT_SET 0x00054
56 #define V3D_HUB_INT_CLR 0x00058
57 #define V3D_HUB_INT_MSK_STS 0x0005c
58 #define V3D_HUB_INT_MSK_SET 0x00060
59 #define V3D_HUB_INT_MSK_CLR 0x00064
65 # define V3D_HUB_INT_TFUF BIT(0)
67 #define V3D_GCA_CACHE_CTRL 0x0000c
68 # define V3D_GCA_CACHE_CTRL_FLUSH BIT(0)
70 #define V3D_GCA_SAFE_SHUTDOWN 0x000b0
71 # define V3D_GCA_SAFE_SHUTDOWN_EN BIT(0)
73 #define V3D_GCA_SAFE_SHUTDOWN_ACK 0x000b4
76 # define V3D_TOP_GR_BRIDGE_REVISION 0x00000
79 # define V3D_TOP_GR_BRIDGE_MINOR_MASK V3D_MASK(7, 0)
80 # define V3D_TOP_GR_BRIDGE_MINOR_SHIFT 0
83 # define V3D_TOP_GR_BRIDGE_SW_INIT_0 0x00008
84 # define V3D_TOP_GR_BRIDGE_SW_INIT_0_V3D_CLK_108_SW_INIT BIT(0)
86 # define V3D_TOP_GR_BRIDGE_SW_INIT_1 0x0000c
87 # define V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT BIT(0)
89 #define V3D_TFU_CS 0x00400
96 # define V3D_TFU_CS_BUSY BIT(0)
98 #define V3D_TFU_SU 0x00404
99 /* Interrupt when FINTTHR input slots are free (0 = disabled) */
104 /* skips writes, computes CRC of the image. miplevels must be 0. */
106 # define V3D_TFU_SU_THROTTLE_MASK V3D_MASK(1, 0)
107 # define V3D_TFU_SU_THROTTLE_SHIFT 0
109 #define V3D_TFU_ICFG 0x00408
111 # define V3D_TFU_ICFG_IOC BIT(0)
114 #define V3D_TFU_IIA 0x0040c
116 #define V3D_TFU_ICA 0x00410
118 #define V3D_TFU_IIS 0x00414
120 #define V3D_TFU_IUA 0x00418
122 #define V3D_TFU_IOA 0x0041c
124 #define V3D_TFU_IOS 0x00420
125 /* TFU YUV Coefficient 0 */
126 #define V3D_TFU_COEF0 0x00424
130 #define V3D_TFU_COEF1 0x00428
132 #define V3D_TFU_COEF2 0x0042c
134 #define V3D_TFU_COEF3 0x00430
136 #define V3D_TFU_CRC 0x00434
140 #define V3D_MMUC_CONTROL 0x01000
144 # define V3D_MMUC_CONTROL_ENABLE BIT(0)
146 #define V3D_MMU_CTL 0x01200
164 # define V3D_MMU_CTL_ENABLE BIT(0)
166 #define V3D_MMU_PT_PA_BASE 0x01204
167 #define V3D_MMU_HIT 0x01208
168 #define V3D_MMU_MISSES 0x0120c
169 #define V3D_MMU_STALLS 0x01210
171 #define V3D_MMU_ADDR_CAP 0x01214
173 # define V3D_MMU_ADDR_CAP_MPAGE_MASK V3D_MASK(11, 0)
174 # define V3D_MMU_ADDR_CAP_MPAGE_SHIFT 0
176 #define V3D_MMU_SHOOT_DOWN 0x01218
179 # define V3D_MMU_SHOOT_DOWN_PAGE_MASK V3D_MASK(27, 0)
180 # define V3D_MMU_SHOOT_DOWN_PAGE_SHIFT 0
182 #define V3D_MMU_BYPASS_START 0x0121c
183 #define V3D_MMU_BYPASS_END 0x01220
186 #define V3D_MMU_VIO_ID 0x0122c
189 #define V3D_MMU_ILLEGAL_ADDR 0x01230
193 #define V3D_MMU_VIO_ADDR 0x01234
195 #define V3D_MMU_DEBUG_INFO 0x01238
200 # define V3D_MMU_VERSION_MASK V3D_MASK(3, 0)
201 # define V3D_MMU_VERSION_SHIFT 0
205 #define V3D_CTL_IDENT0 0x00000
209 #define V3D_CTL_IDENT1 0x00004
221 # define V3D_IDENT1_REV_MASK V3D_MASK(3, 0)
222 # define V3D_IDENT1_REV_SHIFT 0
224 #define V3D_CTL_IDENT2 0x00008
227 #define V3D_CTL_MISCCFG 0x00018
230 # define V3D_MISCCFG_OVRTMUOUT BIT(0)
232 #define V3D_CTL_L2CACTL 0x00020
235 # define V3D_L2CACTL_L2CENA BIT(0)
237 #define V3D_CTL_SLCACTL 0x00024
244 # define V3D_SLCACTL_ICC_MASK V3D_MASK(3, 0)
245 # define V3D_SLCACTL_ICC_SHIFT 0
247 #define V3D_CTL_L2TCACTL 0x00030
251 # define V3D_L2TCACTL_FLM_FLUSH 0
258 # define V3D_L2TCACTL_L2TFLS BIT(0)
259 #define V3D_CTL_L2TFLSTA 0x00034
260 #define V3D_CTL_L2TFLEND 0x00038
262 #define V3D_CTL_INT_STS 0x00050
263 #define V3D_CTL_INT_SET 0x00054
264 #define V3D_CTL_INT_CLR 0x00058
265 #define V3D_CTL_INT_MSK_STS 0x0005c
266 #define V3D_CTL_INT_MSK_SET 0x00060
267 #define V3D_CTL_INT_MSK_CLR 0x00064
277 # define V3D_INT_FRDONE BIT(0)
279 #define V3D_CLE_CT0CS 0x00100
280 #define V3D_CLE_CT1CS 0x00104
282 #define V3D_CLE_CT0EA 0x00108
283 #define V3D_CLE_CT1EA 0x0010c
285 #define V3D_CLE_CT0CA 0x00110
286 #define V3D_CLE_CT1CA 0x00114
288 #define V3D_CLE_CT0RA 0x00118
289 #define V3D_CLE_CT1RA 0x0011c
291 #define V3D_CLE_CT0LC 0x00120
292 #define V3D_CLE_CT1LC 0x00124
293 #define V3D_CLE_CT0PC 0x00128
294 #define V3D_CLE_CT1PC 0x0012c
295 #define V3D_CLE_PCS 0x00130
296 #define V3D_CLE_BFC 0x00134
297 #define V3D_CLE_RFC 0x00138
298 #define V3D_CLE_TFBC 0x0013c
299 #define V3D_CLE_TFIT 0x00140
300 #define V3D_CLE_CT1CFG 0x00144
301 #define V3D_CLE_CT1TILECT 0x00148
302 #define V3D_CLE_CT1TSKIP 0x0014c
303 #define V3D_CLE_CT1PTCT 0x00150
304 #define V3D_CLE_CT0SYNC 0x00154
305 #define V3D_CLE_CT1SYNC 0x00158
306 #define V3D_CLE_CT0QTS 0x0015c
308 #define V3D_CLE_CT0QBA 0x00160
309 #define V3D_CLE_CT1QBA 0x00164
311 #define V3D_CLE_CT0QEA 0x00168
312 #define V3D_CLE_CT1QEA 0x0016c
314 #define V3D_CLE_CT0QMA 0x00170
315 #define V3D_CLE_CT0QMS 0x00174
316 #define V3D_CLE_CT1QCFG 0x00178
324 # define V3D_CLE_QCFG_MCDIS BIT(0)
326 #define V3D_PTB_BPCA 0x00300
327 #define V3D_PTB_BPCS 0x00304
328 #define V3D_PTB_BPOA 0x00308
329 #define V3D_PTB_BPOS 0x0030c
331 #define V3D_PTB_BXCF 0x00310
333 # define V3D_PTB_BXCF_CLIPDISA BIT(0)
335 #define V3D_V3_PCTR_0_EN 0x00674
337 #define V3D_V4_PCTR_0_EN 0x00650
338 /* When a bit is set, resets the counter to 0. */
339 #define V3D_V3_PCTR_0_CLR 0x00670
340 #define V3D_V4_PCTR_0_CLR 0x00654
341 #define V3D_PCTR_0_OVERFLOW 0x00658
343 #define V3D_V3_PCTR_0_PCTRS0 0x00684
344 #define V3D_V3_PCTR_0_PCTRS15 0x00660
348 #define V3D_V4_PCTR_0_SRC_0_3 0x00660
349 #define V3D_V4_PCTR_0_SRC_28_31 0x0067c
350 # define V3D_PCTR_S0_MASK V3D_MASK(6, 0)
351 # define V3D_PCTR_S0_SHIFT 0
361 #define V3D_PCTR_0_PCTR0 0x00680
362 #define V3D_PCTR_0_PCTR31 0x006fc
365 #define V3D_GMP_STATUS 0x00800
376 # define V3D_GMP_STATUS_VIO BIT(0)
378 #define V3D_GMP_CFG 0x00804
382 # define V3D_GMP_CFG_PROT_ENABLE BIT(0)
384 #define V3D_GMP_VIO_ADDR 0x00808
385 #define V3D_GMP_VIO_TYPE 0x0080c
386 #define V3D_GMP_TABLE_ADDR 0x00810
387 #define V3D_GMP_CLEAR_LOAD 0x00814
388 #define V3D_GMP_PRESERVE_LOAD 0x00818
389 #define V3D_GMP_VALID_LINES 0x00820
391 #define V3D_CSD_STATUS 0x00900
397 # define V3D_CSD_STATUS_HAVE_QUEUED_DISPATCH BIT(0)
399 #define V3D_CSD_QUEUED_CFG0 0x00904
402 # define V3D_CSD_QUEUED_CFG0_WG_X_OFFSET_MASK V3D_MASK(15, 0)
403 # define V3D_CSD_QUEUED_CFG0_WG_X_OFFSET_SHIFT 0
405 #define V3D_CSD_QUEUED_CFG1 0x00908
408 # define V3D_CSD_QUEUED_CFG1_WG_Y_OFFSET_MASK V3D_MASK(15, 0)
409 # define V3D_CSD_QUEUED_CFG1_WG_Y_OFFSET_SHIFT 0
411 #define V3D_CSD_QUEUED_CFG2 0x0090c
414 # define V3D_CSD_QUEUED_CFG2_WG_Z_OFFSET_MASK V3D_MASK(15, 0)
415 # define V3D_CSD_QUEUED_CFG2_WG_Z_OFFSET_SHIFT 0
417 #define V3D_CSD_QUEUED_CFG3 0x00910
425 # define V3D_CSD_QUEUED_CFG3_WG_SIZE_MASK V3D_MASK(7, 0)
426 # define V3D_CSD_QUEUED_CFG3_WG_SIZE_SHIFT 0
429 #define V3D_CSD_QUEUED_CFG4 0x00914
432 #define V3D_CSD_QUEUED_CFG5 0x00918
435 #define V3D_CSD_QUEUED_CFG6 0x0091c
437 #define V3D_CSD_CURRENT_CFG0 0x00920
438 #define V3D_CSD_CURRENT_CFG1 0x00924
439 #define V3D_CSD_CURRENT_CFG2 0x00928
440 #define V3D_CSD_CURRENT_CFG3 0x0092c
441 #define V3D_CSD_CURRENT_CFG4 0x00930
442 #define V3D_CSD_CURRENT_CFG5 0x00934
443 #define V3D_CSD_CURRENT_CFG6 0x00938
445 #define V3D_CSD_CURRENT_ID0 0x0093c
450 # define V3D_CSD_CURRENT_ID0_L_IDX_MASK V3D_MASK(7, 0)
451 # define V3D_CSD_CURRENT_ID0_L_IDX_SHIFT 0
453 #define V3D_CSD_CURRENT_ID1 0x00940
456 # define V3D_CSD_CURRENT_ID0_WG_Y_MASK V3D_MASK(15, 0)
457 # define V3D_CSD_CURRENT_ID0_WG_Y_SHIFT 0
459 #define V3D_ERR_FDBGO 0x00f04
460 #define V3D_ERR_FDBGB 0x00f08
461 #define V3D_ERR_FDBGR 0x00f0c
463 #define V3D_ERR_FDBGS 0x00f10
477 # define V3D_ERR_FDBGS_EZTEST_IP_QSTALL BIT(0)
479 #define V3D_ERR_STAT 0x00f20
495 # define V3D_ERR_VPAEABB BIT(0)