22 /* Enum for each of the V3D queues. */
43 	/* Short representation (e.g. 33, 41) of the V3D tech version
66 	/* virtual address bits from V3D to the MMU. */
69 	/* Number of V3D cores. */
125 v3d_has_csd(struct v3d_dev *v3d)  in v3d_has_csd()  argument
127 	return v3d->ver >= 41;  in v3d_has_csd()
130 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev)  argument
134 	struct v3d_dev *v3d;  member
159 	/* v3d seqno for signaled() test */
170 #define V3D_READ(offset) readl(v3d->hub_regs + offset)
171 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset)
173 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset)
174 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset)
176 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset)
177 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset)
179 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset)
180 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset)
187 	struct v3d_dev *v3d;  member
200 	/* v3d fence to be signaled by IRQ handler when the job is complete. */
322 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue);
336 void v3d_reset(struct v3d_dev *v3d);
337 void v3d_invalidate_caches(struct v3d_dev *v3d);
338 void v3d_clean_caches(struct v3d_dev *v3d);
341 int v3d_irq_init(struct v3d_dev *v3d);
342 void v3d_irq_enable(struct v3d_dev *v3d);
343 void v3d_irq_disable(struct v3d_dev *v3d);
344 void v3d_irq_reset(struct v3d_dev *v3d);
349 int v3d_mmu_set_page_table(struct v3d_dev *v3d);
354 int v3d_sched_init(struct v3d_dev *v3d);
355 void v3d_sched_fini(struct v3d_dev *v3d);