Lines Matching +full:k2g +full:- +full:dss
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
9 #include <linux/dma-mapping.h>
78 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
81 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
154 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
157 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
243 * of pixel inc is calculated like this: 1+(xinc-1)*bpp.
246 * because 1+(32-1)*8 < 255 < 1+(33-1)*4.
312 iowrite32(val, dispc->base_common + reg); in dispc_write()
317 return ioread32(dispc->base_common + reg); in dispc_read()
323 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_write()
330 void __iomem *base = dispc->base_vid[hw_plane]; in dispc_vid_read()
338 void __iomem *base = dispc->base_ovr[hw_videoport]; in dispc_ovr_write()
345 void __iomem *base = dispc->base_ovr[hw_videoport]; in dispc_ovr_read()
353 void __iomem *base = dispc->base_vp[hw_videoport]; in dispc_vp_write()
360 void __iomem *base = dispc->base_vp[hw_videoport]; in dispc_vp_read()
372 return ((1 << (start - end + 1)) - 1) << end; in FLD_MASK()
681 for (i = 0; i < dispc->feat->num_vps; ++i) { in dispc_k3_clear_irqstatus()
687 for (i = 0; i < dispc->feat->num_planes; ++i) { in dispc_k3_clear_irqstatus()
693 if (dispc->feat->subrev == DISPC_K2G) in dispc_k3_clear_irqstatus()
708 for (i = 0; i < dispc->feat->num_vps; ++i) in dispc_k3_read_and_clear_irqstatus()
711 for (i = 0; i < dispc->feat->num_planes; ++i) in dispc_k3_read_and_clear_irqstatus()
724 for (i = 0; i < dispc->feat->num_vps; ++i) in dispc_k3_read_irqenable()
727 for (i = 0; i < dispc->feat->num_planes; ++i) in dispc_k3_read_irqenable()
745 for (i = 0; i < dispc->feat->num_vps; ++i) { in dispc_k3_set_irqenable()
753 for (i = 0; i < dispc->feat->num_planes; ++i) { in dispc_k3_set_irqenable()
773 switch (dispc->feat->subrev) { in dispc_read_and_clear_irqstatus()
787 switch (dispc->feat->subrev) { in dispc_set_irqenable()
843 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, in dispc_vp_bus_check()
844 tstate->bus_flags); in dispc_vp_bus_check()
846 dev_dbg(dispc->dev, "%s: Unsupported bus format: %u\n", in dispc_vp_bus_check()
847 __func__, tstate->bus_format); in dispc_vp_bus_check()
848 return -EINVAL; in dispc_vp_bus_check()
851 if (dispc->feat->vp_bus_type[hw_videoport] != DISPC_VP_OLDI && in dispc_vp_bus_check()
852 fmt->is_oldi_fmt) { in dispc_vp_bus_check()
853 dev_dbg(dispc->dev, "%s: %s is not OLDI-port\n", in dispc_vp_bus_check()
854 __func__, dispc->feat->vp_name[hw_videoport]); in dispc_vp_bus_check()
855 return -EINVAL; in dispc_vp_bus_check()
865 if (WARN_ON(!dispc->oldi_io_ctrl)) in dispc_oldi_tx_power()
868 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT0_IO_CTRL, in dispc_oldi_tx_power()
870 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT1_IO_CTRL, in dispc_oldi_tx_power()
872 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT2_IO_CTRL, in dispc_oldi_tx_power()
874 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_DAT3_IO_CTRL, in dispc_oldi_tx_power()
876 regmap_update_bits(dispc->oldi_io_ctrl, OLDI_CLK_IO_CTRL, in dispc_oldi_tx_power()
918 if (fmt->data_width == 24) in dispc_enable_oldi()
920 else if (fmt->data_width != 18) in dispc_enable_oldi()
921 dev_warn(dispc->dev, "%s: %d port width not supported\n", in dispc_enable_oldi()
922 __func__, fmt->data_width); in dispc_enable_oldi()
926 oldi_cfg = FLD_MOD(oldi_cfg, fmt->oldi_mode_reg_val, 3, 1); in dispc_enable_oldi()
939 dev_warn(dispc->dev, "%s: timeout waiting OLDI reset done\n", in dispc_enable_oldi()
949 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, in dispc_vp_prepare()
950 tstate->bus_flags); in dispc_vp_prepare()
955 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) { in dispc_vp_prepare()
965 const struct drm_display_mode *mode = &state->adjusted_mode; in dispc_vp_enable()
971 fmt = dispc_vp_find_bus_fmt(dispc, hw_videoport, tstate->bus_format, in dispc_vp_enable()
972 tstate->bus_flags); in dispc_vp_enable()
977 dispc_set_num_datalines(dispc, hw_videoport, fmt->data_width); in dispc_vp_enable()
979 hfp = mode->hsync_start - mode->hdisplay; in dispc_vp_enable()
980 hsw = mode->hsync_end - mode->hsync_start; in dispc_vp_enable()
981 hbp = mode->htotal - mode->hsync_end; in dispc_vp_enable()
983 vfp = mode->vsync_start - mode->vdisplay; in dispc_vp_enable()
984 vsw = mode->vsync_end - mode->vsync_start; in dispc_vp_enable()
985 vbp = mode->vtotal - mode->vsync_end; in dispc_vp_enable()
988 FLD_VAL(hsw - 1, 7, 0) | in dispc_vp_enable()
989 FLD_VAL(hfp - 1, 19, 8) | in dispc_vp_enable()
990 FLD_VAL(hbp - 1, 31, 20)); in dispc_vp_enable()
993 FLD_VAL(vsw - 1, 7, 0) | in dispc_vp_enable()
997 ivs = !!(mode->flags & DRM_MODE_FLAG_NVSYNC); in dispc_vp_enable()
999 ihs = !!(mode->flags & DRM_MODE_FLAG_NHSYNC); in dispc_vp_enable()
1001 ieo = !!(tstate->bus_flags & DRM_BUS_FLAG_DE_LOW); in dispc_vp_enable()
1003 ipc = !!(tstate->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE); in dispc_vp_enable()
1008 rf = !!(tstate->bus_flags & DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE); in dispc_vp_enable()
1014 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) in dispc_vp_enable()
1027 FLD_VAL(mode->hdisplay - 1, 11, 0) | in dispc_vp_enable()
1028 FLD_VAL(mode->vdisplay - 1, 27, 16)); in dispc_vp_enable()
1040 if (dispc->feat->vp_bus_type[hw_videoport] == DISPC_VP_OLDI) { in dispc_vp_unprepare()
1119 bus_type = dispc->feat->vp_bus_type[hw_videoport]; in dispc_vp_mode_valid()
1121 max_pclk = dispc->feat->max_pclk_khz[bus_type]; in dispc_vp_mode_valid()
1126 if (mode->clock < dispc->feat->min_pclk_khz) in dispc_vp_mode_valid()
1129 if (mode->clock > max_pclk) in dispc_vp_mode_valid()
1132 if (mode->hdisplay > 4096) in dispc_vp_mode_valid()
1135 if (mode->vdisplay > 4096) in dispc_vp_mode_valid()
1139 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in dispc_vp_mode_valid()
1145 * - YUV output selected (BT656, BT1120) in dispc_vp_mode_valid()
1146 * - Dithering enabled in dispc_vp_mode_valid()
1147 * - TDM with TDMCycleFormat == 3 in dispc_vp_mode_valid()
1150 if ((mode->hdisplay % 2) != 0) in dispc_vp_mode_valid()
1153 hfp = mode->hsync_start - mode->hdisplay; in dispc_vp_mode_valid()
1154 hsw = mode->hsync_end - mode->hsync_start; in dispc_vp_mode_valid()
1155 hbp = mode->htotal - mode->hsync_end; in dispc_vp_mode_valid()
1157 vfp = mode->vsync_start - mode->vdisplay; in dispc_vp_mode_valid()
1158 vsw = mode->vsync_end - mode->vsync_start; in dispc_vp_mode_valid()
1159 vbp = mode->vtotal - mode->vsync_end; in dispc_vp_mode_valid()
1170 if (dispc->memory_bandwidth_limit) { in dispc_vp_mode_valid()
1174 bandwidth = 1000 * mode->clock; in dispc_vp_mode_valid()
1175 bandwidth = bandwidth * mode->hdisplay * mode->vdisplay * bpp; in dispc_vp_mode_valid()
1176 bandwidth = div_u64(bandwidth, mode->htotal * mode->vtotal); in dispc_vp_mode_valid()
1178 if (dispc->memory_bandwidth_limit < bandwidth) in dispc_vp_mode_valid()
1187 int ret = clk_prepare_enable(dispc->vp_clk[hw_videoport]); in dispc_vp_enable_clk()
1190 dev_err(dispc->dev, "%s: enabling clk failed: %d\n", __func__, in dispc_vp_enable_clk()
1198 clk_disable_unprepare(dispc->vp_clk[hw_videoport]); in dispc_vp_disable_clk()
1210 return (unsigned int)(abs(((rr - r) * 100) / r)); in dispc_pclk_diff()
1219 r = clk_set_rate(dispc->vp_clk[hw_videoport], rate); in dispc_vp_set_clk_rate()
1221 dev_err(dispc->dev, "vp%d: failed to set clk rate to %lu\n", in dispc_vp_set_clk_rate()
1226 new_rate = clk_get_rate(dispc->vp_clk[hw_videoport]); in dispc_vp_set_clk_rate()
1229 dev_warn(dispc->dev, in dispc_vp_set_clk_rate()
1233 dev_dbg(dispc->dev, "vp%d: new rate %lu Hz (requested %lu Hz)\n", in dispc_vp_set_clk_rate()
1234 hw_videoport, clk_get_rate(dispc->vp_clk[hw_videoport]), rate); in dispc_vp_set_clk_rate()
1244 /* On k2g there is only one plane and no need for ovr */ in dispc_k2g_ovr_set_plane()
1276 switch (dispc->feat->subrev) { in dispc_ovr_set_plane()
1298 if (dispc->feat->subrev == DISPC_K2G) in dispc_ovr_enable_layer()
1339 regval[5] = OVAL(csc->preoffset[0], csc->preoffset[1]); in dispc_csc_offset_regval()
1340 regval[6] = OVAL(csc->preoffset[2], csc->postoffset[0]); in dispc_csc_offset_regval()
1341 regval[7] = OVAL(csc->postoffset[1], csc->postoffset[2]); in dispc_csc_offset_regval()
1349 regval[0] = CVAL(csc->m[CSC_RY], csc->m[CSC_RCR]); in dispc_csc_yuv2rgb_regval()
1350 regval[1] = CVAL(csc->m[CSC_RCB], csc->m[CSC_GY]); in dispc_csc_yuv2rgb_regval()
1351 regval[2] = CVAL(csc->m[CSC_GCR], csc->m[CSC_GCB]); in dispc_csc_yuv2rgb_regval()
1352 regval[3] = CVAL(csc->m[CSC_BY], csc->m[CSC_BCR]); in dispc_csc_yuv2rgb_regval()
1353 regval[4] = CVAL(csc->m[CSC_BCB], 0); in dispc_csc_yuv2rgb_regval()
1361 regval[0] = CVAL(csc->m[CSC_YR], csc->m[CSC_YG]); in dispc_csc_rgb2yuv_regval()
1362 regval[1] = CVAL(csc->m[CSC_YB], csc->m[CSC_CRR]); in dispc_csc_rgb2yuv_regval()
1363 regval[2] = CVAL(csc->m[CSC_CRG], csc->m[CSC_CRB]); in dispc_csc_rgb2yuv_regval()
1364 regval[3] = CVAL(csc->m[CSC_CBR], csc->m[CSC_CBG]); in dispc_csc_rgb2yuv_regval()
1365 regval[4] = CVAL(csc->m[CSC_CBB], 0); in dispc_csc_rgb2yuv_regval()
1373 regval[0] = CVAL(csc->m[CSC_RR], csc->m[CSC_RG]); in dispc_csc_cpr_regval()
1374 regval[1] = CVAL(csc->m[CSC_RB], csc->m[CSC_GR]); in dispc_csc_cpr_regval()
1375 regval[2] = CVAL(csc->m[CSC_GG], csc->m[CSC_GB]); in dispc_csc_cpr_regval()
1376 regval[3] = CVAL(csc->m[CSC_BR], csc->m[CSC_BG]); in dispc_csc_cpr_regval()
1377 regval[4] = CVAL(csc->m[CSC_BB], 0); in dispc_csc_cpr_regval()
1391 DISPC_VID_CSC_COEF(6), /* K2G has no post offset support */ in dispc_k2g_vid_write_csc()
1396 csc->to_regval(csc, regval); in dispc_k2g_vid_write_csc()
1399 dev_warn(dispc->dev, "%s: No post offset support for %s\n", in dispc_k2g_vid_write_csc()
1400 __func__, csc->name); in dispc_k2g_vid_write_csc()
1419 csc->to_regval(csc, regval); in dispc_k3_vid_write_csc()
1426 /* YUV -> RGB, ITU-R BT.601, full range */
1430 256, -88, -182, /* gy, gcb, gcr |1.000 -0.344 -0.714|*/
1432 { 0, -2048, -2048, }, /* full range */
1438 /* YUV -> RGB, ITU-R BT.601, limited range */
1442 298, -100, -208, /* gy, gcb, gcr |1.164 -0.392 -0.813|*/
1444 { -256, -2048, -2048, }, /* limited range */
1450 /* YUV -> RGB, ITU-R BT.709, full range */
1454 256, -48, -120, /* gy, gcb, gcr |1.000 -0.187 -0.467|*/
1456 { 0, -2048, -2048, }, /* full range */
1462 /* YUV -> RGB, ITU-R BT.709, limited range */
1466 298, -55, -136, /* gy, gcb, gcr |1.164 -0.213 -0.533|*/
1468 { -256, -2048, -2048, }, /* limited range */
1509 coef = dispc_find_csc(state->color_encoding, state->color_range); in dispc_vid_csc_setup()
1511 dev_err(dispc->dev, "%s: CSC (%u,%u) not found\n", in dispc_vid_csc_setup()
1512 __func__, state->color_encoding, state->color_range); in dispc_vid_csc_setup()
1516 if (dispc->feat->subrev == DISPC_K2G) in dispc_vid_csc_setup()
1566 dev_err(dispc->dev, "%s: No coefficients given.\n", __func__); in dispc_vid_write_fir_coefs()
1572 u16 c0 = coefs->c0[phase]; in dispc_vid_write_fir_coefs()
1582 c1 = coefs->c1[phase]; in dispc_vid_write_fir_coefs()
1583 c2 = coefs->c2[phase]; in dispc_vid_write_fir_coefs()
1616 const struct dispc_features_scaling *f = &dispc->feat->scaling; in dispc_vid_calc_scaling()
1617 u32 fourcc = state->fb->format->format; in dispc_vid_calc_scaling()
1618 u32 in_width_max_5tap = f->in_width_max_5tap_rgb; in dispc_vid_calc_scaling()
1619 u32 in_width_max_3tap = f->in_width_max_3tap_rgb; in dispc_vid_calc_scaling()
1624 sp->xinc = 1; in dispc_vid_calc_scaling()
1625 sp->yinc = 1; in dispc_vid_calc_scaling()
1626 sp->in_w = state->src_w >> 16; in dispc_vid_calc_scaling()
1627 sp->in_w_uv = sp->in_w; in dispc_vid_calc_scaling()
1628 sp->in_h = state->src_h >> 16; in dispc_vid_calc_scaling()
1629 sp->in_h_uv = sp->in_h; in dispc_vid_calc_scaling()
1631 sp->scale_x = sp->in_w != state->crtc_w; in dispc_vid_calc_scaling()
1632 sp->scale_y = sp->in_h != state->crtc_h; in dispc_vid_calc_scaling()
1635 in_width_max_5tap = f->in_width_max_5tap_yuv; in dispc_vid_calc_scaling()
1636 in_width_max_3tap = f->in_width_max_3tap_yuv; in dispc_vid_calc_scaling()
1638 sp->in_w_uv >>= 1; in dispc_vid_calc_scaling()
1639 sp->scale_x = true; in dispc_vid_calc_scaling()
1642 sp->in_h_uv >>= 1; in dispc_vid_calc_scaling()
1643 sp->scale_y = true; in dispc_vid_calc_scaling()
1648 if ((!sp->scale_x && !sp->scale_y) || lite_plane) in dispc_vid_calc_scaling()
1651 if (sp->in_w > in_width_max_5tap) { in dispc_vid_calc_scaling()
1652 sp->five_taps = false; in dispc_vid_calc_scaling()
1654 downscale_limit = f->downscale_limit_3tap; in dispc_vid_calc_scaling()
1656 sp->five_taps = true; in dispc_vid_calc_scaling()
1658 downscale_limit = f->downscale_limit_5tap; in dispc_vid_calc_scaling()
1661 if (sp->scale_x) { in dispc_vid_calc_scaling()
1662 sp->fir_xinc = dispc_calc_fir_inc(sp->in_w, state->crtc_w); in dispc_vid_calc_scaling()
1664 if (sp->fir_xinc < dispc_calc_fir_inc(1, f->upscale_limit)) { in dispc_vid_calc_scaling()
1665 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1666 "%s: X-scaling factor %u/%u > %u\n", in dispc_vid_calc_scaling()
1667 __func__, state->crtc_w, state->src_w >> 16, in dispc_vid_calc_scaling()
1668 f->upscale_limit); in dispc_vid_calc_scaling()
1669 return -EINVAL; in dispc_vid_calc_scaling()
1672 if (sp->fir_xinc >= dispc_calc_fir_inc(downscale_limit, 1)) { in dispc_vid_calc_scaling()
1673 sp->xinc = DIV_ROUND_UP(DIV_ROUND_UP(sp->in_w, in dispc_vid_calc_scaling()
1674 state->crtc_w), in dispc_vid_calc_scaling()
1677 if (sp->xinc > f->xinc_max) { in dispc_vid_calc_scaling()
1678 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1679 "%s: X-scaling factor %u/%u < 1/%u\n", in dispc_vid_calc_scaling()
1680 __func__, state->crtc_w, in dispc_vid_calc_scaling()
1681 state->src_w >> 16, in dispc_vid_calc_scaling()
1682 downscale_limit * f->xinc_max); in dispc_vid_calc_scaling()
1683 return -EINVAL; in dispc_vid_calc_scaling()
1686 sp->in_w = (state->src_w >> 16) / sp->xinc; in dispc_vid_calc_scaling()
1689 while (sp->in_w > in_width_max) { in dispc_vid_calc_scaling()
1690 sp->xinc++; in dispc_vid_calc_scaling()
1691 sp->in_w = (state->src_w >> 16) / sp->xinc; in dispc_vid_calc_scaling()
1694 if (sp->xinc > f->xinc_max) { in dispc_vid_calc_scaling()
1695 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1697 state->src_w >> 16, in_width_max * f->xinc_max); in dispc_vid_calc_scaling()
1698 return -EINVAL; in dispc_vid_calc_scaling()
1707 sp->in_w &= ~1; in dispc_vid_calc_scaling()
1709 sp->fir_xinc = dispc_calc_fir_inc(sp->in_w, state->crtc_w); in dispc_vid_calc_scaling()
1712 if (sp->scale_y) { in dispc_vid_calc_scaling()
1713 sp->fir_yinc = dispc_calc_fir_inc(sp->in_h, state->crtc_h); in dispc_vid_calc_scaling()
1715 if (sp->fir_yinc < dispc_calc_fir_inc(1, f->upscale_limit)) { in dispc_vid_calc_scaling()
1716 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1717 "%s: Y-scaling factor %u/%u > %u\n", in dispc_vid_calc_scaling()
1718 __func__, state->crtc_h, state->src_h >> 16, in dispc_vid_calc_scaling()
1719 f->upscale_limit); in dispc_vid_calc_scaling()
1720 return -EINVAL; in dispc_vid_calc_scaling()
1723 if (sp->fir_yinc >= dispc_calc_fir_inc(downscale_limit, 1)) { in dispc_vid_calc_scaling()
1724 sp->yinc = DIV_ROUND_UP(DIV_ROUND_UP(sp->in_h, in dispc_vid_calc_scaling()
1725 state->crtc_h), in dispc_vid_calc_scaling()
1728 sp->in_h /= sp->yinc; in dispc_vid_calc_scaling()
1729 sp->fir_yinc = dispc_calc_fir_inc(sp->in_h, in dispc_vid_calc_scaling()
1730 state->crtc_h); in dispc_vid_calc_scaling()
1734 dev_dbg(dispc->dev, in dispc_vid_calc_scaling()
1735 "%s: %ux%u decim %ux%u -> %ux%u firinc %u.%03ux%u.%03u taps %u -> %ux%u\n", in dispc_vid_calc_scaling()
1736 __func__, state->src_w >> 16, state->src_h >> 16, in dispc_vid_calc_scaling()
1737 sp->xinc, sp->yinc, sp->in_w, sp->in_h, in dispc_vid_calc_scaling()
1738 sp->fir_xinc / 0x200000u, in dispc_vid_calc_scaling()
1739 ((sp->fir_xinc & 0x1FFFFFu) * 999u) / 0x1FFFFFu, in dispc_vid_calc_scaling()
1740 sp->fir_yinc / 0x200000u, in dispc_vid_calc_scaling()
1741 ((sp->fir_yinc & 0x1FFFFFu) * 999u) / 0x1FFFFFu, in dispc_vid_calc_scaling()
1742 sp->five_taps ? 5 : 3, in dispc_vid_calc_scaling()
1743 state->crtc_w, state->crtc_h); in dispc_vid_calc_scaling()
1746 if (sp->scale_x) { in dispc_vid_calc_scaling()
1747 sp->in_w_uv /= sp->xinc; in dispc_vid_calc_scaling()
1748 sp->fir_xinc_uv = dispc_calc_fir_inc(sp->in_w_uv, in dispc_vid_calc_scaling()
1749 state->crtc_w); in dispc_vid_calc_scaling()
1750 sp->xcoef_uv = tidss_get_scale_coefs(dispc->dev, in dispc_vid_calc_scaling()
1751 sp->fir_xinc_uv, in dispc_vid_calc_scaling()
1754 if (sp->scale_y) { in dispc_vid_calc_scaling()
1755 sp->in_h_uv /= sp->yinc; in dispc_vid_calc_scaling()
1756 sp->fir_yinc_uv = dispc_calc_fir_inc(sp->in_h_uv, in dispc_vid_calc_scaling()
1757 state->crtc_h); in dispc_vid_calc_scaling()
1758 sp->ycoef_uv = tidss_get_scale_coefs(dispc->dev, in dispc_vid_calc_scaling()
1759 sp->fir_yinc_uv, in dispc_vid_calc_scaling()
1760 sp->five_taps); in dispc_vid_calc_scaling()
1764 if (sp->scale_x) in dispc_vid_calc_scaling()
1765 sp->xcoef = tidss_get_scale_coefs(dispc->dev, sp->fir_xinc, in dispc_vid_calc_scaling()
1768 if (sp->scale_y) in dispc_vid_calc_scaling()
1769 sp->ycoef = tidss_get_scale_coefs(dispc->dev, sp->fir_yinc, in dispc_vid_calc_scaling()
1770 sp->five_taps); in dispc_vid_calc_scaling()
1782 sp->scale_x, 7, 7); in dispc_vid_set_scaling()
1786 sp->scale_y, 8, 8); in dispc_vid_set_scaling()
1789 if (!sp->scale_x && !sp->scale_y) in dispc_vid_set_scaling()
1792 /* VERTICAL 5-TAPS */ in dispc_vid_set_scaling()
1794 sp->five_taps, 21, 21); in dispc_vid_set_scaling()
1797 if (sp->scale_x) { in dispc_vid_set_scaling()
1799 sp->fir_xinc_uv); in dispc_vid_set_scaling()
1802 sp->xcoef_uv); in dispc_vid_set_scaling()
1804 if (sp->scale_y) { in dispc_vid_set_scaling()
1806 sp->fir_yinc_uv); in dispc_vid_set_scaling()
1809 sp->ycoef_uv); in dispc_vid_set_scaling()
1813 if (sp->scale_x) { in dispc_vid_set_scaling()
1814 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH, sp->fir_xinc); in dispc_vid_set_scaling()
1817 sp->xcoef); in dispc_vid_set_scaling()
1820 if (sp->scale_y) { in dispc_vid_set_scaling()
1821 dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRV, sp->fir_yinc); in dispc_vid_set_scaling()
1823 DISPC_VID_FIR_COEF_VERT, sp->ycoef); in dispc_vid_set_scaling()
1894 WARN_ON(!dispc->fourccs); in dispc_plane_formats()
1896 *len = dispc->num_fourccs; in dispc_plane_formats()
1898 return dispc->fourccs; in dispc_plane_formats()
1906 return 1 + (pixels - 1) * ps; in pixinc()
1908 return 1 - (-pixels + 1) * ps; in pixinc()
1918 bool lite = dispc->feat->vid_lite[hw_plane]; in dispc_plane_check()
1919 u32 fourcc = state->fb->format->format; in dispc_plane_check()
1920 bool need_scaling = state->src_w >> 16 != state->crtc_w || in dispc_plane_check()
1921 state->src_h >> 16 != state->crtc_h; in dispc_plane_check()
1926 if (!dispc_find_csc(state->color_encoding, in dispc_plane_check()
1927 state->color_range)) { in dispc_plane_check()
1928 dev_dbg(dispc->dev, in dispc_plane_check()
1930 __func__, state->color_encoding, in dispc_plane_check()
1931 state->color_range, hw_plane); in dispc_plane_check()
1932 return -EINVAL; in dispc_plane_check()
1938 dev_dbg(dispc->dev, in dispc_plane_check()
1941 state->src_w >> 16, state->src_h >> 16, in dispc_plane_check()
1942 state->crtc_w, state->crtc_h); in dispc_plane_check()
1943 return -EINVAL; in dispc_plane_check()
1956 struct drm_framebuffer *fb = state->fb; in dispc_plane_state_paddr()
1958 u32 x = state->src_x >> 16; in dispc_plane_state_paddr()
1959 u32 y = state->src_y >> 16; in dispc_plane_state_paddr()
1961 gem = drm_fb_cma_get_gem_obj(state->fb, 0); in dispc_plane_state_paddr()
1963 return gem->paddr + fb->offsets[0] + x * fb->format->cpp[0] + in dispc_plane_state_paddr()
1964 y * fb->pitches[0]; in dispc_plane_state_paddr()
1970 struct drm_framebuffer *fb = state->fb; in dispc_plane_state_p_uv_addr()
1972 u32 x = state->src_x >> 16; in dispc_plane_state_p_uv_addr()
1973 u32 y = state->src_y >> 16; in dispc_plane_state_p_uv_addr()
1975 if (WARN_ON(state->fb->format->num_planes != 2)) in dispc_plane_state_p_uv_addr()
1980 return gem->paddr + fb->offsets[1] + in dispc_plane_state_p_uv_addr()
1981 (x * fb->format->cpp[1] / fb->format->hsub) + in dispc_plane_state_p_uv_addr()
1982 (y * fb->pitches[1] / fb->format->vsub); in dispc_plane_state_p_uv_addr()
1989 bool lite = dispc->feat->vid_lite[hw_plane]; in dispc_plane_setup()
1990 u32 fourcc = state->fb->format->format; in dispc_plane_setup()
1991 u16 cpp = state->fb->format->cpp[0]; in dispc_plane_setup()
1992 u32 fb_width = state->fb->pitches[0] / cpp; in dispc_plane_setup()
2006 (scale.in_w - 1) | ((scale.in_h - 1) << 16)); in dispc_plane_setup()
2017 pixinc(1 + (scale.yinc * fb_width - in dispc_plane_setup()
2021 if (state->fb->format->num_planes == 2) { in dispc_plane_setup()
2022 u16 cpp_uv = state->fb->format->cpp[1]; in dispc_plane_setup()
2023 u32 fb_width_uv = state->fb->pitches[1] / cpp_uv; in dispc_plane_setup()
2036 pixinc(1 + (scale.yinc * fb_width_uv - in dispc_plane_setup()
2043 (state->crtc_w - 1) | in dispc_plane_setup()
2044 ((state->crtc_h - 1) << 16)); in dispc_plane_setup()
2049 /* enable YUV->RGB color conversion */ in dispc_plane_setup()
2058 0xFF & (state->alpha >> 8)); in dispc_plane_setup()
2060 if (state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) in dispc_plane_setup()
2100 dev_dbg(dispc->dev, "%s()\n", __func__); in dispc_k2g_plane_init()
2107 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) { in dispc_k2g_plane_init()
2113 thr_high = size - 1; in dispc_k2g_plane_init()
2121 dev_dbg(dispc->dev, in dispc_k2g_plane_init()
2123 dispc->feat->vid_name[hw_plane], in dispc_k2g_plane_init()
2137 * Prefetch up to fifo high-threshold value to minimize the in dispc_k2g_plane_init()
2152 dev_dbg(dispc->dev, "%s()\n", __func__); in dispc_k3_plane_init()
2162 for (hw_plane = 0; hw_plane < dispc->feat->num_planes; hw_plane++) { in dispc_k3_plane_init()
2168 thr_high = size - 1; in dispc_k3_plane_init()
2176 dev_dbg(dispc->dev, in dispc_k3_plane_init()
2178 dispc->feat->vid_name[hw_plane], in dispc_k3_plane_init()
2199 switch (dispc->feat->subrev) { in dispc_plane_init()
2216 dev_dbg(dispc->dev, "%s()\n", __func__); in dispc_vp_init()
2218 /* Enable the gamma Shadow bit-field for all VPs*/ in dispc_vp_init()
2219 for (i = 0; i < dispc->feat->num_vps; i++) in dispc_vp_init()
2229 if (dispc->feat->subrev == DISPC_J721E) { in dispc_initial_config()
2240 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_k2g_vp_write_gamma_table()
2241 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_k2g_vp_write_gamma_table()
2244 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); in dispc_k2g_vp_write_gamma_table()
2246 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT)) in dispc_k2g_vp_write_gamma_table()
2262 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_am65x_vp_write_gamma_table()
2263 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_am65x_vp_write_gamma_table()
2266 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); in dispc_am65x_vp_write_gamma_table()
2268 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_8BIT)) in dispc_am65x_vp_write_gamma_table()
2283 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_j721e_vp_write_gamma_table()
2284 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_j721e_vp_write_gamma_table()
2287 dev_dbg(dispc->dev, "%s: hw_videoport %d\n", __func__, hw_videoport); in dispc_j721e_vp_write_gamma_table()
2289 if (WARN_ON(dispc->feat->vp_feat.color.gamma_type != TIDSS_GAMMA_10BIT)) in dispc_j721e_vp_write_gamma_table()
2305 switch (dispc->feat->subrev) { in dispc_vp_write_gamma_table()
2331 u32 *table = dispc->vp_data[hw_videoport].gamma_table; in dispc_vp_set_gamma()
2332 u32 hwlen = dispc->feat->vp_feat.color.gamma_size; in dispc_vp_set_gamma()
2336 dev_dbg(dispc->dev, "%s: hw_videoport %d, lut len %u, hw len %u\n", in dispc_vp_set_gamma()
2339 if (dispc->feat->vp_feat.color.gamma_type == TIDSS_GAMMA_10BIT) in dispc_vp_set_gamma()
2349 for (i = 0; i < length - 1; ++i) { in dispc_vp_set_gamma()
2350 unsigned int first = i * (hwlen - 1) / (length - 1); in dispc_vp_set_gamma()
2351 unsigned int last = (i + 1) * (hwlen - 1) / (length - 1); in dispc_vp_set_gamma()
2352 unsigned int w = last - first; in dispc_vp_set_gamma()
2360 r = (lut[i].red * (w - j) + lut[i + 1].red * j) / w; in dispc_vp_set_gamma()
2361 g = (lut[i].green * (w - j) + lut[i + 1].green * j) / w; in dispc_vp_set_gamma()
2362 b = (lut[i].blue * (w - j) + lut[i + 1].blue * j) / w; in dispc_vp_set_gamma()
2364 r >>= 16 - hwbits; in dispc_vp_set_gamma()
2365 g >>= 16 - hwbits; in dispc_vp_set_gamma()
2366 b >>= 16 - hwbits; in dispc_vp_set_gamma()
2383 ret = -clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x200); in dispc_S31_32_to_s2_8()
2395 cpr->to_regval = dispc_csc_cpr_regval; in dispc_k2g_cpr_from_ctm()
2396 cpr->m[CSC_RR] = dispc_S31_32_to_s2_8(ctm->matrix[0]); in dispc_k2g_cpr_from_ctm()
2397 cpr->m[CSC_RG] = dispc_S31_32_to_s2_8(ctm->matrix[1]); in dispc_k2g_cpr_from_ctm()
2398 cpr->m[CSC_RB] = dispc_S31_32_to_s2_8(ctm->matrix[2]); in dispc_k2g_cpr_from_ctm()
2399 cpr->m[CSC_GR] = dispc_S31_32_to_s2_8(ctm->matrix[3]); in dispc_k2g_cpr_from_ctm()
2400 cpr->m[CSC_GG] = dispc_S31_32_to_s2_8(ctm->matrix[4]); in dispc_k2g_cpr_from_ctm()
2401 cpr->m[CSC_GB] = dispc_S31_32_to_s2_8(ctm->matrix[5]); in dispc_k2g_cpr_from_ctm()
2402 cpr->m[CSC_BR] = dispc_S31_32_to_s2_8(ctm->matrix[6]); in dispc_k2g_cpr_from_ctm()
2403 cpr->m[CSC_BG] = dispc_S31_32_to_s2_8(ctm->matrix[7]); in dispc_k2g_cpr_from_ctm()
2404 cpr->m[CSC_BB] = dispc_S31_32_to_s2_8(ctm->matrix[8]); in dispc_k2g_cpr_from_ctm()
2413 regval[0] = CVAL(csc->m[CSC_BB], csc->m[CSC_BG], csc->m[CSC_BR]); in dispc_k2g_vp_csc_cpr_regval()
2414 regval[1] = CVAL(csc->m[CSC_GB], csc->m[CSC_GG], csc->m[CSC_GR]); in dispc_k2g_vp_csc_cpr_regval()
2415 regval[2] = CVAL(csc->m[CSC_RB], csc->m[CSC_RG], csc->m[CSC_RR]); in dispc_k2g_vp_csc_cpr_regval()
2425 /* K2G CPR is packed to three registers. */ in dispc_k2g_vp_write_csc()
2461 ret = -clamp_val(((cbits & ~sign_bit) >> 24), 0, 0x400); in dispc_S31_32_to_s3_8()
2473 cpr->to_regval = dispc_csc_cpr_regval; in dispc_csc_from_ctm()
2474 cpr->m[CSC_RR] = dispc_S31_32_to_s3_8(ctm->matrix[0]); in dispc_csc_from_ctm()
2475 cpr->m[CSC_RG] = dispc_S31_32_to_s3_8(ctm->matrix[1]); in dispc_csc_from_ctm()
2476 cpr->m[CSC_RB] = dispc_S31_32_to_s3_8(ctm->matrix[2]); in dispc_csc_from_ctm()
2477 cpr->m[CSC_GR] = dispc_S31_32_to_s3_8(ctm->matrix[3]); in dispc_csc_from_ctm()
2478 cpr->m[CSC_GG] = dispc_S31_32_to_s3_8(ctm->matrix[4]); in dispc_csc_from_ctm()
2479 cpr->m[CSC_GB] = dispc_S31_32_to_s3_8(ctm->matrix[5]); in dispc_csc_from_ctm()
2480 cpr->m[CSC_BR] = dispc_S31_32_to_s3_8(ctm->matrix[6]); in dispc_csc_from_ctm()
2481 cpr->m[CSC_BG] = dispc_S31_32_to_s3_8(ctm->matrix[7]); in dispc_csc_from_ctm()
2482 cpr->m[CSC_BB] = dispc_S31_32_to_s3_8(ctm->matrix[8]); in dispc_csc_from_ctm()
2496 csc->to_regval(csc, regval); in dispc_k3_vp_write_csc()
2529 if (!(state->color_mgmt_changed || newmodeset)) in dispc_vp_set_color_mgmt()
2532 if (state->gamma_lut) { in dispc_vp_set_color_mgmt()
2533 lut = (struct drm_color_lut *)state->gamma_lut->data; in dispc_vp_set_color_mgmt()
2534 length = state->gamma_lut->length / sizeof(*lut); in dispc_vp_set_color_mgmt()
2539 if (state->ctm) in dispc_vp_set_color_mgmt()
2540 ctm = (struct drm_color_ctm *)state->ctm->data; in dispc_vp_set_color_mgmt()
2542 if (dispc->feat->subrev == DISPC_K2G) in dispc_vp_set_color_mgmt()
2557 dev_dbg(dispc->dev, "suspend\n"); in dispc_runtime_suspend()
2559 dispc->is_enabled = false; in dispc_runtime_suspend()
2561 clk_disable_unprepare(dispc->fclk); in dispc_runtime_suspend()
2568 dev_dbg(dispc->dev, "resume\n"); in dispc_runtime_resume()
2570 clk_prepare_enable(dispc->fclk); in dispc_runtime_resume()
2573 dev_warn(dispc->dev, "DSS FUNC RESET not done!\n"); in dispc_runtime_resume()
2575 dev_dbg(dispc->dev, "OMAP DSS7 rev 0x%x\n", in dispc_runtime_resume()
2578 dev_dbg(dispc->dev, "VP RESETDONE %d,%d,%d\n", in dispc_runtime_resume()
2583 if (dispc->feat->subrev == DISPC_AM65X) in dispc_runtime_resume()
2584 dev_dbg(dispc->dev, "OLDI RESETDONE %d,%d,%d\n", in dispc_runtime_resume()
2589 dev_dbg(dispc->dev, "DISPC IDLE %d\n", in dispc_runtime_resume()
2594 dispc->is_enabled = true; in dispc_runtime_resume()
2596 tidss_irq_resume(dispc->tidss); in dispc_runtime_resume()
2603 dev_dbg(tidss->dev, "%s\n", __func__); in dispc_remove()
2605 tidss->dispc = NULL; in dispc_remove()
2616 dev_err(&pdev->dev, "cannot get mem resource '%s'\n", name); in dispc_iomap_resource()
2617 return -EINVAL; in dispc_iomap_resource()
2620 b = devm_ioremap_resource(&pdev->dev, res); in dispc_iomap_resource()
2622 dev_err(&pdev->dev, "cannot ioremap resource '%s'\n", name); in dispc_iomap_resource()
2634 dispc->oldi_io_ctrl = in dispc_init_am65x_oldi_io_ctrl()
2635 syscon_regmap_lookup_by_phandle(dev->of_node, in dispc_init_am65x_oldi_io_ctrl()
2636 "ti,am65x-oldi-io-ctrl"); in dispc_init_am65x_oldi_io_ctrl()
2637 if (PTR_ERR(dispc->oldi_io_ctrl) == -ENODEV) { in dispc_init_am65x_oldi_io_ctrl()
2638 dispc->oldi_io_ctrl = NULL; in dispc_init_am65x_oldi_io_ctrl()
2639 } else if (IS_ERR(dispc->oldi_io_ctrl)) { in dispc_init_am65x_oldi_io_ctrl()
2641 __func__, PTR_ERR(dispc->oldi_io_ctrl)); in dispc_init_am65x_oldi_io_ctrl()
2642 return PTR_ERR(dispc->oldi_io_ctrl); in dispc_init_am65x_oldi_io_ctrl()
2655 dispc->errata.i2000 = true; in dispc_init_errata()
2656 dev_info(dispc->dev, "WA for erratum i2000: YUV formats disabled\n"); in dispc_init_errata()
2662 struct device *dev = tidss->dev; in dispc_init()
2671 feat = tidss->feat; in dispc_init()
2673 if (feat->subrev != DISPC_K2G) { in dispc_init()
2676 dev_warn(dev, "cannot set DMA masks to 48-bit\n"); in dispc_init()
2681 return -ENOMEM; in dispc_init()
2683 dispc->tidss = tidss; in dispc_init()
2684 dispc->dev = dev; in dispc_init()
2685 dispc->feat = feat; in dispc_init()
2689 dispc->fourccs = devm_kcalloc(dev, ARRAY_SIZE(dispc_color_formats), in dispc_init()
2690 sizeof(*dispc->fourccs), GFP_KERNEL); in dispc_init()
2691 if (!dispc->fourccs) in dispc_init()
2692 return -ENOMEM; in dispc_init()
2696 if (dispc->errata.i2000 && in dispc_init()
2700 dispc->fourccs[num_fourccs++] = dispc_color_formats[i].fourcc; in dispc_init()
2703 dispc->num_fourccs = num_fourccs; in dispc_init()
2705 dispc_common_regmap = dispc->feat->common_regs; in dispc_init()
2707 r = dispc_iomap_resource(pdev, dispc->feat->common, in dispc_init()
2708 &dispc->base_common); in dispc_init()
2712 for (i = 0; i < dispc->feat->num_planes; i++) { in dispc_init()
2713 r = dispc_iomap_resource(pdev, dispc->feat->vid_name[i], in dispc_init()
2714 &dispc->base_vid[i]); in dispc_init()
2719 for (i = 0; i < dispc->feat->num_vps; i++) { in dispc_init()
2720 u32 gamma_size = dispc->feat->vp_feat.color.gamma_size; in dispc_init()
2724 r = dispc_iomap_resource(pdev, dispc->feat->ovr_name[i], in dispc_init()
2725 &dispc->base_ovr[i]); in dispc_init()
2729 r = dispc_iomap_resource(pdev, dispc->feat->vp_name[i], in dispc_init()
2730 &dispc->base_vp[i]); in dispc_init()
2734 clk = devm_clk_get(dev, dispc->feat->vpclk_name[i]); in dispc_init()
2737 dispc->feat->vpclk_name[i], PTR_ERR(clk)); in dispc_init()
2740 dispc->vp_clk[i] = clk; in dispc_init()
2746 return -ENOMEM; in dispc_init()
2747 dispc->vp_data[i].gamma_table = gamma_table; in dispc_init()
2750 if (feat->subrev == DISPC_AM65X) { in dispc_init()
2756 dispc->fclk = devm_clk_get(dev, "fck"); in dispc_init()
2757 if (IS_ERR(dispc->fclk)) { in dispc_init()
2759 __func__, PTR_ERR(dispc->fclk)); in dispc_init()
2760 return PTR_ERR(dispc->fclk); in dispc_init()
2762 dev_dbg(dev, "DSS fclk %lu Hz\n", clk_get_rate(dispc->fclk)); in dispc_init()
2764 of_property_read_u32(dispc->dev->of_node, "max-memory-bandwidth", in dispc_init()
2765 &dispc->memory_bandwidth_limit); in dispc_init()
2767 tidss->dispc = dispc; in dispc_init()