Lines Matching refs:tx_pu_value
44 u8 tx_pu_value; member
64 .tx_pu_value = 0x10,
79 .tx_pu_value = 0x40,
94 .tx_pu_value = 0x66,
109 .tx_pu_value = 0x66,
124 .tx_pu_value = 0x66,
143 .tx_pu_value = 0x40,
158 .tx_pu_value = 0x66,
173 .tx_pu_value = 0x66,
188 .tx_pu_value = 0x66,
208 .tx_pu_value = 0,
223 .tx_pu_value = 0,
238 .tx_pu_value = 0x66 /* 0 */,
253 .tx_pu_value = 64,
268 .tx_pu_value = 96,
287 .tx_pu_value = 0,
302 .tx_pu_value = 0,
317 .tx_pu_value = 0x66 /* 0 */,
332 .tx_pu_value = 64,
347 .tx_pu_value = 96,
2538 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value); in tegra_sor_hdmi_enable()