Lines Matching +full:mipi +full:- +full:dsi
1 // SPDX-License-Identifier: GPL-2.0-only
29 #include "dsi.h"
30 #include "mipi-phy.h"
73 struct tegra_mipi_device *mipi; member
81 /* for ganged-mode support */
102 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) in tegra_dsi_get_state() argument
104 return to_dsi_state(dsi->output.connector.state); in tegra_dsi_get_state()
107 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) in tegra_dsi_readl() argument
109 u32 value = readl(dsi->regs + (offset << 2)); in tegra_dsi_readl()
111 trace_dsi_readl(dsi->dev, offset, value); in tegra_dsi_readl()
116 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value, in tegra_dsi_writel() argument
119 trace_dsi_writel(dsi->dev, offset, value); in tegra_dsi_writel()
120 writel(value, dsi->regs + (offset << 2)); in tegra_dsi_writel()
201 struct drm_info_node *node = s->private; in tegra_dsi_show_regs()
202 struct tegra_dsi *dsi = node->info_ent->data; in tegra_dsi_show_regs() local
203 struct drm_crtc *crtc = dsi->output.encoder.crtc; in tegra_dsi_show_regs()
204 struct drm_device *drm = node->minor->dev; in tegra_dsi_show_regs()
210 if (!crtc || !crtc->state->active) { in tegra_dsi_show_regs()
211 err = -EBUSY; in tegra_dsi_show_regs()
218 seq_printf(s, "%-32s %#05x %08x\n", tegra_dsi_regs[i].name, in tegra_dsi_show_regs()
219 offset, tegra_dsi_readl(dsi, offset)); in tegra_dsi_show_regs()
235 struct drm_minor *minor = connector->dev->primary; in tegra_dsi_late_register()
236 struct dentry *root = connector->debugfs_entry; in tegra_dsi_late_register()
237 struct tegra_dsi *dsi = to_dsi(output); in tegra_dsi_late_register() local
239 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_dsi_late_register()
241 if (!dsi->debugfs_files) in tegra_dsi_late_register()
242 return -ENOMEM; in tegra_dsi_late_register()
245 dsi->debugfs_files[i].data = dsi; in tegra_dsi_late_register()
247 drm_debugfs_create_files(dsi->debugfs_files, count, root, minor); in tegra_dsi_late_register()
256 struct tegra_dsi *dsi = to_dsi(output); in tegra_dsi_early_unregister() local
258 drm_debugfs_remove_files(dsi->debugfs_files, count, in tegra_dsi_early_unregister()
259 connector->dev->primary); in tegra_dsi_early_unregister()
260 kfree(dsi->debugfs_files); in tegra_dsi_early_unregister()
261 dsi->debugfs_files = NULL; in tegra_dsi_early_unregister()
275 * non-burst mode with sync pulses
313 * non-burst mode with sync events
357 static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi, in tegra_dsi_set_phy_timing() argument
363 value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 | in tegra_dsi_set_phy_timing()
364 DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 | in tegra_dsi_set_phy_timing()
365 DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 | in tegra_dsi_set_phy_timing()
366 DSI_TIMING_FIELD(timing->hsprepare, period, 1); in tegra_dsi_set_phy_timing()
367 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0); in tegra_dsi_set_phy_timing()
369 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 | in tegra_dsi_set_phy_timing()
370 DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 | in tegra_dsi_set_phy_timing()
371 DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 | in tegra_dsi_set_phy_timing()
372 DSI_TIMING_FIELD(timing->lpx, period, 1); in tegra_dsi_set_phy_timing()
373 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1); in tegra_dsi_set_phy_timing()
375 value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 | in tegra_dsi_set_phy_timing()
376 DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 | in tegra_dsi_set_phy_timing()
378 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2); in tegra_dsi_set_phy_timing()
380 value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 | in tegra_dsi_set_phy_timing()
381 DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 | in tegra_dsi_set_phy_timing()
382 DSI_TIMING_FIELD(timing->tago, period, 1); in tegra_dsi_set_phy_timing()
383 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING); in tegra_dsi_set_phy_timing()
385 if (dsi->slave) in tegra_dsi_set_phy_timing()
386 tegra_dsi_set_phy_timing(dsi->slave, period, timing); in tegra_dsi_set_phy_timing()
410 return -EINVAL; in tegra_dsi_get_muldiv()
437 return -EINVAL; in tegra_dsi_get_format()
443 static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start, in tegra_dsi_ganged_enable() argument
448 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START); in tegra_dsi_ganged_enable()
449 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE); in tegra_dsi_ganged_enable()
452 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL); in tegra_dsi_ganged_enable()
455 static void tegra_dsi_enable(struct tegra_dsi *dsi) in tegra_dsi_enable() argument
459 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); in tegra_dsi_enable()
461 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); in tegra_dsi_enable()
463 if (dsi->slave) in tegra_dsi_enable()
464 tegra_dsi_enable(dsi->slave); in tegra_dsi_enable()
467 static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi) in tegra_dsi_get_lanes() argument
469 if (dsi->master) in tegra_dsi_get_lanes()
470 return dsi->master->lanes + dsi->lanes; in tegra_dsi_get_lanes()
472 if (dsi->slave) in tegra_dsi_get_lanes()
473 return dsi->lanes + dsi->slave->lanes; in tegra_dsi_get_lanes()
475 return dsi->lanes; in tegra_dsi_get_lanes()
478 static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe, in tegra_dsi_configure() argument
487 if (dsi->master) in tegra_dsi_configure()
488 state = tegra_dsi_get_state(dsi->master); in tegra_dsi_configure()
490 state = tegra_dsi_get_state(dsi); in tegra_dsi_configure()
492 mul = state->mul; in tegra_dsi_configure()
493 div = state->div; in tegra_dsi_configure()
495 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { in tegra_dsi_configure()
496 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n"); in tegra_dsi_configure()
498 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) { in tegra_dsi_configure()
499 DRM_DEBUG_KMS("Non-burst video mode with sync events\n"); in tegra_dsi_configure()
507 DSI_CONTROL_FORMAT(state->format) | in tegra_dsi_configure()
508 DSI_CONTROL_LANES(dsi->lanes - 1) | in tegra_dsi_configure()
510 tegra_dsi_writel(dsi, value, DSI_CONTROL); in tegra_dsi_configure()
512 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD); in tegra_dsi_configure()
515 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); in tegra_dsi_configure()
517 value = tegra_dsi_readl(dsi, DSI_CONTROL); in tegra_dsi_configure()
519 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) in tegra_dsi_configure()
525 if (dsi->flags & MIPI_DSI_MODE_VIDEO) in tegra_dsi_configure()
532 tegra_dsi_writel(dsi, value, DSI_CONTROL); in tegra_dsi_configure()
535 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i); in tegra_dsi_configure()
537 if (dsi->flags & MIPI_DSI_MODE_VIDEO) { in tegra_dsi_configure()
539 hact = mode->hdisplay * mul / div; in tegra_dsi_configure()
542 hsw = (mode->hsync_end - mode->hsync_start) * mul / div; in tegra_dsi_configure()
545 hbp = (mode->htotal - mode->hsync_end) * mul / div; in tegra_dsi_configure()
547 if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0) in tegra_dsi_configure()
551 hfp = (mode->hsync_start - mode->hdisplay) * mul / div; in tegra_dsi_configure()
554 hsw -= 10; in tegra_dsi_configure()
555 hbp -= 14; in tegra_dsi_configure()
556 hfp -= 8; in tegra_dsi_configure()
558 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1); in tegra_dsi_configure()
559 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3); in tegra_dsi_configure()
560 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5); in tegra_dsi_configure()
561 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7); in tegra_dsi_configure()
563 /* set SOL delay (for non-burst mode only) */ in tegra_dsi_configure()
564 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY); in tegra_dsi_configure()
570 if (dsi->master || dsi->slave) { in tegra_dsi_configure()
572 * For ganged mode, assume symmetric left-right mode. in tegra_dsi_configure()
574 bytes = 1 + (mode->hdisplay / 2) * mul / div; in tegra_dsi_configure()
577 bytes = 1 + mode->hdisplay * mul / div; in tegra_dsi_configure()
580 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1); in tegra_dsi_configure()
581 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3); in tegra_dsi_configure()
582 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5); in tegra_dsi_configure()
583 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7); in tegra_dsi_configure()
587 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS); in tegra_dsi_configure()
590 if (dsi->master || dsi->slave) { in tegra_dsi_configure()
592 unsigned int lanes = state->lanes; in tegra_dsi_configure()
600 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes); in tegra_dsi_configure()
602 value = bclk - bclk_ganged + delay + 20; in tegra_dsi_configure()
604 /* TODO: revisit for non-ganged mode */ in tegra_dsi_configure()
608 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY); in tegra_dsi_configure()
611 if (dsi->slave) { in tegra_dsi_configure()
612 tegra_dsi_configure(dsi->slave, pipe, mode); in tegra_dsi_configure()
615 * TODO: Support modes other than symmetrical left-right in tegra_dsi_configure()
618 tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2); in tegra_dsi_configure()
619 tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2, in tegra_dsi_configure()
620 mode->hdisplay / 2); in tegra_dsi_configure()
624 static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout) in tegra_dsi_wait_idle() argument
631 value = tegra_dsi_readl(dsi, DSI_STATUS); in tegra_dsi_wait_idle()
638 return -ETIMEDOUT; in tegra_dsi_wait_idle()
641 static void tegra_dsi_video_disable(struct tegra_dsi *dsi) in tegra_dsi_video_disable() argument
645 value = tegra_dsi_readl(dsi, DSI_CONTROL); in tegra_dsi_video_disable()
647 tegra_dsi_writel(dsi, value, DSI_CONTROL); in tegra_dsi_video_disable()
649 if (dsi->slave) in tegra_dsi_video_disable()
650 tegra_dsi_video_disable(dsi->slave); in tegra_dsi_video_disable()
653 static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi) in tegra_dsi_ganged_disable() argument
655 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START); in tegra_dsi_ganged_disable()
656 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE); in tegra_dsi_ganged_disable()
657 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL); in tegra_dsi_ganged_disable()
660 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi) in tegra_dsi_pad_enable() argument
665 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); in tegra_dsi_pad_enable()
670 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) in tegra_dsi_pad_calibrate() argument
679 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); in tegra_dsi_pad_calibrate()
680 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); in tegra_dsi_pad_calibrate()
681 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); in tegra_dsi_pad_calibrate()
682 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); in tegra_dsi_pad_calibrate()
683 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); in tegra_dsi_pad_calibrate()
686 tegra_dsi_pad_enable(dsi); in tegra_dsi_pad_calibrate()
691 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); in tegra_dsi_pad_calibrate()
695 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); in tegra_dsi_pad_calibrate()
697 err = tegra_mipi_start_calibration(dsi->mipi); in tegra_dsi_pad_calibrate()
701 return tegra_mipi_finish_calibration(dsi->mipi); in tegra_dsi_pad_calibrate()
704 static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk, in tegra_dsi_set_timeout() argument
710 /* one frame high-speed transmission timeout */ in tegra_dsi_set_timeout()
713 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0); in tegra_dsi_set_timeout()
718 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1); in tegra_dsi_set_timeout()
721 tegra_dsi_writel(dsi, value, DSI_TO_TALLY); in tegra_dsi_set_timeout()
723 if (dsi->slave) in tegra_dsi_set_timeout()
724 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh); in tegra_dsi_set_timeout()
727 static void tegra_dsi_disable(struct tegra_dsi *dsi) in tegra_dsi_disable() argument
731 if (dsi->slave) { in tegra_dsi_disable()
732 tegra_dsi_ganged_disable(dsi->slave); in tegra_dsi_disable()
733 tegra_dsi_ganged_disable(dsi); in tegra_dsi_disable()
736 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); in tegra_dsi_disable()
738 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); in tegra_dsi_disable()
740 if (dsi->slave) in tegra_dsi_disable()
741 tegra_dsi_disable(dsi->slave); in tegra_dsi_disable()
746 static void tegra_dsi_soft_reset(struct tegra_dsi *dsi) in tegra_dsi_soft_reset() argument
750 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); in tegra_dsi_soft_reset()
752 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); in tegra_dsi_soft_reset()
756 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); in tegra_dsi_soft_reset()
758 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); in tegra_dsi_soft_reset()
762 value = tegra_dsi_readl(dsi, DSI_TRIGGER); in tegra_dsi_soft_reset()
764 tegra_dsi_writel(dsi, 0, DSI_TRIGGER); in tegra_dsi_soft_reset()
766 if (dsi->slave) in tegra_dsi_soft_reset()
767 tegra_dsi_soft_reset(dsi->slave); in tegra_dsi_soft_reset()
777 if (connector->state) { in tegra_dsi_connector_reset()
778 __drm_atomic_helper_connector_destroy_state(connector->state); in tegra_dsi_connector_reset()
779 kfree(connector->state); in tegra_dsi_connector_reset()
782 __drm_atomic_helper_connector_reset(connector, &state->base); in tegra_dsi_connector_reset()
788 struct tegra_dsi_state *state = to_dsi_state(connector->state); in tegra_dsi_connector_duplicate_state()
796 ©->base); in tegra_dsi_connector_duplicate_state()
798 return ©->base; in tegra_dsi_connector_duplicate_state()
824 static void tegra_dsi_unprepare(struct tegra_dsi *dsi) in tegra_dsi_unprepare() argument
828 if (dsi->slave) in tegra_dsi_unprepare()
829 tegra_dsi_unprepare(dsi->slave); in tegra_dsi_unprepare()
831 err = tegra_mipi_disable(dsi->mipi); in tegra_dsi_unprepare()
833 dev_err(dsi->dev, "failed to disable MIPI calibration: %d\n", in tegra_dsi_unprepare()
836 err = host1x_client_suspend(&dsi->client); in tegra_dsi_unprepare()
838 dev_err(dsi->dev, "failed to suspend: %d\n", err); in tegra_dsi_unprepare()
844 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); in tegra_dsi_encoder_disable()
845 struct tegra_dsi *dsi = to_dsi(output); in tegra_dsi_encoder_disable() local
849 if (output->panel) in tegra_dsi_encoder_disable()
850 drm_panel_disable(output->panel); in tegra_dsi_encoder_disable()
852 tegra_dsi_video_disable(dsi); in tegra_dsi_encoder_disable()
866 err = tegra_dsi_wait_idle(dsi, 100); in tegra_dsi_encoder_disable()
868 dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err); in tegra_dsi_encoder_disable()
870 tegra_dsi_soft_reset(dsi); in tegra_dsi_encoder_disable()
872 if (output->panel) in tegra_dsi_encoder_disable()
873 drm_panel_unprepare(output->panel); in tegra_dsi_encoder_disable()
875 tegra_dsi_disable(dsi); in tegra_dsi_encoder_disable()
877 tegra_dsi_unprepare(dsi); in tegra_dsi_encoder_disable()
880 static int tegra_dsi_prepare(struct tegra_dsi *dsi) in tegra_dsi_prepare() argument
884 err = host1x_client_resume(&dsi->client); in tegra_dsi_prepare()
886 dev_err(dsi->dev, "failed to resume: %d\n", err); in tegra_dsi_prepare()
890 err = tegra_mipi_enable(dsi->mipi); in tegra_dsi_prepare()
892 dev_err(dsi->dev, "failed to enable MIPI calibration: %d\n", in tegra_dsi_prepare()
895 err = tegra_dsi_pad_calibrate(dsi); in tegra_dsi_prepare()
897 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err); in tegra_dsi_prepare()
899 if (dsi->slave) in tegra_dsi_prepare()
900 tegra_dsi_prepare(dsi->slave); in tegra_dsi_prepare()
907 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; in tegra_dsi_encoder_enable()
909 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); in tegra_dsi_encoder_enable()
910 struct tegra_dsi *dsi = to_dsi(output); in tegra_dsi_encoder_enable() local
915 err = tegra_dsi_prepare(dsi); in tegra_dsi_encoder_enable()
917 dev_err(dsi->dev, "failed to prepare: %d\n", err); in tegra_dsi_encoder_enable()
921 state = tegra_dsi_get_state(dsi); in tegra_dsi_encoder_enable()
923 tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh); in tegra_dsi_encoder_enable()
926 * The D-PHY timing fields are expressed in byte-clock cycles, so in tegra_dsi_encoder_enable()
929 tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing); in tegra_dsi_encoder_enable()
931 if (output->panel) in tegra_dsi_encoder_enable()
932 drm_panel_prepare(output->panel); in tegra_dsi_encoder_enable()
934 tegra_dsi_configure(dsi, dc->pipe, mode); in tegra_dsi_encoder_enable()
943 /* enable DSI controller */ in tegra_dsi_encoder_enable()
944 tegra_dsi_enable(dsi); in tegra_dsi_encoder_enable()
946 if (output->panel) in tegra_dsi_encoder_enable()
947 drm_panel_enable(output->panel); in tegra_dsi_encoder_enable()
957 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); in tegra_dsi_encoder_atomic_check()
958 struct tegra_dsi *dsi = to_dsi(output); in tegra_dsi_encoder_atomic_check() local
963 state->pclk = crtc_state->mode.clock * 1000; in tegra_dsi_encoder_atomic_check()
965 err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div); in tegra_dsi_encoder_atomic_check()
969 state->lanes = tegra_dsi_get_lanes(dsi); in tegra_dsi_encoder_atomic_check()
971 err = tegra_dsi_get_format(dsi->format, &state->format); in tegra_dsi_encoder_atomic_check()
975 state->vrefresh = drm_mode_vrefresh(&crtc_state->mode); in tegra_dsi_encoder_atomic_check()
978 state->bclk = (state->pclk * state->mul) / (state->div * state->lanes); in tegra_dsi_encoder_atomic_check()
980 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div, in tegra_dsi_encoder_atomic_check()
981 state->lanes); in tegra_dsi_encoder_atomic_check()
982 DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format, in tegra_dsi_encoder_atomic_check()
983 state->vrefresh); in tegra_dsi_encoder_atomic_check()
984 DRM_DEBUG_KMS("bclk: %lu\n", state->bclk); in tegra_dsi_encoder_atomic_check()
989 plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC; in tegra_dsi_encoder_atomic_check()
990 state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld); in tegra_dsi_encoder_atomic_check()
992 err = mipi_dphy_timing_get_default(&state->timing, state->period); in tegra_dsi_encoder_atomic_check()
996 err = mipi_dphy_timing_validate(&state->timing, state->period); in tegra_dsi_encoder_atomic_check()
998 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err); in tegra_dsi_encoder_atomic_check()
1019 scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2; in tegra_dsi_encoder_atomic_check()
1021 err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent, in tegra_dsi_encoder_atomic_check()
1024 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); in tegra_dsi_encoder_atomic_check()
1039 struct drm_device *drm = dev_get_drvdata(client->host); in tegra_dsi_init()
1040 struct tegra_dsi *dsi = host1x_client_to_dsi(client); in tegra_dsi_init() local
1044 if (!dsi->master) { in tegra_dsi_init()
1045 dsi->output.dev = client->dev; in tegra_dsi_init()
1047 drm_connector_init(drm, &dsi->output.connector, in tegra_dsi_init()
1050 drm_connector_helper_add(&dsi->output.connector, in tegra_dsi_init()
1052 dsi->output.connector.dpms = DRM_MODE_DPMS_OFF; in tegra_dsi_init()
1054 drm_simple_encoder_init(drm, &dsi->output.encoder, in tegra_dsi_init()
1056 drm_encoder_helper_add(&dsi->output.encoder, in tegra_dsi_init()
1059 drm_connector_attach_encoder(&dsi->output.connector, in tegra_dsi_init()
1060 &dsi->output.encoder); in tegra_dsi_init()
1061 drm_connector_register(&dsi->output.connector); in tegra_dsi_init()
1063 err = tegra_output_init(drm, &dsi->output); in tegra_dsi_init()
1065 dev_err(dsi->dev, "failed to initialize output: %d\n", in tegra_dsi_init()
1068 dsi->output.encoder.possible_crtcs = 0x3; in tegra_dsi_init()
1076 struct tegra_dsi *dsi = host1x_client_to_dsi(client); in tegra_dsi_exit() local
1078 tegra_output_exit(&dsi->output); in tegra_dsi_exit()
1085 struct tegra_dsi *dsi = host1x_client_to_dsi(client); in tegra_dsi_runtime_suspend() local
1086 struct device *dev = client->dev; in tegra_dsi_runtime_suspend()
1089 if (dsi->rst) { in tegra_dsi_runtime_suspend()
1090 err = reset_control_assert(dsi->rst); in tegra_dsi_runtime_suspend()
1099 clk_disable_unprepare(dsi->clk_lp); in tegra_dsi_runtime_suspend()
1100 clk_disable_unprepare(dsi->clk); in tegra_dsi_runtime_suspend()
1102 regulator_disable(dsi->vdd); in tegra_dsi_runtime_suspend()
1110 struct tegra_dsi *dsi = host1x_client_to_dsi(client); in tegra_dsi_runtime_resume() local
1111 struct device *dev = client->dev; in tegra_dsi_runtime_resume()
1120 err = regulator_enable(dsi->vdd); in tegra_dsi_runtime_resume()
1126 err = clk_prepare_enable(dsi->clk); in tegra_dsi_runtime_resume()
1128 dev_err(dev, "cannot enable DSI clock: %d\n", err); in tegra_dsi_runtime_resume()
1132 err = clk_prepare_enable(dsi->clk_lp); in tegra_dsi_runtime_resume()
1134 dev_err(dev, "cannot enable low-power clock: %d\n", err); in tegra_dsi_runtime_resume()
1140 if (dsi->rst) { in tegra_dsi_runtime_resume()
1141 err = reset_control_deassert(dsi->rst); in tegra_dsi_runtime_resume()
1151 clk_disable_unprepare(dsi->clk_lp); in tegra_dsi_runtime_resume()
1153 clk_disable_unprepare(dsi->clk); in tegra_dsi_runtime_resume()
1155 regulator_disable(dsi->vdd); in tegra_dsi_runtime_resume()
1168 static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi) in tegra_dsi_setup_clocks() argument
1173 parent = clk_get_parent(dsi->clk); in tegra_dsi_setup_clocks()
1175 return -EINVAL; in tegra_dsi_setup_clocks()
1177 err = clk_set_parent(parent, dsi->clk_parent); in tegra_dsi_setup_clocks()
1189 "Low-Power Transmit Sync Error",
1193 "ECC Error, single-bit",
1194 "ECC Error, multi-bit",
1196 "DSI Data Type Not Recognized",
1197 "DSI VC ID Invalid",
1200 "DSI Protocol Violation",
1203 static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi, in tegra_dsi_read_response() argument
1207 u8 *rx = msg->rx_buf; in tegra_dsi_read_response()
1214 value = tegra_dsi_readl(dsi, DSI_RD_DATA); in tegra_dsi_read_response()
1219 dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n", in tegra_dsi_read_response()
1223 dev_dbg(dsi->dev, " %2u: %s\n", i, in tegra_dsi_read_response()
1247 dev_err(dsi->dev, "unhandled response type: %02x\n", in tegra_dsi_read_response()
1249 return -EPROTO; in tegra_dsi_read_response()
1252 size = min(size, msg->rx_len); in tegra_dsi_read_response()
1254 if (msg->rx_buf && size > 0) { in tegra_dsi_read_response()
1255 for (i = 0, j = 0; i < count - 1; i++, j += 4) { in tegra_dsi_read_response()
1256 u8 *rx = msg->rx_buf + j; in tegra_dsi_read_response()
1258 value = tegra_dsi_readl(dsi, DSI_RD_DATA); in tegra_dsi_read_response()
1260 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++) in tegra_dsi_read_response()
1268 static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout) in tegra_dsi_transmit() argument
1270 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER); in tegra_dsi_transmit()
1275 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER); in tegra_dsi_transmit()
1283 return -ETIMEDOUT; in tegra_dsi_transmit()
1286 static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi, in tegra_dsi_wait_for_response() argument
1292 u32 value = tegra_dsi_readl(dsi, DSI_STATUS); in tegra_dsi_wait_for_response()
1302 return -ETIMEDOUT; in tegra_dsi_wait_for_response()
1305 static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset, in tegra_dsi_writesl() argument
1318 tegra_dsi_writel(dsi, value, DSI_WR_DATA); in tegra_dsi_writesl()
1325 struct tegra_dsi *dsi = host_to_tegra(host); in tegra_dsi_host_transfer() local
1339 if (packet.size > dsi->video_fifo_depth * 4) in tegra_dsi_host_transfer()
1340 return -ENOSPC; in tegra_dsi_host_transfer()
1343 value = tegra_dsi_readl(dsi, DSI_STATUS); in tegra_dsi_host_transfer()
1346 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); in tegra_dsi_host_transfer()
1350 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); in tegra_dsi_host_transfer()
1352 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); in tegra_dsi_host_transfer()
1359 if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0) in tegra_dsi_host_transfer()
1366 if (packet.size > dsi->host_fifo_depth * 4) in tegra_dsi_host_transfer()
1369 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); in tegra_dsi_host_transfer()
1375 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || in tegra_dsi_host_transfer()
1376 (msg->rx_buf && msg->rx_len > 0)) { in tegra_dsi_host_transfer()
1377 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL); in tegra_dsi_host_transfer()
1379 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); in tegra_dsi_host_transfer()
1383 tegra_dsi_writel(dsi, value, DSI_CONTROL); in tegra_dsi_host_transfer()
1387 tegra_dsi_writel(dsi, value, DSI_WR_DATA); in tegra_dsi_host_transfer()
1391 tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload, in tegra_dsi_host_transfer()
1394 err = tegra_dsi_transmit(dsi, 250); in tegra_dsi_host_transfer()
1398 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || in tegra_dsi_host_transfer()
1399 (msg->rx_buf && msg->rx_len > 0)) { in tegra_dsi_host_transfer()
1400 err = tegra_dsi_wait_for_response(dsi, 250); in tegra_dsi_host_transfer()
1406 value = tegra_dsi_readl(dsi, DSI_RD_DATA); in tegra_dsi_host_transfer()
1410 dev_dbg(dsi->dev, "ACK\n"); in tegra_dsi_host_transfer()
1416 dev_dbg(dsi->dev, "ESCAPE\n"); in tegra_dsi_host_transfer()
1421 dev_err(dsi->dev, "unknown status: %08x\n", value); in tegra_dsi_host_transfer()
1426 err = tegra_dsi_read_response(dsi, msg, count); in tegra_dsi_host_transfer()
1428 dev_err(dsi->dev, in tegra_dsi_host_transfer()
1441 * For write commands, we have transmitted the 4-byte header in tegra_dsi_host_transfer()
1442 * plus the variable-length payload. in tegra_dsi_host_transfer()
1450 static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi) in tegra_dsi_ganged_setup() argument
1455 /* make sure both DSI controllers share the same PLL */ in tegra_dsi_ganged_setup()
1456 parent = clk_get_parent(dsi->slave->clk); in tegra_dsi_ganged_setup()
1458 return -EINVAL; in tegra_dsi_ganged_setup()
1460 err = clk_set_parent(parent, dsi->clk_parent); in tegra_dsi_ganged_setup()
1470 struct tegra_dsi *dsi = host_to_tegra(host); in tegra_dsi_host_attach() local
1472 dsi->flags = device->mode_flags; in tegra_dsi_host_attach()
1473 dsi->format = device->format; in tegra_dsi_host_attach()
1474 dsi->lanes = device->lanes; in tegra_dsi_host_attach()
1476 if (dsi->slave) { in tegra_dsi_host_attach()
1479 dev_dbg(dsi->dev, "attaching dual-channel device %s\n", in tegra_dsi_host_attach()
1480 dev_name(&device->dev)); in tegra_dsi_host_attach()
1482 err = tegra_dsi_ganged_setup(dsi); in tegra_dsi_host_attach()
1484 dev_err(dsi->dev, "failed to set up ganged mode: %d\n", in tegra_dsi_host_attach()
1494 if (!dsi->master) { in tegra_dsi_host_attach()
1495 struct tegra_output *output = &dsi->output; in tegra_dsi_host_attach()
1497 output->panel = of_drm_find_panel(device->dev.of_node); in tegra_dsi_host_attach()
1498 if (IS_ERR(output->panel)) in tegra_dsi_host_attach()
1499 output->panel = NULL; in tegra_dsi_host_attach()
1501 if (output->panel && output->connector.dev) in tegra_dsi_host_attach()
1502 drm_helper_hpd_irq_event(output->connector.dev); in tegra_dsi_host_attach()
1511 struct tegra_dsi *dsi = host_to_tegra(host); in tegra_dsi_host_detach() local
1512 struct tegra_output *output = &dsi->output; in tegra_dsi_host_detach()
1514 if (output->panel && &device->dev == output->panel->dev) { in tegra_dsi_host_detach()
1515 output->panel = NULL; in tegra_dsi_host_detach()
1517 if (output->connector.dev) in tegra_dsi_host_detach()
1518 drm_helper_hpd_irq_event(output->connector.dev); in tegra_dsi_host_detach()
1530 static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi) in tegra_dsi_ganged_probe() argument
1534 np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0); in tegra_dsi_ganged_probe()
1538 dsi->slave = platform_get_drvdata(gangster); in tegra_dsi_ganged_probe()
1541 if (!dsi->slave) in tegra_dsi_ganged_probe()
1542 return -EPROBE_DEFER; in tegra_dsi_ganged_probe()
1544 dsi->slave->master = dsi; in tegra_dsi_ganged_probe()
1552 struct tegra_dsi *dsi; in tegra_dsi_probe() local
1556 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL); in tegra_dsi_probe()
1557 if (!dsi) in tegra_dsi_probe()
1558 return -ENOMEM; in tegra_dsi_probe()
1560 dsi->output.dev = dsi->dev = &pdev->dev; in tegra_dsi_probe()
1561 dsi->video_fifo_depth = 1920; in tegra_dsi_probe()
1562 dsi->host_fifo_depth = 64; in tegra_dsi_probe()
1564 err = tegra_dsi_ganged_probe(dsi); in tegra_dsi_probe()
1568 err = tegra_output_probe(&dsi->output); in tegra_dsi_probe()
1572 dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD; in tegra_dsi_probe()
1575 * Assume these values by default. When a DSI peripheral driver in tegra_dsi_probe()
1576 * attaches to the DSI host, the parameters will be taken from in tegra_dsi_probe()
1579 dsi->flags = MIPI_DSI_MODE_VIDEO; in tegra_dsi_probe()
1580 dsi->format = MIPI_DSI_FMT_RGB888; in tegra_dsi_probe()
1581 dsi->lanes = 4; in tegra_dsi_probe()
1583 if (!pdev->dev.pm_domain) { in tegra_dsi_probe()
1584 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi"); in tegra_dsi_probe()
1585 if (IS_ERR(dsi->rst)) in tegra_dsi_probe()
1586 return PTR_ERR(dsi->rst); in tegra_dsi_probe()
1589 dsi->clk = devm_clk_get(&pdev->dev, NULL); in tegra_dsi_probe()
1590 if (IS_ERR(dsi->clk)) { in tegra_dsi_probe()
1591 dev_err(&pdev->dev, "cannot get DSI clock\n"); in tegra_dsi_probe()
1592 return PTR_ERR(dsi->clk); in tegra_dsi_probe()
1595 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp"); in tegra_dsi_probe()
1596 if (IS_ERR(dsi->clk_lp)) { in tegra_dsi_probe()
1597 dev_err(&pdev->dev, "cannot get low-power clock\n"); in tegra_dsi_probe()
1598 return PTR_ERR(dsi->clk_lp); in tegra_dsi_probe()
1601 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent"); in tegra_dsi_probe()
1602 if (IS_ERR(dsi->clk_parent)) { in tegra_dsi_probe()
1603 dev_err(&pdev->dev, "cannot get parent clock\n"); in tegra_dsi_probe()
1604 return PTR_ERR(dsi->clk_parent); in tegra_dsi_probe()
1607 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi"); in tegra_dsi_probe()
1608 if (IS_ERR(dsi->vdd)) { in tegra_dsi_probe()
1609 dev_err(&pdev->dev, "cannot get VDD supply\n"); in tegra_dsi_probe()
1610 return PTR_ERR(dsi->vdd); in tegra_dsi_probe()
1613 err = tegra_dsi_setup_clocks(dsi); in tegra_dsi_probe()
1615 dev_err(&pdev->dev, "cannot setup clocks\n"); in tegra_dsi_probe()
1620 dsi->regs = devm_ioremap_resource(&pdev->dev, regs); in tegra_dsi_probe()
1621 if (IS_ERR(dsi->regs)) in tegra_dsi_probe()
1622 return PTR_ERR(dsi->regs); in tegra_dsi_probe()
1624 dsi->mipi = tegra_mipi_request(&pdev->dev, pdev->dev.of_node); in tegra_dsi_probe()
1625 if (IS_ERR(dsi->mipi)) in tegra_dsi_probe()
1626 return PTR_ERR(dsi->mipi); in tegra_dsi_probe()
1628 dsi->host.ops = &tegra_dsi_host_ops; in tegra_dsi_probe()
1629 dsi->host.dev = &pdev->dev; in tegra_dsi_probe()
1631 err = mipi_dsi_host_register(&dsi->host); in tegra_dsi_probe()
1633 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err); in tegra_dsi_probe()
1637 platform_set_drvdata(pdev, dsi); in tegra_dsi_probe()
1638 pm_runtime_enable(&pdev->dev); in tegra_dsi_probe()
1640 INIT_LIST_HEAD(&dsi->client.list); in tegra_dsi_probe()
1641 dsi->client.ops = &dsi_client_ops; in tegra_dsi_probe()
1642 dsi->client.dev = &pdev->dev; in tegra_dsi_probe()
1644 err = host1x_client_register(&dsi->client); in tegra_dsi_probe()
1646 dev_err(&pdev->dev, "failed to register host1x client: %d\n", in tegra_dsi_probe()
1654 mipi_dsi_host_unregister(&dsi->host); in tegra_dsi_probe()
1656 tegra_mipi_free(dsi->mipi); in tegra_dsi_probe()
1662 struct tegra_dsi *dsi = platform_get_drvdata(pdev); in tegra_dsi_remove() local
1665 pm_runtime_disable(&pdev->dev); in tegra_dsi_remove()
1667 err = host1x_client_unregister(&dsi->client); in tegra_dsi_remove()
1669 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", in tegra_dsi_remove()
1674 tegra_output_remove(&dsi->output); in tegra_dsi_remove()
1676 mipi_dsi_host_unregister(&dsi->host); in tegra_dsi_remove()
1677 tegra_mipi_free(dsi->mipi); in tegra_dsi_remove()
1683 { .compatible = "nvidia,tegra210-dsi", },
1684 { .compatible = "nvidia,tegra132-dsi", },
1685 { .compatible = "nvidia,tegra124-dsi", },
1686 { .compatible = "nvidia,tegra114-dsi", },
1693 .name = "tegra-dsi",