Lines Matching +full:0 +full:x042
161 #define DC_CMD_GENERAL_INCR_SYNCPT 0x000
162 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001
164 #define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
165 #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002
166 #define DC_CMD_WIN_A_INCR_SYNCPT 0x008
167 #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009
168 #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a
169 #define DC_CMD_WIN_B_INCR_SYNCPT 0x010
170 #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011
171 #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012
172 #define DC_CMD_WIN_C_INCR_SYNCPT 0x018
173 #define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL 0x019
174 #define DC_CMD_WIN_C_INCR_SYNCPT_ERROR 0x01a
175 #define DC_CMD_CONT_SYNCPT_VSYNC 0x028
177 #define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031
178 #define DC_CMD_DISPLAY_COMMAND 0x032
179 #define DISP_CTRL_MODE_STOP (0 << 5)
183 #define DC_CMD_SIGNAL_RAISE 0x033
184 #define DC_CMD_DISPLAY_POWER_CONTROL 0x036
185 #define PW0_ENABLE (1 << 0)
193 #define DC_CMD_INT_STATUS 0x037
194 #define DC_CMD_INT_MASK 0x038
195 #define DC_CMD_INT_ENABLE 0x039
196 #define DC_CMD_INT_TYPE 0x03a
197 #define DC_CMD_INT_POLARITY 0x03b
198 #define CTXSW_INT (1 << 0)
219 #define DC_CMD_SIGNAL_RAISE1 0x03c
220 #define DC_CMD_SIGNAL_RAISE2 0x03d
221 #define DC_CMD_SIGNAL_RAISE3 0x03e
223 #define DC_CMD_STATE_ACCESS 0x040
224 #define READ_MUX (1 << 0)
227 #define DC_CMD_STATE_CONTROL 0x041
228 #define GENERAL_ACT_REQ (1 << 0)
242 #define DC_CMD_DISPLAY_WINDOW_HEADER 0x042
247 #define DC_CMD_REG_ACT_CONTROL 0x043
249 #define DC_COM_CRC_CONTROL 0x300
251 #define DC_COM_CRC_CONTROL_FULL_FRAME (0 << 2)
254 #define DC_COM_CRC_CONTROL_ENABLE (1 << 0)
255 #define DC_COM_CRC_CHECKSUM 0x301
256 #define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x))
257 #define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
260 #define DC_COM_PIN_OUTPUT_DATA(x) (0x30a + (x))
261 #define DC_COM_PIN_INPUT_ENABLE(x) (0x30e + (x))
262 #define DC_COM_PIN_INPUT_DATA(x) (0x312 + (x))
263 #define DC_COM_PIN_OUTPUT_SELECT(x) (0x314 + (x))
265 #define DC_COM_PIN_MISC_CONTROL 0x31b
266 #define DC_COM_PIN_PM0_CONTROL 0x31c
267 #define DC_COM_PIN_PM0_DUTY_CYCLE 0x31d
268 #define DC_COM_PIN_PM1_CONTROL 0x31e
269 #define DC_COM_PIN_PM1_DUTY_CYCLE 0x31f
271 #define DC_COM_SPI_CONTROL 0x320
272 #define DC_COM_SPI_START_BYTE 0x321
273 #define DC_COM_HSPI_WRITE_DATA_AB 0x322
274 #define DC_COM_HSPI_WRITE_DATA_CD 0x323
275 #define DC_COM_HSPI_CS_DC 0x324
276 #define DC_COM_SCRATCH_REGISTER_A 0x325
277 #define DC_COM_SCRATCH_REGISTER_B 0x326
278 #define DC_COM_GPIO_CTRL 0x327
279 #define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328
280 #define DC_COM_CRC_CHECKSUM_LATCHED 0x329
282 #define DC_COM_RG_UNDERFLOW 0x365
284 #define UNDERFLOW_REPORT_ENABLE (1 << 0)
286 #define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400
291 #define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401
293 #define DC_DISP_DISP_WIN_OPTIONS 0x402
301 #define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
302 #define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24)
303 #define WINDOW_A_THRESHOLD(x) (((x) & 0x7f) << 16)
304 #define WINDOW_B_THRESHOLD(x) (((x) & 0x7f) << 8)
305 #define WINDOW_C_THRESHOLD(x) (((x) & 0xff) << 0)
307 #define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404
308 #define CURSOR_DELAY(x) (((x) & 0x3f) << 24)
309 #define WINDOW_A_DELAY(x) (((x) & 0x3f) << 16)
310 #define WINDOW_B_DELAY(x) (((x) & 0x3f) << 8)
311 #define WINDOW_C_DELAY(x) (((x) & 0x3f) << 0)
313 #define DC_DISP_DISP_TIMING_OPTIONS 0x405
314 #define VSYNC_H_POSITION(x) ((x) & 0xfff)
316 #define DC_DISP_REF_TO_SYNC 0x406
317 #define DC_DISP_SYNC_WIDTH 0x407
318 #define DC_DISP_BACK_PORCH 0x408
319 #define DC_DISP_ACTIVE 0x409
320 #define DC_DISP_FRONT_PORCH 0x40a
321 #define DC_DISP_H_PULSE0_CONTROL 0x40b
322 #define DC_DISP_H_PULSE0_POSITION_A 0x40c
323 #define DC_DISP_H_PULSE0_POSITION_B 0x40d
324 #define DC_DISP_H_PULSE0_POSITION_C 0x40e
325 #define DC_DISP_H_PULSE0_POSITION_D 0x40f
326 #define DC_DISP_H_PULSE1_CONTROL 0x410
327 #define DC_DISP_H_PULSE1_POSITION_A 0x411
328 #define DC_DISP_H_PULSE1_POSITION_B 0x412
329 #define DC_DISP_H_PULSE1_POSITION_C 0x413
330 #define DC_DISP_H_PULSE1_POSITION_D 0x414
331 #define DC_DISP_H_PULSE2_CONTROL 0x415
332 #define DC_DISP_H_PULSE2_POSITION_A 0x416
333 #define DC_DISP_H_PULSE2_POSITION_B 0x417
334 #define DC_DISP_H_PULSE2_POSITION_C 0x418
335 #define DC_DISP_H_PULSE2_POSITION_D 0x419
336 #define DC_DISP_V_PULSE0_CONTROL 0x41a
337 #define DC_DISP_V_PULSE0_POSITION_A 0x41b
338 #define DC_DISP_V_PULSE0_POSITION_B 0x41c
339 #define DC_DISP_V_PULSE0_POSITION_C 0x41d
340 #define DC_DISP_V_PULSE1_CONTROL 0x41e
341 #define DC_DISP_V_PULSE1_POSITION_A 0x41f
342 #define DC_DISP_V_PULSE1_POSITION_B 0x420
343 #define DC_DISP_V_PULSE1_POSITION_C 0x421
344 #define DC_DISP_V_PULSE2_CONTROL 0x422
345 #define DC_DISP_V_PULSE2_POSITION_A 0x423
346 #define DC_DISP_V_PULSE3_CONTROL 0x424
347 #define DC_DISP_V_PULSE3_POSITION_A 0x425
348 #define DC_DISP_M0_CONTROL 0x426
349 #define DC_DISP_M1_CONTROL 0x427
350 #define DC_DISP_DI_CONTROL 0x428
351 #define DC_DISP_PP_CONTROL 0x429
352 #define DC_DISP_PP_SELECT_A 0x42a
353 #define DC_DISP_PP_SELECT_B 0x42b
354 #define DC_DISP_PP_SELECT_C 0x42c
355 #define DC_DISP_PP_SELECT_D 0x42d
357 #define PULSE_MODE_NORMAL (0 << 3)
359 #define PULSE_POLARITY_HIGH (0 << 4)
361 #define PULSE_QUAL_ALWAYS (0 << 6)
364 #define PULSE_LAST_START_A (0 << 8)
373 #define PULSE_START(x) (((x) & 0xfff) << 0)
374 #define PULSE_END(x) (((x) & 0xfff) << 16)
376 #define DC_DISP_DISP_CLOCK_CONTROL 0x42e
377 #define PIXEL_CLK_DIVIDER_PCD1 (0 << 8)
390 #define SHIFT_CLK_DIVIDER(x) ((x) & 0xff)
392 #define DC_DISP_DISP_INTERFACE_CONTROL 0x42f
393 #define DISP_DATA_FORMAT_DF1P1C (0 << 0)
394 #define DISP_DATA_FORMAT_DF1P2C24B (1 << 0)
395 #define DISP_DATA_FORMAT_DF1P2C18B (2 << 0)
396 #define DISP_DATA_FORMAT_DF1P2C16B (3 << 0)
397 #define DISP_DATA_FORMAT_DF2S (4 << 0)
398 #define DISP_DATA_FORMAT_DF3S (5 << 0)
399 #define DISP_DATA_FORMAT_DFSPI (6 << 0)
400 #define DISP_DATA_FORMAT_DF1P3C24B (7 << 0)
401 #define DISP_DATA_FORMAT_DF1P3C18B (8 << 0)
402 #define DISP_ALIGNMENT_MSB (0 << 8)
404 #define DISP_ORDER_RED_BLUE (0 << 9)
407 #define DC_DISP_DISP_COLOR_CONTROL 0x430
408 #define BASE_COLOR_SIZE666 ( 0 << 0)
409 #define BASE_COLOR_SIZE111 ( 1 << 0)
410 #define BASE_COLOR_SIZE222 ( 2 << 0)
411 #define BASE_COLOR_SIZE333 ( 3 << 0)
412 #define BASE_COLOR_SIZE444 ( 4 << 0)
413 #define BASE_COLOR_SIZE555 ( 5 << 0)
414 #define BASE_COLOR_SIZE565 ( 6 << 0)
415 #define BASE_COLOR_SIZE332 ( 7 << 0)
416 #define BASE_COLOR_SIZE888 ( 8 << 0)
417 #define BASE_COLOR_SIZE101010 (10 << 0)
418 #define BASE_COLOR_SIZE121212 (12 << 0)
420 #define DITHER_CONTROL_DISABLE (0 << 8)
423 #define BASE_COLOR_SIZE_MASK (0xf << 0)
424 #define BASE_COLOR_SIZE_666 ( 0 << 0)
425 #define BASE_COLOR_SIZE_111 ( 1 << 0)
426 #define BASE_COLOR_SIZE_222 ( 2 << 0)
427 #define BASE_COLOR_SIZE_333 ( 3 << 0)
428 #define BASE_COLOR_SIZE_444 ( 4 << 0)
429 #define BASE_COLOR_SIZE_555 ( 5 << 0)
430 #define BASE_COLOR_SIZE_565 ( 6 << 0)
431 #define BASE_COLOR_SIZE_332 ( 7 << 0)
432 #define BASE_COLOR_SIZE_888 ( 8 << 0)
433 #define BASE_COLOR_SIZE_101010 ( 10 << 0)
434 #define BASE_COLOR_SIZE_121212 ( 12 << 0)
436 #define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
438 #define SC0_H_QUALIFIER_NONE (1 << 0)
440 #define DC_DISP_DATA_ENABLE_OPTIONS 0x432
441 #define DE_SELECT_ACTIVE_BLANK (0 << 0)
442 #define DE_SELECT_ACTIVE (1 << 0)
443 #define DE_SELECT_ACTIVE_IS (2 << 0)
444 #define DE_CONTROL_ONECLK (0 << 2)
450 #define DC_DISP_SERIAL_INTERFACE_OPTIONS 0x433
451 #define DC_DISP_LCD_SPI_OPTIONS 0x434
452 #define DC_DISP_BORDER_COLOR 0x435
453 #define DC_DISP_COLOR_KEY0_LOWER 0x436
454 #define DC_DISP_COLOR_KEY0_UPPER 0x437
455 #define DC_DISP_COLOR_KEY1_LOWER 0x438
456 #define DC_DISP_COLOR_KEY1_UPPER 0x439
458 #define DC_DISP_CURSOR_FOREGROUND 0x43c
459 #define DC_DISP_CURSOR_BACKGROUND 0x43d
461 #define DC_DISP_CURSOR_START_ADDR 0x43e
462 #define CURSOR_CLIP_DISPLAY (0 << 28)
466 #define CURSOR_SIZE_32x32 (0 << 24)
470 #define DC_DISP_CURSOR_START_ADDR_NS 0x43f
472 #define DC_DISP_CURSOR_POSITION 0x440
473 #define DC_DISP_CURSOR_POSITION_NS 0x441
475 #define DC_DISP_INIT_SEQ_CONTROL 0x442
476 #define DC_DISP_SPI_INIT_SEQ_DATA_A 0x443
477 #define DC_DISP_SPI_INIT_SEQ_DATA_B 0x444
478 #define DC_DISP_SPI_INIT_SEQ_DATA_C 0x445
479 #define DC_DISP_SPI_INIT_SEQ_DATA_D 0x446
481 #define DC_DISP_DC_MCCIF_FIFOCTRL 0x480
482 #define DC_DISP_MCCIF_DISPLAY0A_HYST 0x481
483 #define DC_DISP_MCCIF_DISPLAY0B_HYST 0x482
484 #define DC_DISP_MCCIF_DISPLAY1A_HYST 0x483
485 #define DC_DISP_MCCIF_DISPLAY1B_HYST 0x484
487 #define DC_DISP_DAC_CRT_CTRL 0x4c0
488 #define DC_DISP_DISP_MISC_CONTROL 0x4c1
489 #define DC_DISP_SD_CONTROL 0x4c2
490 #define DC_DISP_SD_CSC_COEFF 0x4c3
491 #define DC_DISP_SD_LUT(x) (0x4c4 + (x))
492 #define DC_DISP_SD_FLICKER_CONTROL 0x4cd
493 #define DC_DISP_DC_PIXEL_COUNT 0x4ce
494 #define DC_DISP_SD_HISTOGRAM(x) (0x4cf + (x))
495 #define DC_DISP_SD_BL_PARAMETERS 0x4d7
496 #define DC_DISP_SD_BL_TF(x) (0x4d8 + (x))
497 #define DC_DISP_SD_BL_CONTROL 0x4dc
498 #define DC_DISP_SD_HW_K_VALUES 0x4dd
499 #define DC_DISP_SD_MAN_K_VALUES 0x4de
501 #define DC_DISP_BLEND_BACKGROUND_COLOR 0x4e4
502 #define BACKGROUND_COLOR_ALPHA(x) (((x) & 0xff) << 24)
503 #define BACKGROUND_COLOR_BLUE(x) (((x) & 0xff) << 16)
504 #define BACKGROUND_COLOR_GREEN(x) (((x) & 0xff) << 8)
505 #define BACKGROUND_COLOR_RED(x) (((x) & 0xff) << 0)
507 #define DC_DISP_INTERLACE_CONTROL 0x4e5
510 #define INTERLACE_ENABLE (1 << 0)
512 #define DC_DISP_CURSOR_START_ADDR_HI 0x4ec
513 #define DC_DISP_BLEND_CURSOR_CONTROL 0x4f1
514 #define CURSOR_MODE_LEGACY (0 << 24)
516 #define CURSOR_DST_BLEND_ZERO (0 << 16)
520 #define CURSOR_SRC_BLEND_K1 (0 << 8)
523 #define CURSOR_ALPHA 0xff
525 #define DC_WIN_CORE_ACT_CONTROL 0x50e
526 #define VCOUNTER (0 << 0)
527 #define HCOUNTER (1 << 0)
529 #define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA 0x543
532 #define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB 0x544
533 #define WATERMARK_MASK 0x1fffffff
535 #define DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER 0x560
536 #define PIPE_METER_INT(x) (((x) & 0xff) << 8)
537 #define PIPE_METER_FRAC(x) (((x) & 0xff) << 0)
539 #define DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG 0x561
540 #define MEMPOOL_ENTRIES(x) (((x) & 0xffff) << 0)
542 #define DC_WIN_CORE_IHUB_WGRP_FETCH_METER 0x562
543 #define SLOTS(x) (((x) & 0xff) << 0)
545 #define DC_WIN_CORE_IHUB_LINEBUF_CONFIG 0x563
546 #define MODE_TWO_LINES (0 << 14)
549 #define DC_WIN_CORE_IHUB_THREAD_GROUP 0x568
550 #define THREAD_NUM_MASK (0x1f << 1)
551 #define THREAD_NUM(x) (((x) & 0x1f) << 1)
552 #define THREAD_GROUP_ENABLE (1 << 0)
554 #define DC_WIN_H_FILTER_P(p) (0x601 + (p))
555 #define DC_WIN_V_FILTER_P(p) (0x619 + (p))
557 #define DC_WIN_CSC_YOF 0x611
558 #define DC_WIN_CSC_KYRGB 0x612
559 #define DC_WIN_CSC_KUR 0x613
560 #define DC_WIN_CSC_KVR 0x614
561 #define DC_WIN_CSC_KUG 0x615
562 #define DC_WIN_CSC_KVG 0x616
563 #define DC_WIN_CSC_KUB 0x617
564 #define DC_WIN_CSC_KVB 0x618
566 #define DC_WIN_WIN_OPTIONS 0x700
567 #define H_DIRECTION (1 << 0)
575 #define DC_WIN_BYTE_SWAP 0x701
576 #define BYTE_SWAP_NOSWAP (0 << 0)
577 #define BYTE_SWAP_SWAP2 (1 << 0)
578 #define BYTE_SWAP_SWAP4 (2 << 0)
579 #define BYTE_SWAP_SWAP4HW (3 << 0)
581 #define DC_WIN_BUFFER_CONTROL 0x702
582 #define BUFFER_CONTROL_HOST (0 << 0)
583 #define BUFFER_CONTROL_VI (1 << 0)
584 #define BUFFER_CONTROL_EPP (2 << 0)
585 #define BUFFER_CONTROL_MPEGE (3 << 0)
586 #define BUFFER_CONTROL_SB2D (4 << 0)
588 #define DC_WIN_COLOR_DEPTH 0x703
589 #define WIN_COLOR_DEPTH_P1 0
626 #define DC_WIN_POSITION 0x704
627 #define H_POSITION(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */
628 #define V_POSITION(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
630 #define DC_WIN_SIZE 0x705
631 #define H_SIZE(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */
632 #define V_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
634 #define DC_WIN_PRESCALED_SIZE 0x706
635 #define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0)
636 #define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */
638 #define DC_WIN_H_INITIAL_DDA 0x707
639 #define DC_WIN_V_INITIAL_DDA 0x708
640 #define DC_WIN_DDA_INC 0x709
641 #define H_DDA_INC(x) (((x) & 0xffff) << 0)
642 #define V_DDA_INC(x) (((x) & 0xffff) << 16)
644 #define DC_WIN_LINE_STRIDE 0x70a
645 #define DC_WIN_BUF_STRIDE 0x70b
646 #define DC_WIN_UV_BUF_STRIDE 0x70c
647 #define DC_WIN_BUFFER_ADDR_MODE 0x70d
648 #define DC_WIN_BUFFER_ADDR_MODE_LINEAR (0 << 0)
649 #define DC_WIN_BUFFER_ADDR_MODE_TILE (1 << 0)
650 #define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV (0 << 16)
653 #define DC_WIN_DV_CONTROL 0x70e
655 #define DC_WIN_BLEND_NOKEY 0x70f
656 #define BLEND_WEIGHT1(x) (((x) & 0xff) << 16)
657 #define BLEND_WEIGHT0(x) (((x) & 0xff) << 8)
659 #define DC_WIN_BLEND_1WIN 0x710
660 #define BLEND_CONTROL_FIX (0 << 2)
662 #define BLEND_COLOR_KEY_NONE (0 << 0)
663 #define BLEND_COLOR_KEY_0 (1 << 0)
664 #define BLEND_COLOR_KEY_1 (2 << 0)
665 #define BLEND_COLOR_KEY_BOTH (3 << 0)
667 #define DC_WIN_BLEND_2WIN_X 0x711
670 #define DC_WIN_BLEND_2WIN_Y 0x712
671 #define DC_WIN_BLEND_3WIN_XY 0x713
673 #define DC_WIN_HP_FETCH_CONTROL 0x714
675 #define DC_WINBUF_START_ADDR 0x800
676 #define DC_WINBUF_START_ADDR_NS 0x801
677 #define DC_WINBUF_START_ADDR_U 0x802
678 #define DC_WINBUF_START_ADDR_U_NS 0x803
679 #define DC_WINBUF_START_ADDR_V 0x804
680 #define DC_WINBUF_START_ADDR_V_NS 0x805
682 #define DC_WINBUF_ADDR_H_OFFSET 0x806
683 #define DC_WINBUF_ADDR_H_OFFSET_NS 0x807
684 #define DC_WINBUF_ADDR_V_OFFSET 0x808
685 #define DC_WINBUF_ADDR_V_OFFSET_NS 0x809
687 #define DC_WINBUF_UFLOW_STATUS 0x80a
688 #define DC_WINBUF_SURFACE_KIND 0x80b
689 #define DC_WINBUF_SURFACE_KIND_PITCH (0 << 0)
690 #define DC_WINBUF_SURFACE_KIND_TILED (1 << 0)
691 #define DC_WINBUF_SURFACE_KIND_BLOCK (2 << 0)
692 #define DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4)
694 #define DC_WINBUF_START_ADDR_HI 0x80d
696 #define DC_WINBUF_CDE_CONTROL 0x82f
697 #define ENABLE_SURFACE (1 << 0)
699 #define DC_WINBUF_AD_UFLOW_STATUS 0xbca
700 #define DC_WINBUF_BD_UFLOW_STATUS 0xdca
701 #define DC_WINBUF_CD_UFLOW_STATUS 0xfca
704 #define DC_DISP_CORE_SOR_SET_CONTROL(x) (0x403 + (x))
705 #define PROTOCOL_MASK (0xf << 8)
706 #define PROTOCOL_SINGLE_TMDS_A (0x1 << 8)
708 #define DC_WIN_CORE_WINDOWGROUP_SET_CONTROL 0x702
709 #define OWNER_MASK (0xf << 0)
710 #define OWNER(x) (((x) & 0xf) << 0)
712 #define DC_WIN_CROPPED_SIZE 0x706
714 #define DC_WIN_PLANAR_STORAGE 0x709
715 #define PITCH(x) (((x) >> 6) & 0x1fff)
717 #define DC_WIN_SET_PARAMS 0x70d
719 #define DEGAMMA_NONE (0 << 13)
723 #define INPUT_RANGE_BYPASS (0 << 10)
726 #define COLOR_SPACE_RGB (0 << 8)
731 #define DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER 0x70e
734 #define VERTICAL_TAPS_2 (1 << 0)
735 #define VERTICAL_TAPS_5 (4 << 0)
737 #define DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE 0x711
740 #define INPUT_SCALER_HBYPASS (1 << 0)
742 #define DC_WIN_BLEND_LAYER_CONTROL 0x716
743 #define COLOR_KEY_NONE (0 << 25)
747 #define K2(x) (((x) & 0xff) << 16)
748 #define K1(x) (((x) & 0xff) << 8)
749 #define WINDOW_LAYER_DEPTH(x) (((x) & 0xff) << 0)
751 #define DC_WIN_BLEND_MATCH_SELECT 0x717
752 #define BLEND_FACTOR_DST_ALPHA_ZERO (0 << 12)
756 #define BLEND_FACTOR_SRC_ALPHA_ZERO (0 << 8)
760 #define BLEND_FACTOR_DST_COLOR_ZERO (0 << 4)
768 #define BLEND_FACTOR_SRC_COLOR_ZERO (0 << 0)
769 #define BLEND_FACTOR_SRC_COLOR_ONE (1 << 0)
770 #define BLEND_FACTOR_SRC_COLOR_K1 (2 << 0)
771 #define BLEND_FACTOR_SRC_COLOR_K1_TIMES_DST (3 << 0)
772 #define BLEND_FACTOR_SRC_COLOR_NEG_K1_TIMES_DST (4 << 0)
773 #define BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC (5 << 0)
775 #define DC_WIN_BLEND_NOMATCH_SELECT 0x718
777 #define DC_WIN_PRECOMP_WGRP_PARAMS 0x724
778 #define SWAP_UV (1 << 0)
780 #define DC_WIN_WINDOW_SET_CONTROL 0x730
783 #define DC_WINBUF_CROPPED_POINT 0x806
784 #define OFFSET_Y(x) (((x) & 0xffff) << 16)
785 #define OFFSET_X(x) (((x) & 0xffff) << 0)