Lines Matching refs:dc
43 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) in tegra_dc_readl_active() argument
47 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
48 value = tegra_dc_readl(dc, offset); in tegra_dc_readl_active()
49 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
72 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); in tegra_plane_offset()
80 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); in tegra_plane_readl()
86 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); in tegra_plane_writel()
89 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev) in tegra_dc_has_output() argument
91 struct device_node *np = dc->dev->of_node; in tegra_dc_has_output()
114 void tegra_dc_commit(struct tegra_dc *dc) in tegra_dc_commit() argument
116 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
117 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); in tegra_dc_commit()
310 struct tegra_dc *dc = plane->dc; in tegra_plane_use_horizontal_filtering() local
315 if (plane->index == 0 && dc->soc->has_win_a_without_filters) in tegra_plane_use_horizontal_filtering()
325 struct tegra_dc *dc = plane->dc; in tegra_plane_use_vertical_filtering() local
330 if (plane->index == 0 && dc->soc->has_win_a_without_filters) in tegra_plane_use_vertical_filtering()
333 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter) in tegra_plane_use_vertical_filtering()
343 struct tegra_dc *dc = plane->dc; in tegra_dc_setup_window() local
416 if (dc->soc->supports_block_linear) { in tegra_dc_setup_window()
522 if (dc->soc->has_legacy_blending) in tegra_dc_setup_window()
616 struct tegra_dc *dc = to_tegra_dc(state->crtc); in tegra_plane_atomic_check() local
635 if (dc->soc->has_legacy_blending) { in tegra_plane_atomic_check()
646 !dc->soc->supports_block_linear) { in tegra_plane_atomic_check()
782 struct tegra_dc *dc) in tegra_primary_plane_create() argument
799 plane->dc = dc; in tegra_primary_plane_create()
801 num_formats = dc->soc->num_primary_formats; in tegra_primary_plane_create()
802 formats = dc->soc->primary_formats; in tegra_primary_plane_create()
803 modifiers = dc->soc->modifiers; in tegra_primary_plane_create()
823 dev_err(dc->dev, "failed to create rotation property: %d\n", in tegra_primary_plane_create()
867 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc); in tegra_cursor_atomic_update() local
898 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); in tegra_cursor_atomic_update()
902 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); in tegra_cursor_atomic_update()
906 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_update()
908 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_update()
910 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); in tegra_cursor_atomic_update()
917 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); in tegra_cursor_atomic_update()
922 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); in tegra_cursor_atomic_update()
928 struct tegra_dc *dc; in tegra_cursor_atomic_disable() local
935 dc = to_tegra_dc(old_state->crtc); in tegra_cursor_atomic_disable()
937 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_disable()
939 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_cursor_atomic_disable()
951 struct tegra_dc *dc) in tegra_dc_cursor_plane_create() argument
971 plane->dc = dc; in tegra_dc_cursor_plane_create()
1068 struct tegra_dc *dc, in tegra_dc_overlay_plane_create() argument
1085 plane->dc = dc; in tegra_dc_overlay_plane_create()
1087 num_formats = dc->soc->num_overlay_formats; in tegra_dc_overlay_plane_create()
1088 formats = dc->soc->overlay_formats; in tegra_dc_overlay_plane_create()
1113 dev_err(dc->dev, "failed to create rotation property: %d\n", in tegra_dc_overlay_plane_create()
1120 struct tegra_dc *dc) in tegra_dc_add_shared_planes() argument
1125 for (i = 0; i < dc->soc->num_wgrps; i++) { in tegra_dc_add_shared_planes()
1126 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; in tegra_dc_add_shared_planes()
1128 if (wgrp->dc == dc->pipe) { in tegra_dc_add_shared_planes()
1132 plane = tegra_shared_plane_create(drm, dc, in tegra_dc_add_shared_planes()
1154 struct tegra_dc *dc) in tegra_dc_add_planes() argument
1161 primary = tegra_primary_plane_create(drm, dc); in tegra_dc_add_planes()
1165 if (dc->soc->supports_cursor) in tegra_dc_add_planes()
1171 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i, in tegra_dc_add_planes()
1448 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_regs() local
1452 drm_modeset_lock(&dc->base.mutex, NULL); in tegra_dc_show_regs()
1454 if (!dc->base.state->active) { in tegra_dc_show_regs()
1463 offset, tegra_dc_readl(dc, offset)); in tegra_dc_show_regs()
1467 drm_modeset_unlock(&dc->base.mutex); in tegra_dc_show_regs()
1474 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_crc() local
1478 drm_modeset_lock(&dc->base.mutex, NULL); in tegra_dc_show_crc()
1480 if (!dc->base.state->active) { in tegra_dc_show_crc()
1486 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL); in tegra_dc_show_crc()
1487 tegra_dc_commit(dc); in tegra_dc_show_crc()
1489 drm_crtc_wait_one_vblank(&dc->base); in tegra_dc_show_crc()
1490 drm_crtc_wait_one_vblank(&dc->base); in tegra_dc_show_crc()
1492 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM); in tegra_dc_show_crc()
1495 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL); in tegra_dc_show_crc()
1498 drm_modeset_unlock(&dc->base.mutex); in tegra_dc_show_crc()
1505 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_stats() local
1507 seq_printf(s, "frames: %lu\n", dc->stats.frames); in tegra_dc_show_stats()
1508 seq_printf(s, "vblank: %lu\n", dc->stats.vblank); in tegra_dc_show_stats()
1509 seq_printf(s, "underflow: %lu\n", dc->stats.underflow); in tegra_dc_show_stats()
1510 seq_printf(s, "overflow: %lu\n", dc->stats.overflow); in tegra_dc_show_stats()
1526 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_late_register() local
1534 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_dc_late_register()
1536 if (!dc->debugfs_files) in tegra_dc_late_register()
1540 dc->debugfs_files[i].data = dc; in tegra_dc_late_register()
1542 drm_debugfs_create_files(dc->debugfs_files, count, root, minor); in tegra_dc_late_register()
1551 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_early_unregister() local
1553 drm_debugfs_remove_files(dc->debugfs_files, count, minor); in tegra_dc_early_unregister()
1554 kfree(dc->debugfs_files); in tegra_dc_early_unregister()
1555 dc->debugfs_files = NULL; in tegra_dc_early_unregister()
1560 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_get_vblank_counter() local
1563 if (dc->syncpt && !dc->soc->has_nvdisplay) in tegra_dc_get_vblank_counter()
1564 return host1x_syncpt_read(dc->syncpt); in tegra_dc_get_vblank_counter()
1567 return (u32)drm_crtc_vblank_count(&dc->base); in tegra_dc_get_vblank_counter()
1572 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_enable_vblank() local
1575 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
1577 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_enable_vblank()
1584 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_dc_disable_vblank() local
1587 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
1589 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_dc_disable_vblank()
1606 static int tegra_dc_set_timings(struct tegra_dc *dc, in tegra_dc_set_timings() argument
1613 if (!dc->soc->has_nvdisplay) { in tegra_dc_set_timings()
1614 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); in tegra_dc_set_timings()
1617 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); in tegra_dc_set_timings()
1622 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); in tegra_dc_set_timings()
1626 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); in tegra_dc_set_timings()
1630 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); in tegra_dc_set_timings()
1633 tegra_dc_writel(dc, value, DC_DISP_ACTIVE); in tegra_dc_set_timings()
1650 int tegra_dc_state_setup_clock(struct tegra_dc *dc, in tegra_dc_state_setup_clock() argument
1657 if (!clk_has_parent(dc->clk, clk)) in tegra_dc_state_setup_clock()
1667 static void tegra_dc_commit_state(struct tegra_dc *dc, in tegra_dc_commit_state() argument
1673 err = clk_set_parent(dc->clk, state->clk); in tegra_dc_commit_state()
1675 dev_err(dc->dev, "failed to set parent clock: %d\n", err); in tegra_dc_commit_state()
1688 dev_err(dc->dev, in tegra_dc_commit_state()
1693 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), in tegra_dc_commit_state()
1697 if (!dc->soc->has_nvdisplay) { in tegra_dc_commit_state()
1699 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); in tegra_dc_commit_state()
1702 err = clk_set_rate(dc->clk, state->pclk); in tegra_dc_commit_state()
1704 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n", in tegra_dc_commit_state()
1705 dc->clk, state->pclk, err); in tegra_dc_commit_state()
1708 static void tegra_dc_stop(struct tegra_dc *dc) in tegra_dc_stop() argument
1713 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); in tegra_dc_stop()
1715 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); in tegra_dc_stop()
1717 tegra_dc_commit(dc); in tegra_dc_stop()
1720 static bool tegra_dc_idle(struct tegra_dc *dc) in tegra_dc_idle() argument
1724 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND); in tegra_dc_idle()
1729 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) in tegra_dc_wait_idle() argument
1734 if (tegra_dc_idle(dc)) in tegra_dc_wait_idle()
1740 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n"); in tegra_dc_wait_idle()
1747 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_atomic_disable() local
1751 if (!tegra_dc_idle(dc)) { in tegra_crtc_atomic_disable()
1752 tegra_dc_stop(dc); in tegra_crtc_atomic_disable()
1758 tegra_dc_wait_idle(dc, 100); in tegra_crtc_atomic_disable()
1777 if (dc->rgb) { in tegra_crtc_atomic_disable()
1778 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_disable()
1781 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_disable()
1784 tegra_dc_stats_reset(&dc->stats); in tegra_crtc_atomic_disable()
1796 err = host1x_client_suspend(&dc->client); in tegra_crtc_atomic_disable()
1798 dev_err(dc->dev, "failed to suspend: %d\n", err); in tegra_crtc_atomic_disable()
1806 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_atomic_enable() local
1810 err = host1x_client_resume(&dc->client); in tegra_crtc_atomic_enable()
1812 dev_err(dc->dev, "failed to resume: %d\n", err); in tegra_crtc_atomic_enable()
1817 if (dc->syncpt) { in tegra_crtc_atomic_enable()
1818 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable; in tegra_crtc_atomic_enable()
1820 if (dc->soc->has_nvdisplay) in tegra_crtc_atomic_enable()
1826 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); in tegra_crtc_atomic_enable()
1829 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC); in tegra_crtc_atomic_enable()
1832 if (dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
1835 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); in tegra_crtc_atomic_enable()
1842 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); in tegra_crtc_atomic_enable()
1846 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); in tegra_crtc_atomic_enable()
1849 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_crtc_atomic_enable()
1851 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_crtc_atomic_enable()
1855 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); in tegra_crtc_atomic_enable()
1859 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); in tegra_crtc_atomic_enable()
1864 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); in tegra_crtc_atomic_enable()
1868 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); in tegra_crtc_atomic_enable()
1872 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); in tegra_crtc_atomic_enable()
1876 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); in tegra_crtc_atomic_enable()
1879 if (dc->soc->supports_background_color) in tegra_crtc_atomic_enable()
1880 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR); in tegra_crtc_atomic_enable()
1882 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); in tegra_crtc_atomic_enable()
1885 tegra_dc_commit_state(dc, state); in tegra_crtc_atomic_enable()
1888 tegra_dc_set_timings(dc, mode); in tegra_crtc_atomic_enable()
1891 if (dc->soc->supports_interlacing) { in tegra_crtc_atomic_enable()
1892 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); in tegra_crtc_atomic_enable()
1894 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); in tegra_crtc_atomic_enable()
1897 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); in tegra_crtc_atomic_enable()
1900 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); in tegra_crtc_atomic_enable()
1902 if (!dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
1903 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_enable()
1906 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); in tegra_crtc_atomic_enable()
1910 if (dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
1912 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW); in tegra_crtc_atomic_enable()
1915 tegra_dc_commit(dc); in tegra_crtc_atomic_enable()
1943 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_crtc_atomic_flush() local
1947 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
1948 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
1951 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
1952 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); in tegra_crtc_atomic_flush()
1964 struct tegra_dc *dc = data; in tegra_dc_irq() local
1967 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); in tegra_dc_irq()
1968 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); in tegra_dc_irq()
1974 dc->stats.frames++; in tegra_dc_irq()
1981 drm_crtc_handle_vblank(&dc->base); in tegra_dc_irq()
1982 dc->stats.vblank++; in tegra_dc_irq()
1989 dc->stats.underflow++; in tegra_dc_irq()
1996 dc->stats.overflow++; in tegra_dc_irq()
2000 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__); in tegra_dc_irq()
2001 dc->stats.underflow++; in tegra_dc_irq()
2007 static bool tegra_dc_has_window_groups(struct tegra_dc *dc) in tegra_dc_has_window_groups() argument
2011 if (!dc->soc->wgrps) in tegra_dc_has_window_groups()
2014 for (i = 0; i < dc->soc->num_wgrps; i++) { in tegra_dc_has_window_groups()
2015 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; in tegra_dc_has_window_groups()
2017 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0) in tegra_dc_has_window_groups()
2028 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_init() local
2039 if (!tegra_dc_has_window_groups(dc)) in tegra_dc_init()
2048 if (dc->soc->has_nvdisplay) in tegra_dc_init()
2051 dc->syncpt = host1x_syncpt_request(client, flags); in tegra_dc_init()
2052 if (!dc->syncpt) in tegra_dc_init()
2053 dev_warn(dc->dev, "failed to allocate syncpoint\n"); in tegra_dc_init()
2061 if (dc->soc->wgrps) in tegra_dc_init()
2062 primary = tegra_dc_add_shared_planes(drm, dc); in tegra_dc_init()
2064 primary = tegra_dc_add_planes(drm, dc); in tegra_dc_init()
2071 if (dc->soc->supports_cursor) { in tegra_dc_init()
2072 cursor = tegra_dc_cursor_plane_create(drm, dc); in tegra_dc_init()
2079 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true); in tegra_dc_init()
2086 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, in tegra_dc_init()
2091 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); in tegra_dc_init()
2097 if (dc->soc->pitch_align > tegra->pitch_align) in tegra_dc_init()
2098 tegra->pitch_align = dc->soc->pitch_align; in tegra_dc_init()
2100 err = tegra_dc_rgb_init(drm, dc); in tegra_dc_init()
2102 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); in tegra_dc_init()
2106 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, in tegra_dc_init()
2107 dev_name(dc->dev), dc); in tegra_dc_init()
2109 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, in tegra_dc_init()
2130 host1x_syncpt_free(dc->syncpt); in tegra_dc_init()
2137 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_exit() local
2140 if (!tegra_dc_has_window_groups(dc)) in tegra_dc_exit()
2146 devm_free_irq(dc->dev, dc->irq, dc); in tegra_dc_exit()
2148 err = tegra_dc_rgb_exit(dc); in tegra_dc_exit()
2150 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); in tegra_dc_exit()
2155 host1x_syncpt_free(dc->syncpt); in tegra_dc_exit()
2162 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_runtime_suspend() local
2166 err = reset_control_assert(dc->rst); in tegra_dc_runtime_suspend()
2172 if (dc->soc->has_powergate) in tegra_dc_runtime_suspend()
2173 tegra_powergate_power_off(dc->powergate); in tegra_dc_runtime_suspend()
2175 clk_disable_unprepare(dc->clk); in tegra_dc_runtime_suspend()
2183 struct tegra_dc *dc = host1x_client_to_dc(client); in tegra_dc_runtime_resume() local
2193 if (dc->soc->has_powergate) { in tegra_dc_runtime_resume()
2194 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, in tegra_dc_runtime_resume()
2195 dc->rst); in tegra_dc_runtime_resume()
2201 err = clk_prepare_enable(dc->clk); in tegra_dc_runtime_resume()
2207 err = reset_control_deassert(dc->rst); in tegra_dc_runtime_resume()
2217 clk_disable_unprepare(dc->clk); in tegra_dc_runtime_resume()
2328 .dc = 0,
2333 .dc = 1,
2338 .dc = 1,
2343 .dc = 2,
2348 .dc = 2,
2353 .dc = 2,
2376 .dc = 0,
2381 .dc = 1,
2386 .dc = 1,
2391 .dc = 2,
2396 .dc = 2,
2401 .dc = 2,
2449 static int tegra_dc_parse_dt(struct tegra_dc *dc) in tegra_dc_parse_dt() argument
2455 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); in tegra_dc_parse_dt()
2457 dev_err(dc->dev, "missing \"nvidia,head\" property\n"); in tegra_dc_parse_dt()
2472 if (np == dc->dev->of_node) { in tegra_dc_parse_dt()
2481 dc->pipe = value; in tegra_dc_parse_dt()
2488 struct tegra_dc *dc = dev_get_drvdata(dev); in tegra_dc_match_by_pipe() local
2491 return dc->pipe == pipe; in tegra_dc_match_by_pipe()
2494 static int tegra_dc_couple(struct tegra_dc *dc) in tegra_dc_couple() argument
2501 if (dc->soc->coupled_pm && dc->pipe == 1) { in tegra_dc_couple()
2506 partner = driver_find_device(dc->dev->driver, NULL, NULL, in tegra_dc_couple()
2511 link = device_link_add(dc->dev, partner, flags); in tegra_dc_couple()
2513 dev_err(dc->dev, "failed to link controllers\n"); in tegra_dc_couple()
2517 dev_dbg(dc->dev, "coupled to %s\n", dev_name(partner)); in tegra_dc_couple()
2525 struct tegra_dc *dc; in tegra_dc_probe() local
2528 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); in tegra_dc_probe()
2529 if (!dc) in tegra_dc_probe()
2532 dc->soc = of_device_get_match_data(&pdev->dev); in tegra_dc_probe()
2534 INIT_LIST_HEAD(&dc->list); in tegra_dc_probe()
2535 dc->dev = &pdev->dev; in tegra_dc_probe()
2537 err = tegra_dc_parse_dt(dc); in tegra_dc_probe()
2541 err = tegra_dc_couple(dc); in tegra_dc_probe()
2545 dc->clk = devm_clk_get(&pdev->dev, NULL); in tegra_dc_probe()
2546 if (IS_ERR(dc->clk)) { in tegra_dc_probe()
2548 return PTR_ERR(dc->clk); in tegra_dc_probe()
2551 dc->rst = devm_reset_control_get(&pdev->dev, "dc"); in tegra_dc_probe()
2552 if (IS_ERR(dc->rst)) { in tegra_dc_probe()
2554 return PTR_ERR(dc->rst); in tegra_dc_probe()
2558 err = clk_prepare_enable(dc->clk); in tegra_dc_probe()
2564 err = reset_control_assert(dc->rst); in tegra_dc_probe()
2570 clk_disable_unprepare(dc->clk); in tegra_dc_probe()
2572 if (dc->soc->has_powergate) { in tegra_dc_probe()
2573 if (dc->pipe == 0) in tegra_dc_probe()
2574 dc->powergate = TEGRA_POWERGATE_DIS; in tegra_dc_probe()
2576 dc->powergate = TEGRA_POWERGATE_DISB; in tegra_dc_probe()
2578 tegra_powergate_power_off(dc->powergate); in tegra_dc_probe()
2581 dc->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_dc_probe()
2582 if (IS_ERR(dc->regs)) in tegra_dc_probe()
2583 return PTR_ERR(dc->regs); in tegra_dc_probe()
2585 dc->irq = platform_get_irq(pdev, 0); in tegra_dc_probe()
2586 if (dc->irq < 0) in tegra_dc_probe()
2589 err = tegra_dc_rgb_probe(dc); in tegra_dc_probe()
2596 dev_printk(level, dc->dev, "failed to probe RGB output: %d\n", in tegra_dc_probe()
2601 platform_set_drvdata(pdev, dc); in tegra_dc_probe()
2604 INIT_LIST_HEAD(&dc->client.list); in tegra_dc_probe()
2605 dc->client.ops = &dc_client_ops; in tegra_dc_probe()
2606 dc->client.dev = &pdev->dev; in tegra_dc_probe()
2608 err = host1x_client_register(&dc->client); in tegra_dc_probe()
2619 tegra_dc_rgb_remove(dc); in tegra_dc_probe()
2626 struct tegra_dc *dc = platform_get_drvdata(pdev); in tegra_dc_remove() local
2629 err = host1x_client_unregister(&dc->client); in tegra_dc_remove()
2636 err = tegra_dc_rgb_remove(dc); in tegra_dc_remove()