Lines Matching +full:lvds +full:- +full:alt
1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
47 drm_connector_list_iter_begin(encoder->dev, &iter); in sun4i_tcon_get_connector()
49 if (connector->encoder == encoder) { in sun4i_tcon_get_connector()
65 return -EINVAL; in sun4i_tcon_get_pixel_depth()
67 info = &connector->display_info; in sun4i_tcon_get_pixel_depth()
68 if (info->num_bus_formats != 1) in sun4i_tcon_get_pixel_depth()
69 return -EINVAL; in sun4i_tcon_get_pixel_depth()
71 switch (info->bus_formats[0]) { in sun4i_tcon_get_pixel_depth()
80 return -EINVAL; in sun4i_tcon_get_pixel_depth()
90 WARN_ON(!tcon->quirks->has_channel_0); in sun4i_tcon_channel_set_status()
91 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon_channel_set_status()
94 clk = tcon->dclk; in sun4i_tcon_channel_set_status()
97 WARN_ON(!tcon->quirks->has_channel_1); in sun4i_tcon_channel_set_status()
98 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon_channel_set_status()
101 clk = tcon->sclk1; in sun4i_tcon_channel_set_status()
120 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun4i_tcon_setup_lvds_phy()
129 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG, in sun4i_tcon_setup_lvds_phy()
133 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG, in sun4i_tcon_setup_lvds_phy()
136 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun4i_tcon_setup_lvds_phy()
146 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
153 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
158 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
167 regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun6i_tcon_setup_lvds_phy()
177 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, in sun4i_tcon_lvds_set_status()
180 if (tcon->quirks->setup_lvds_phy) in sun4i_tcon_lvds_set_status()
181 tcon->quirks->setup_lvds_phy(tcon, encoder); in sun4i_tcon_lvds_set_status()
183 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, in sun4i_tcon_lvds_set_status()
195 switch (encoder->encoder_type) { in sun4i_tcon_set_status()
215 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon_set_status()
238 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val); in sun4i_tcon_enable_vblank()
250 struct sun4i_drv *drv = drm->dev_private; in sun4i_get_tcon0()
253 list_for_each_entry(tcon, &drv->tcon_list, list) in sun4i_get_tcon0()
254 if (tcon->id == 0) in sun4i_get_tcon0()
257 dev_warn(drm->dev, in sun4i_get_tcon0()
266 int ret = -ENOTSUPP; in sun4i_tcon_set_mux()
268 if (tcon->quirks->set_mux) in sun4i_tcon_set_mux()
269 ret = tcon->quirks->set_mux(tcon, encoder); in sun4i_tcon_set_mux()
272 encoder->name, encoder->crtc->name, ret); in sun4i_tcon_set_mux()
278 int delay = mode->vtotal - mode->vdisplay; in sun4i_tcon_get_clk_delay()
280 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in sun4i_tcon_get_clk_delay()
284 delay -= 2; in sun4i_tcon_get_clk_delay()
297 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); in sun4i_tcon0_mode_set_common()
300 regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, in sun4i_tcon0_mode_set_common()
301 SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | in sun4i_tcon0_mode_set_common()
302 SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); in sun4i_tcon0_mode_set_common()
321 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PR_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
322 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PG_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
323 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PB_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
324 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LR_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
325 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LG_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
326 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LB_REG, 0x11111111); in sun4i_tcon0_mode_set_dithering()
327 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL0_REG, 0x01010000); in sun4i_tcon0_mode_set_dithering()
328 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL1_REG, 0x15151111); in sun4i_tcon0_mode_set_dithering()
329 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL2_REG, 0x57575555); in sun4i_tcon0_mode_set_dithering()
330 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL3_REG, 0x7f7f7777); in sun4i_tcon0_mode_set_dithering()
333 if (connector->display_info.bpc == 6) in sun4i_tcon0_mode_set_dithering()
336 if (connector->display_info.num_bus_formats == 1) in sun4i_tcon0_mode_set_dithering()
337 bus_format = connector->display_info.bus_formats[0]; in sun4i_tcon0_mode_set_dithering()
354 regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val); in sun4i_tcon0_mode_set_dithering()
363 struct mipi_dsi_device *device = dsi->device; in sun4i_tcon0_mode_set_cpu()
364 u8 bpp = mipi_dsi_pixel_format_to_bpp(device->format); in sun4i_tcon0_mode_set_cpu()
365 u8 lanes = device->lanes; in sun4i_tcon0_mode_set_cpu()
369 tcon->dclk_min_div = SUN6I_DSI_TCON_DIV; in sun4i_tcon0_mode_set_cpu()
370 tcon->dclk_max_div = SUN6I_DSI_TCON_DIV; in sun4i_tcon0_mode_set_cpu()
377 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon0_mode_set_cpu()
381 regmap_write(tcon->regs, SUN4I_TCON_ECC_FIFO_REG, in sun4i_tcon0_mode_set_cpu()
384 regmap_write(tcon->regs, SUN4I_TCON0_CPU_IF_REG, in sun4i_tcon0_mode_set_cpu()
396 regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div); in sun4i_tcon0_mode_set_cpu()
398 block_space = mode->htotal * bpp / (tcon_div * lanes); in sun4i_tcon0_mode_set_cpu()
399 block_space -= mode->hdisplay + 40; in sun4i_tcon0_mode_set_cpu()
401 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG, in sun4i_tcon0_mode_set_cpu()
403 SUN4I_TCON0_CPU_TRI0_BLOCK_SIZE(mode->hdisplay)); in sun4i_tcon0_mode_set_cpu()
405 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI1_REG, in sun4i_tcon0_mode_set_cpu()
406 SUN4I_TCON0_CPU_TRI1_BLOCK_NUM(mode->vdisplay)); in sun4i_tcon0_mode_set_cpu()
408 start_delay = (mode->crtc_vtotal - mode->crtc_vdisplay - 10 - 1); in sun4i_tcon0_mode_set_cpu()
409 start_delay = start_delay * mode->crtc_htotal * 149; in sun4i_tcon0_mode_set_cpu()
410 start_delay = start_delay / (mode->crtc_clock / 1000) / 8; in sun4i_tcon0_mode_set_cpu()
411 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI2_REG, in sun4i_tcon0_mode_set_cpu()
419 regmap_write(tcon->regs, SUN4I_TCON_SAFE_PERIOD_REG, in sun4i_tcon0_mode_set_cpu()
424 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, in sun4i_tcon0_mode_set_cpu()
436 WARN_ON(!tcon->quirks->has_channel_0); in sun4i_tcon0_mode_set_lvds()
438 tcon->dclk_min_div = 7; in sun4i_tcon0_mode_set_lvds()
439 tcon->dclk_max_div = 7; in sun4i_tcon0_mode_set_lvds()
447 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon0_mode_set_lvds()
455 bp = mode->crtc_htotal - mode->crtc_hsync_start; in sun4i_tcon0_mode_set_lvds()
457 mode->crtc_htotal, bp); in sun4i_tcon0_mode_set_lvds()
460 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG, in sun4i_tcon0_mode_set_lvds()
461 SUN4I_TCON0_BASIC1_H_TOTAL(mode->htotal) | in sun4i_tcon0_mode_set_lvds()
468 bp = mode->crtc_vtotal - mode->crtc_vsync_start; in sun4i_tcon0_mode_set_lvds()
470 mode->crtc_vtotal, bp); in sun4i_tcon0_mode_set_lvds()
473 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, in sun4i_tcon0_mode_set_lvds()
474 SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) | in sun4i_tcon0_mode_set_lvds()
483 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg); in sun4i_tcon0_mode_set_lvds()
486 if (!(mode->flags & DRM_MODE_FLAG_PHSYNC)) in sun4i_tcon0_mode_set_lvds()
489 if (!(mode->flags & DRM_MODE_FLAG_PVSYNC)) in sun4i_tcon0_mode_set_lvds()
492 regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val); in sun4i_tcon0_mode_set_lvds()
495 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon0_mode_set_lvds()
500 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0xe0000000); in sun4i_tcon0_mode_set_lvds()
508 const struct drm_display_info *info = &connector->display_info; in sun4i_tcon0_mode_set_rgb()
513 WARN_ON(!tcon->quirks->has_channel_0); in sun4i_tcon0_mode_set_rgb()
515 tcon->dclk_min_div = tcon->quirks->dclk_min_div; in sun4i_tcon0_mode_set_rgb()
516 tcon->dclk_max_div = 127; in sun4i_tcon0_mode_set_rgb()
524 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon0_mode_set_rgb()
532 bp = mode->crtc_htotal - mode->crtc_hsync_start; in sun4i_tcon0_mode_set_rgb()
534 mode->crtc_htotal, bp); in sun4i_tcon0_mode_set_rgb()
537 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG, in sun4i_tcon0_mode_set_rgb()
538 SUN4I_TCON0_BASIC1_H_TOTAL(mode->crtc_htotal) | in sun4i_tcon0_mode_set_rgb()
545 bp = mode->crtc_vtotal - mode->crtc_vsync_start; in sun4i_tcon0_mode_set_rgb()
547 mode->crtc_vtotal, bp); in sun4i_tcon0_mode_set_rgb()
550 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, in sun4i_tcon0_mode_set_rgb()
551 SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) | in sun4i_tcon0_mode_set_rgb()
555 hsync = mode->crtc_hsync_end - mode->crtc_hsync_start; in sun4i_tcon0_mode_set_rgb()
556 vsync = mode->crtc_vsync_end - mode->crtc_vsync_start; in sun4i_tcon0_mode_set_rgb()
558 regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG, in sun4i_tcon0_mode_set_rgb()
563 if (mode->flags & DRM_MODE_FLAG_PHSYNC) in sun4i_tcon0_mode_set_rgb()
566 if (mode->flags & DRM_MODE_FLAG_PVSYNC) in sun4i_tcon0_mode_set_rgb()
569 if (info->bus_flags & DRM_BUS_FLAG_DE_LOW) in sun4i_tcon0_mode_set_rgb()
587 if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE) in sun4i_tcon0_mode_set_rgb()
588 clk_set_phase(tcon->dclk, 240); in sun4i_tcon0_mode_set_rgb()
590 if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) in sun4i_tcon0_mode_set_rgb()
591 clk_set_phase(tcon->dclk, 0); in sun4i_tcon0_mode_set_rgb()
593 regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG, in sun4i_tcon0_mode_set_rgb()
600 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon0_mode_set_rgb()
605 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0); in sun4i_tcon0_mode_set_rgb()
615 WARN_ON(!tcon->quirks->has_channel_1); in sun4i_tcon1_mode_set()
618 clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000); in sun4i_tcon1_mode_set()
622 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon1_mode_set()
627 if (mode->flags & DRM_MODE_FLAG_INTERLACE) in sun4i_tcon1_mode_set()
631 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon1_mode_set()
636 regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG, in sun4i_tcon1_mode_set()
637 SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay) | in sun4i_tcon1_mode_set()
638 SUN4I_TCON1_BASIC0_Y(mode->crtc_vdisplay)); in sun4i_tcon1_mode_set()
641 regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG, in sun4i_tcon1_mode_set()
642 SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay) | in sun4i_tcon1_mode_set()
643 SUN4I_TCON1_BASIC1_Y(mode->crtc_vdisplay)); in sun4i_tcon1_mode_set()
646 regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG, in sun4i_tcon1_mode_set()
647 SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay) | in sun4i_tcon1_mode_set()
648 SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay)); in sun4i_tcon1_mode_set()
651 bp = mode->crtc_htotal - mode->crtc_hsync_start; in sun4i_tcon1_mode_set()
653 mode->htotal, bp); in sun4i_tcon1_mode_set()
654 regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG, in sun4i_tcon1_mode_set()
655 SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) | in sun4i_tcon1_mode_set()
658 bp = mode->crtc_vtotal - mode->crtc_vsync_start; in sun4i_tcon1_mode_set()
660 mode->crtc_vtotal, bp); in sun4i_tcon1_mode_set()
675 vtotal = mode->vtotal; in sun4i_tcon1_mode_set()
676 if (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) in sun4i_tcon1_mode_set()
680 regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG, in sun4i_tcon1_mode_set()
685 hsync = mode->crtc_hsync_end - mode->crtc_hsync_start; in sun4i_tcon1_mode_set()
686 vsync = mode->crtc_vsync_end - mode->crtc_vsync_start; in sun4i_tcon1_mode_set()
688 regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG, in sun4i_tcon1_mode_set()
693 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon1_mode_set()
702 switch (encoder->encoder_type) { in sun4i_tcon_mode_set()
730 spin_lock_irqsave(&dev->event_lock, flags); in sun4i_tcon_finish_page_flip()
731 if (scrtc->event) { in sun4i_tcon_finish_page_flip()
732 drm_crtc_send_vblank_event(&scrtc->crtc, scrtc->event); in sun4i_tcon_finish_page_flip()
733 drm_crtc_vblank_put(&scrtc->crtc); in sun4i_tcon_finish_page_flip()
734 scrtc->event = NULL; in sun4i_tcon_finish_page_flip()
736 spin_unlock_irqrestore(&dev->event_lock, flags); in sun4i_tcon_finish_page_flip()
742 struct drm_device *drm = tcon->drm; in sun4i_tcon_handler()
743 struct sun4i_crtc *scrtc = tcon->crtc; in sun4i_tcon_handler()
744 struct sunxi_engine *engine = scrtc->engine; in sun4i_tcon_handler()
747 regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status); in sun4i_tcon_handler()
754 drm_crtc_handle_vblank(&scrtc->crtc); in sun4i_tcon_handler()
758 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, in sun4i_tcon_handler()
764 if (engine->ops->vblank_quirk) in sun4i_tcon_handler()
765 engine->ops->vblank_quirk(engine); in sun4i_tcon_handler()
773 tcon->clk = devm_clk_get(dev, "ahb"); in sun4i_tcon_init_clocks()
774 if (IS_ERR(tcon->clk)) { in sun4i_tcon_init_clocks()
776 return PTR_ERR(tcon->clk); in sun4i_tcon_init_clocks()
778 clk_prepare_enable(tcon->clk); in sun4i_tcon_init_clocks()
780 if (tcon->quirks->has_channel_0) { in sun4i_tcon_init_clocks()
781 tcon->sclk0 = devm_clk_get(dev, "tcon-ch0"); in sun4i_tcon_init_clocks()
782 if (IS_ERR(tcon->sclk0)) { in sun4i_tcon_init_clocks()
784 return PTR_ERR(tcon->sclk0); in sun4i_tcon_init_clocks()
787 clk_prepare_enable(tcon->sclk0); in sun4i_tcon_init_clocks()
789 if (tcon->quirks->has_channel_1) { in sun4i_tcon_init_clocks()
790 tcon->sclk1 = devm_clk_get(dev, "tcon-ch1"); in sun4i_tcon_init_clocks()
791 if (IS_ERR(tcon->sclk1)) { in sun4i_tcon_init_clocks()
793 return PTR_ERR(tcon->sclk1); in sun4i_tcon_init_clocks()
802 clk_disable_unprepare(tcon->sclk0); in sun4i_tcon_free_clocks()
803 clk_disable_unprepare(tcon->clk); in sun4i_tcon_free_clocks()
845 tcon->regs = devm_regmap_init_mmio(dev, regs, in sun4i_tcon_init_regmap()
847 if (IS_ERR(tcon->regs)) { in sun4i_tcon_init_regmap()
849 return PTR_ERR(tcon->regs); in sun4i_tcon_init_regmap()
853 regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0); in sun4i_tcon_init_regmap()
854 regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0); in sun4i_tcon_init_regmap()
855 regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0); in sun4i_tcon_init_regmap()
858 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0); in sun4i_tcon_init_regmap()
859 regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0); in sun4i_tcon_init_regmap()
885 struct sunxi_engine *engine = ERR_PTR(-EINVAL); in sun4i_tcon_find_engine_traverse()
890 return ERR_PTR(-EINVAL); in sun4i_tcon_find_engine_traverse()
914 list_for_each_entry(engine, &drv->engine_list, list) in sun4i_tcon_find_engine_traverse()
915 if (remote == engine->node) in sun4i_tcon_find_engine_traverse()
929 reg -= 1; in sun4i_tcon_find_engine_traverse()
957 int ret = -EINVAL; in sun4i_tcon_of_get_id_from_port()
988 list_for_each_entry(engine, &drv->engine_list, list) in sun4i_tcon_get_engine_by_id()
989 if (engine->id == id) in sun4i_tcon_get_engine_by_id()
992 return ERR_PTR(-EINVAL); in sun4i_tcon_get_engine_by_id()
1000 remote = of_graph_get_remote_node(node, 0, -1); in sun4i_tcon_connected_to_tcon_top()
1020 list_for_each(pos, &drv->tcon_list) in sun4i_tcon_get_index()
1067 return ERR_PTR(-EINVAL); in sun4i_tcon_find_engine()
1081 * TCONs than engines (R40) or TCONs with non-consecutive ids. in sun4i_tcon_find_engine()
1109 struct sun4i_drv *drv = drm->dev_private; in sun4i_tcon_bind()
1117 engine = sun4i_tcon_find_engine(drv, dev->of_node); in sun4i_tcon_bind()
1120 return -EPROBE_DEFER; in sun4i_tcon_bind()
1125 return -ENOMEM; in sun4i_tcon_bind()
1127 tcon->drm = drm; in sun4i_tcon_bind()
1128 tcon->dev = dev; in sun4i_tcon_bind()
1129 tcon->id = engine->id; in sun4i_tcon_bind()
1130 tcon->quirks = of_device_get_match_data(dev); in sun4i_tcon_bind()
1132 tcon->lcd_rst = devm_reset_control_get(dev, "lcd"); in sun4i_tcon_bind()
1133 if (IS_ERR(tcon->lcd_rst)) { in sun4i_tcon_bind()
1135 return PTR_ERR(tcon->lcd_rst); in sun4i_tcon_bind()
1138 if (tcon->quirks->needs_edp_reset) { in sun4i_tcon_bind()
1153 ret = reset_control_reset(tcon->lcd_rst); in sun4i_tcon_bind()
1159 if (tcon->quirks->supports_lvds) { in sun4i_tcon_bind()
1162 * nodes without the LVDS reset properties. in sun4i_tcon_bind()
1164 * If the property is missing, just disable LVDS, and in sun4i_tcon_bind()
1167 tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds"); in sun4i_tcon_bind()
1168 if (IS_ERR(tcon->lvds_rst)) { in sun4i_tcon_bind()
1170 return PTR_ERR(tcon->lvds_rst); in sun4i_tcon_bind()
1171 } else if (tcon->lvds_rst) { in sun4i_tcon_bind()
1173 reset_control_reset(tcon->lvds_rst); in sun4i_tcon_bind()
1180 * nodes without the LVDS reset properties. in sun4i_tcon_bind()
1182 * If the property is missing, just disable LVDS, and in sun4i_tcon_bind()
1185 if (tcon->quirks->has_lvds_alt) { in sun4i_tcon_bind()
1186 tcon->lvds_pll = devm_clk_get(dev, "lvds-alt"); in sun4i_tcon_bind()
1187 if (IS_ERR(tcon->lvds_pll)) { in sun4i_tcon_bind()
1188 if (PTR_ERR(tcon->lvds_pll) == -ENOENT) { in sun4i_tcon_bind()
1191 dev_err(dev, "Couldn't get the LVDS PLL\n"); in sun4i_tcon_bind()
1192 return PTR_ERR(tcon->lvds_pll); in sun4i_tcon_bind()
1200 (tcon->quirks->has_lvds_alt && !has_lvds_alt)) { in sun4i_tcon_bind()
1201 dev_warn(dev, "Missing LVDS properties, Please upgrade your DT\n"); in sun4i_tcon_bind()
1202 dev_warn(dev, "LVDS output disabled\n"); in sun4i_tcon_bind()
1223 if (tcon->quirks->has_channel_0) { in sun4i_tcon_bind()
1237 tcon->crtc = sun4i_crtc_init(drm, engine, tcon); in sun4i_tcon_bind()
1238 if (IS_ERR(tcon->crtc)) { in sun4i_tcon_bind()
1240 ret = PTR_ERR(tcon->crtc); in sun4i_tcon_bind()
1244 if (tcon->quirks->has_channel_0) { in sun4i_tcon_bind()
1246 * If we have an LVDS panel connected to the TCON, we should in sun4i_tcon_bind()
1247 * just probe the LVDS connector. Otherwise, just probe RGB as in sun4i_tcon_bind()
1250 remote = of_graph_get_remote_node(dev->of_node, 1, 0); in sun4i_tcon_bind()
1251 if (of_device_is_compatible(remote, "panel-lvds")) in sun4i_tcon_bind()
1255 ret = -EINVAL; in sun4i_tcon_bind()
1264 if (tcon->quirks->needs_de_be_mux) { in sun4i_tcon_bind()
1275 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon_bind()
1277 tcon->id); in sun4i_tcon_bind()
1278 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon_bind()
1280 tcon->id); in sun4i_tcon_bind()
1283 list_add_tail(&tcon->list, &drv->tcon_list); in sun4i_tcon_bind()
1288 if (tcon->quirks->has_channel_0) in sun4i_tcon_bind()
1293 reset_control_assert(tcon->lcd_rst); in sun4i_tcon_bind()
1302 list_del(&tcon->list); in sun4i_tcon_unbind()
1303 if (tcon->quirks->has_channel_0) in sun4i_tcon_unbind()
1315 struct device_node *node = pdev->dev.of_node; in sun4i_tcon_probe()
1321 quirks = of_device_get_match_data(&pdev->dev); in sun4i_tcon_probe()
1324 if (quirks->has_channel_0) { in sun4i_tcon_probe()
1326 if (ret == -EPROBE_DEFER) in sun4i_tcon_probe()
1330 return component_add(&pdev->dev, &sun4i_tcon_ops); in sun4i_tcon_probe()
1335 component_del(&pdev->dev, &sun4i_tcon_ops); in sun4i_tcon_remove()
1344 struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev); in sun4i_a10_tcon_set_mux()
1348 return -EINVAL; in sun4i_a10_tcon_set_mux()
1350 switch (encoder->encoder_type) { in sun4i_a10_tcon_set_mux()
1356 return -EINVAL; in sun4i_a10_tcon_set_mux()
1359 regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG, in sun4i_a10_tcon_set_mux()
1360 0x3 << shift, tcon->id << shift); in sun4i_a10_tcon_set_mux()
1370 if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) in sun5i_a13_tcon_set_mux()
1378 return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val); in sun5i_a13_tcon_set_mux()
1384 struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev); in sun6i_tcon_set_mux()
1388 return -EINVAL; in sun6i_tcon_set_mux()
1390 switch (encoder->encoder_type) { in sun6i_tcon_set_mux()
1397 return -EINVAL; in sun6i_tcon_set_mux()
1400 regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG, in sun6i_tcon_set_mux()
1401 0x3 << shift, tcon->id << shift); in sun6i_tcon_set_mux()
1415 port = of_graph_get_port_by_id(tcon->dev->of_node, 0); in sun8i_r40_tcon_tv_set_mux()
1417 return -EINVAL; in sun8i_r40_tcon_tv_set_mux()
1422 remote = of_graph_get_remote_node(tcon->dev->of_node, 0, -1); in sun8i_r40_tcon_tv_set_mux()
1424 return -EINVAL; in sun8i_r40_tcon_tv_set_mux()
1429 return -EINVAL; in sun8i_r40_tcon_tv_set_mux()
1432 encoder->encoder_type == DRM_MODE_ENCODER_TMDS) { in sun8i_r40_tcon_tv_set_mux()
1433 ret = sun8i_tcon_top_set_hdmi_src(&pdev->dev, id); in sun8i_r40_tcon_tv_set_mux()
1435 put_device(&pdev->dev); in sun8i_r40_tcon_tv_set_mux()
1441 ret = sun8i_tcon_top_de_config(&pdev->dev, tcon->id, id); in sun8i_r40_tcon_tv_set_mux()
1443 put_device(&pdev->dev); in sun8i_r40_tcon_tv_set_mux()
1541 { .compatible = "allwinner,sun4i-a10-tcon", .data = &sun4i_a10_quirks },
1542 { .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks },
1543 { .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
1544 { .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
1545 { .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks },
1546 { .compatible = "allwinner,sun7i-a20-tcon0", .data = &sun7i_a20_tcon0_quirks },
1547 { .compatible = "allwinner,sun7i-a20-tcon1", .data = &sun7i_a20_quirks },
1548 { .compatible = "allwinner,sun8i-a23-tcon", .data = &sun8i_a33_quirks },
1549 { .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
1550 { .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
1551 { .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks },
1552 { .compatible = "allwinner,sun8i-r40-tcon-tv", .data = &sun8i_r40_tv_quirks },
1553 { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
1554 { .compatible = "allwinner,sun9i-a80-tcon-lcd", .data = &sun9i_a80_tcon_lcd_quirks },
1555 { .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
1565 .name = "sun4i-tcon",
1571 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");